[ARM] 3400/1: lpd7a40x: platform headers update
Patch from Marc Singer Updates to the lpd7a40x platform headers. Includes support for new architecture, lpd7a400. Signed-off-by: Marc Singer <elf@buici.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Marc Singer
Russell King
parent
427abfa28a
commit
2295196c30
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@ -12,6 +12,7 @@ extern struct sys_timer lh7a40x_timer;
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extern void lh7a400_init_irq (void);
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extern void lh7a404_init_irq (void);
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extern void lh7a40x_clcd_init (void);
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extern void lh7a40x_init_board_irq (void);
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#define IRQ_DISPATCH(irq) desc_handle_irq((irq),(irq_desc + irq), regs)
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@ -0,0 +1,346 @@
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/* lcd-panel.h
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$Id$
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written by Marc Singer
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18 Jul 2005
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Copyright (C) 2005 Marc Singer
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-----------
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DESCRIPTION
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-----------
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Only one panel may be defined at a time.
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The pixel clock is calculated to be no greater than the target.
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Each timing value is accompanied by a specification comment.
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UNITS/MIN/TYP/MAX
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Most of the units will be in clocks.
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USE_RGB555
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Define this macro to configure the AMBA LCD controller to use an
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RGB555 encoding for the pels instead of the normal RGB565.
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LPD9520, LPD79524, LPD7A400, LPD7A404-10, LPD7A404-11
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These boards are best approximated by 555 for all panels. Some
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can use an extra low-order bit of blue in bit 16 of the color
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value, but we don't have a way to communicate this non-linear
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mapping to the kernel.
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*/
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#if !defined (__LCD_PANEL_H__)
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# define __LCD_PANEL_H__
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#if defined (MACH_LPD79520)\
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|| defined (MACH_LPD79524)\
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|| defined (MACH_LPD7A400)\
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|| defined (MACH_LPD7A404)
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# define USE_RGB555
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#endif
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struct clcd_panel_extra {
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unsigned int hrmode;
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unsigned int clsen;
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unsigned int spsen;
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unsigned int pcdel;
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unsigned int revdel;
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unsigned int lpdel;
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unsigned int spldel;
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unsigned int pc2del;
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};
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#define NS_TO_CLOCK(ns,c) ((((ns)*((c)/1000) + (1000000 - 1))/1000000))
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#define CLOCK_TO_DIV(e,c) (((c) + (e) - 1)/(e))
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#if defined CONFIG_FB_ARMCLCD_SHARP_LQ035Q7DB02_HRTFT
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/* Logic Product Development LCD 3.5" QVGA HRTFT -10 */
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/* Sharp PN LQ035Q7DB02 w/HRTFT controller chip */
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#define PIX_CLOCK_TARGET (6800000)
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#define PIX_CLOCK_DIVIDER CLOCK_TO_DIV (PIX_CLOCK_TARGET, HCLK)
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#define PIX_CLOCK (HCLK/PIX_CLOCK_DIVIDER)
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static struct clcd_panel lcd_panel = {
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.mode = {
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.name = "3.5in QVGA (LQ035Q7DB02)",
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.xres = 240,
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.yres = 320,
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.pixclock = PIX_CLOCK,
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.left_margin = 16,
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.right_margin = 21,
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.upper_margin = 8, // line/8/8/8
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.lower_margin = 5,
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.hsync_len = 61,
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.vsync_len = NS_TO_CLOCK (60, PIX_CLOCK),
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.vmode = FB_VMODE_NONINTERLACED,
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},
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.width = -1,
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.height = -1,
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.tim2 = TIM2_IPC | (PIX_CLOCK_DIVIDER - 2),
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.cntl = CNTL_LCDTFT | CNTL_WATERMARK,
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.bpp = 16,
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};
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#define HAS_LCD_PANEL_EXTRA
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static struct clcd_panel_extra lcd_panel_extra = {
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.hrmode = 1,
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.clsen = 1,
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.spsen = 1,
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.pcdel = 8,
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.revdel = 7,
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.lpdel = 13,
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.spldel = 77,
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.pc2del = 208,
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};
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#endif
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#if defined CONFIG_FB_ARMCLCD_SHARP_LQ057Q3DC02
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/* Logic Product Development LCD 5.7" QVGA -10 */
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/* Sharp PN LQ057Q3DC02 */
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/* QVGA mode, V/Q=LOW */
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/* From Sharp on 2006.1.3. I believe some of the values are incorrect
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* based on the datasheet.
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Timing0 TIMING1 TIMING2 CONTROL
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0x140A0C4C 0x080504EF 0x013F380D 0x00000829
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HBP= 20 VBP= 8 BCD= 0
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HFP= 10 VFP= 5 CPL=319
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HSW= 12 VSW= 1 IOE= 0
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PPL= 19 LPP=239 IPC= 1
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IHS= 1
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IVS= 1
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ACB= 0
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CSEL= 0
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PCD= 13
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*/
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/* The full horozontal cycle (Th) is clock/360/400/450. */
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/* The full vertical cycle (Tv) is line/251/262/280. */
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#define PIX_CLOCK_TARGET (6300000) /* -/6.3/7 MHz */
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#define PIX_CLOCK_DIVIDER CLOCK_TO_DIV (PIX_CLOCK_TARGET, HCLK)
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#define PIX_CLOCK (HCLK/PIX_CLOCK_DIVIDER)
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static struct clcd_panel lcd_panel = {
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.mode = {
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.name = "5.7in QVGA (LQ057Q3DC02)",
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.xres = 320,
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.yres = 240,
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.pixclock = PIX_CLOCK,
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.left_margin = 11,
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.right_margin = 400-11-320-2,
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.upper_margin = 7, // line/7/7/7
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.lower_margin = 262-7-240-2,
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.hsync_len = 2, // clk/2/96/200
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.vsync_len = 2, // line/2/-/34
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.vmode = FB_VMODE_NONINTERLACED,
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},
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.width = -1,
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.height = -1,
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.tim2 = TIM2_IHS | TIM2_IVS
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| (PIX_CLOCK_DIVIDER - 2),
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.cntl = CNTL_LCDTFT | CNTL_WATERMARK,
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.bpp = 16,
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};
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#endif
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#if defined CONFIG_FB_ARMCLCD_SHARP_LQ64D343
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/* Logic Product Development LCD 6.4" VGA -10 */
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/* Sharp PN LQ64D343 */
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/* The full horozontal cycle (Th) is clock/750/800/900. */
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/* The full vertical cycle (Tv) is line/515/525/560. */
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#define PIX_CLOCK_TARGET (28330000)
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#define PIX_CLOCK_DIVIDER CLOCK_TO_DIV (PIX_CLOCK_TARGET, HCLK)
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#define PIX_CLOCK (HCLK/PIX_CLOCK_DIVIDER)
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static struct clcd_panel lcd_panel = {
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.mode = {
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.name = "6.4in QVGA (LQ64D343)",
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.xres = 640,
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.yres = 480,
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.pixclock = PIX_CLOCK,
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.left_margin = 32,
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.right_margin = 800-32-640-96,
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.upper_margin = 32, // line/34/34/34
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.lower_margin = 540-32-480-2,
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.hsync_len = 96, // clk/2/96/200
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.vsync_len = 2, // line/2/-/34
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.vmode = FB_VMODE_NONINTERLACED,
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},
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.width = -1,
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.height = -1,
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.tim2 = TIM2_IHS | TIM2_IVS
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| (PIX_CLOCK_DIVIDER - 2),
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.cntl = CNTL_LCDTFT | CNTL_WATERMARK,
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.bpp = 16,
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};
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#endif
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#if defined CONFIG_FB_ARMCLCD_SHARP_LQ10D368
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/* Logic Product Development LCD 10.4" VGA -10 */
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/* Sharp PN LQ10D368 */
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#define PIX_CLOCK_TARGET (28330000)
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#define PIX_CLOCK_DIVIDER CLOCK_TO_DIV (PIX_CLOCK_TARGET, HCLK)
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#define PIX_CLOCK (HCLK/PIX_CLOCK_DIVIDER)
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static struct clcd_panel lcd_panel = {
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.mode = {
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.name = "10.4in VGA (LQ10D368)",
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.xres = 640,
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.yres = 480,
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.pixclock = PIX_CLOCK,
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.left_margin = 21,
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.right_margin = 15,
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.upper_margin = 34,
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.lower_margin = 5,
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.hsync_len = 96,
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.vsync_len = 16,
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.vmode = FB_VMODE_NONINTERLACED,
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},
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.width = -1,
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.height = -1,
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.tim2 = TIM2_IHS | TIM2_IVS
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| (PIX_CLOCK_DIVIDER - 2),
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.cntl = CNTL_LCDTFT | CNTL_WATERMARK,
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.bpp = 16,
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};
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#endif
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#if defined CONFIG_FB_ARMCLCD_SHARP_LQ121S1DG41
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/* Logic Product Development LCD 12.1" SVGA -10 */
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/* Sharp PN LQ121S1DG41, was LQ121S1DG31 */
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/* Note that with a 99993900 Hz HCLK, it is not possible to hit the
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* target clock frequency range of 35MHz to 42MHz. */
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/* If the target pixel clock is substantially lower than the panel
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* spec, this is done to prevent the LCD display from glitching when
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* the CPU is under load. A pixel clock higher than 25MHz
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* (empirically determined) will compete with the CPU for bus cycles
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* for the Ethernet chip. However, even a pixel clock of 10MHz
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* competes with Compact Flash interface during some operations
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* (fdisk, e2fsck). And, at that speed the display may have a visible
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* flicker. */
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/* The full horozontal cycle (Th) is clock/832/1056/1395. */
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#define PIX_CLOCK_TARGET (20000000)
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#define PIX_CLOCK_DIVIDER CLOCK_TO_DIV (PIX_CLOCK_TARGET, HCLK)
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#define PIX_CLOCK (HCLK/PIX_CLOCK_DIVIDER)
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static struct clcd_panel lcd_panel = {
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.mode = {
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.name = "12.1in SVGA (LQ121S1DG41)",
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.xres = 800,
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.yres = 600,
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.pixclock = PIX_CLOCK,
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.left_margin = 89, // ns/5/-/(1/PIX_CLOCK)-10
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.right_margin = 1056-800-89-128,
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.upper_margin = 23, // line/23/23/23
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.lower_margin = 44,
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.hsync_len = 128, // clk/2/128/200
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.vsync_len = 4, // line/2/4/6
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.vmode = FB_VMODE_NONINTERLACED,
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},
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.width = -1,
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.height = -1,
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.tim2 = TIM2_IHS | TIM2_IVS
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| (PIX_CLOCK_DIVIDER - 2),
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.cntl = CNTL_LCDTFT | CNTL_WATERMARK,
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.bpp = 16,
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};
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#endif
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#if defined CONFIG_FB_ARMCLCD_HITACHI
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/* Hitachi*/
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/* Submitted by Michele Da Rold <michele.darold@ecsproject.com> */
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#define PIX_CLOCK_TARGET (49000000)
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#define PIX_CLOCK_DIVIDER CLOCK_TO_DIV (PIX_CLOCK_TARGET, HCLK)
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#define PIX_CLOCK (HCLK/PIX_CLOCK_DIVIDER)
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static struct clcd_panel lcd_panel = {
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.mode = {
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.name = "Hitachi 800x480",
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.xres = 800,
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.yres = 480,
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.pixclock = PIX_CLOCK,
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.left_margin = 88,
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.right_margin = 40,
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.upper_margin = 32,
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.lower_margin = 11,
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.hsync_len = 128,
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.vsync_len = 2,
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.vmode = FB_VMODE_NONINTERLACED,
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},
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.width = -1,
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.height = -1,
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.tim2 = TIM2_IPC | TIM2_IHS | TIM2_IVS
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| (PIX_CLOCK_DIVIDER - 2),
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.cntl = CNTL_LCDTFT | CNTL_WATERMARK,
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.bpp = 16,
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};
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#endif
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#if defined CONFIG_FB_ARMCLCD_AUO_A070VW01_WIDE
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/* AU Optotronics A070VW01 7.0 Wide Screen color Display*/
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/* Submitted by Michele Da Rold <michele.darold@ecsproject.com> */
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#define PIX_CLOCK_TARGET (10000000)
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#define PIX_CLOCK_DIVIDER CLOCK_TO_DIV (PIX_CLOCK_TARGET, HCLK)
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#define PIX_CLOCK (HCLK/PIX_CLOCK_DIVIDER)
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static struct clcd_panel lcd_panel = {
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.mode = {
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.name = "7.0in Wide (A070VW01)",
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.xres = 480,
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.yres = 234,
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.pixclock = PIX_CLOCK,
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.left_margin = 30,
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.right_margin = 25,
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.upper_margin = 14,
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.lower_margin = 12,
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.hsync_len = 100,
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.vsync_len = 1,
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.vmode = FB_VMODE_NONINTERLACED,
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},
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.width = -1,
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.height = -1,
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.tim2 = TIM2_IPC | TIM2_IHS | TIM2_IVS
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| (PIX_CLOCK_DIVIDER - 2),
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.cntl = CNTL_LCDTFT | CNTL_WATERMARK,
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.bpp = 16,
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};
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#endif
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#undef NS_TO_CLOCK
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#undef CLOCK_TO_DIV
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#endif /* __LCD_PANEL_H__ */
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@ -0,0 +1,20 @@
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/* include/asm-arm/arch-lh7a40x/clocks.h
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*
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* Copyright (C) 2004 Marc Singer
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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*
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*/
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#include <linux/config.h>
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#ifndef __ASM_ARCH_CLOCKS_H
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#define __ASM_ARCH_CLOCKS_H
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unsigned int fclkfreq_get (void);
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unsigned int hclkfreq_get (void);
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unsigned int pclkfreq_get (void);
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#endif /* _ASM_ARCH_CLOCKS_H */
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@ -29,8 +29,7 @@
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#if defined (CONFIG_MACH_LPD7A400) || defined (CONFIG_MACH_LPD7A404)
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# define IOBARRIER_PHYS 0xc0000000 /* Start of SDRAM */
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/*# define IOBARRIER_PHYS 0x00000000 */ /* Start of flash */
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# define IOBARRIER_PHYS 0x10000000 /* Second bank, fastest timing */
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# define IOBARRIER_VIRT 0xf0000000
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# define IOBARRIER_SIZE PAGE_SIZE
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@ -53,6 +52,9 @@
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# define CPLD08_PHYS CPLDX_PHYS (0x08)
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# define CPLD08_VIRT CPLDX_VIRT (0x08)
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# define CPLD08_SIZE PAGE_SIZE
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# define CPLD0A_PHYS CPLDX_PHYS (0x0a)
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# define CPLD0A_VIRT CPLDX_VIRT (0x0a)
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# define CPLD0A_SIZE PAGE_SIZE
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# define CPLD0C_PHYS CPLDX_PHYS (0x0c)
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# define CPLD0C_VIRT CPLDX_VIRT (0x0c)
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# define CPLD0C_SIZE PAGE_SIZE
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@ -84,5 +86,7 @@
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#define XTAL_IN 14745600 /* 14.7456 MHz crystal */
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#define PLL_CLOCK (XTAL_IN * 21) /* 309 MHz PLL clock */
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#define MAX_HCLK_KHZ 100000 /* HCLK max limit ~100MHz */
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#define HCLK (99993600)
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//#define HCLK (119808000)
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#endif /* __ASM_ARCH_CONSTANTS_H */
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@ -1,9 +1,86 @@
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/* include/asm-arm/arch-lh7a40x/dma.h
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*
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* Copyright (C) 2003 Coastal Environmental Systems
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* Copyright (C) 2005 Marc Singer
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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*
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*/
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typedef enum {
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DMA_M2M0 = 0,
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DMA_M2M1 = 1,
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DMA_M2P0 = 2, /* Tx */
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DMA_M2P1 = 3, /* Rx */
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DMA_M2P2 = 4, /* Tx */
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DMA_M2P3 = 5, /* Rx */
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DMA_M2P4 = 6, /* Tx - AC97 */
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DMA_M2P5 = 7, /* Rx - AC97 */
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DMA_M2P6 = 8, /* Tx */
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DMA_M2P7 = 9, /* Rx */
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} dma_device_t;
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#define DMA_LENGTH_MAX ((64*1024) - 4) /* bytes */
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#define DMAC_GCA __REG(DMAC_PHYS + 0x2b80)
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#define DMAC_GIR __REG(DMAC_PHYS + 0x2bc0)
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#define DMAC_GIR_MMI1 (1<<11)
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#define DMAC_GIR_MMI0 (1<<10)
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#define DMAC_GIR_MPI8 (1<<9)
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#define DMAC_GIR_MPI9 (1<<8)
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#define DMAC_GIR_MPI6 (1<<7)
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#define DMAC_GIR_MPI7 (1<<6)
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#define DMAC_GIR_MPI4 (1<<5)
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#define DMAC_GIR_MPI5 (1<<4)
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#define DMAC_GIR_MPI2 (1<<3)
|
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#define DMAC_GIR_MPI3 (1<<2)
|
||||
#define DMAC_GIR_MPI0 (1<<1)
|
||||
#define DMAC_GIR_MPI1 (1<<0)
|
||||
|
||||
#define DMAC_M2P0 0x0000
|
||||
#define DMAC_M2P1 0x0040
|
||||
#define DMAC_M2P2 0x0080
|
||||
#define DMAC_M2P3 0x00c0
|
||||
#define DMAC_M2P4 0x0240
|
||||
#define DMAC_M2P5 0x0200
|
||||
#define DMAC_M2P6 0x02c0
|
||||
#define DMAC_M2P7 0x0280
|
||||
#define DMAC_M2P8 0x0340
|
||||
#define DMAC_M2P9 0x0300
|
||||
#define DMAC_M2M0 0x0100
|
||||
#define DMAC_M2M1 0x0140
|
||||
|
||||
#define DMAC_P_PCONTROL(c) __REG(DMAC_PHYS + (c) + 0x00)
|
||||
#define DMAC_P_PINTERRUPT(c) __REG(DMAC_PHYS + (c) + 0x04)
|
||||
#define DMAC_P_PPALLOC(c) __REG(DMAC_PHYS + (c) + 0x08)
|
||||
#define DMAC_P_PSTATUS(c) __REG(DMAC_PHYS + (c) + 0x0c)
|
||||
#define DMAC_P_REMAIN(c) __REG(DMAC_PHYS + (c) + 0x14)
|
||||
#define DMAC_P_MAXCNT0(c) __REG(DMAC_PHYS + (c) + 0x20)
|
||||
#define DMAC_P_BASE0(c) __REG(DMAC_PHYS + (c) + 0x24)
|
||||
#define DMAC_P_CURRENT0(c) __REG(DMAC_PHYS + (c) + 0x28)
|
||||
#define DMAC_P_MAXCNT1(c) __REG(DMAC_PHYS + (c) + 0x30)
|
||||
#define DMAC_P_BASE1(c) __REG(DMAC_PHYS + (c) + 0x34)
|
||||
#define DMAC_P_CURRENT1(c) __REG(DMAC_PHYS + (c) + 0x38)
|
||||
|
||||
#define DMAC_PCONTROL_ENABLE (1<<4)
|
||||
|
||||
#define DMAC_PORT_USB 0
|
||||
#define DMAC_PORT_SDMMC 1
|
||||
#define DMAC_PORT_AC97_1 2
|
||||
#define DMAC_PORT_AC97_2 3
|
||||
#define DMAC_PORT_AC97_3 4
|
||||
#define DMAC_PORT_UART1 6
|
||||
#define DMAC_PORT_UART2 7
|
||||
#define DMAC_PORT_UART3 8
|
||||
|
||||
#define DMAC_PSTATUS_CURRSTATE_SHIFT 4
|
||||
#define DMAC_PSTATUS_CURRSTATE_MASK 0x3
|
||||
|
||||
#define DMAC_PSTATUS_NEXTBUF (1<<6)
|
||||
#define DMAC_PSTATUS_STALLRINT (1<<0)
|
||||
|
||||
#define DMAC_INT_CHE (1<<3)
|
||||
#define DMAC_INT_NFB (1<<1)
|
||||
#define DMAC_INT_STALL (1<<0)
|
||||
|
|
|
|||
|
|
@ -13,6 +13,8 @@
|
|||
#ifndef __ASM_ARCH_HARDWARE_H
|
||||
#define __ASM_ARCH_HARDWARE_H
|
||||
|
||||
#include <asm/sizes.h> /* Added for the sake of amba-clcd driver */
|
||||
|
||||
#define io_p2v(x) (0xf0000000 | (((x) & 0xfff00000) >> 4) | ((x) & 0x0000ffff))
|
||||
#define io_v2p(x) ( (((x) & 0x0fff0000) << 4) | ((x) & 0x0000ffff))
|
||||
|
||||
|
|
@ -53,6 +55,8 @@ typedef struct { volatile u8 offset[4096]; } __regbase8;
|
|||
|
||||
#endif
|
||||
|
||||
#define MASK_AND_SET(v,m,s) (v) = ((v)&~(m))|(s)
|
||||
|
||||
#include "registers.h"
|
||||
|
||||
#endif /* _ASM_ARCH_HARDWARE_H */
|
||||
|
|
|
|||
|
|
@ -154,9 +154,10 @@
|
|||
#if !defined (IRQ_GPIO0INTR)
|
||||
# define IRQ_GPIO0INTR IRQ_GPIO0FIQ
|
||||
#endif
|
||||
#define IRQ_TICK IRQ_TINTR
|
||||
#define IRQ_TICK IRQ_TINTR
|
||||
#define IRQ_PCC1_RDY IRQ_GPIO6INTR /* PCCard 1 ready */
|
||||
#define IRQ_PCC2_RDY IRQ_GPIO7INTR /* PCCard 2 ready */
|
||||
#define IRQ_USB IRQ_USBINTR /* USB device */
|
||||
|
||||
#ifdef CONFIG_MACH_KEV7A400
|
||||
# define IRQ_TS IRQ_GPIOFIQ /* Touchscreen */
|
||||
|
|
@ -191,6 +192,10 @@
|
|||
# define IRQ_LPD7A400_TS IRQ_LPD7A40X_CPLD + 1 /* Touch screen */
|
||||
#endif
|
||||
|
||||
#if defined (CONFIG_MACH_LPD7A400)
|
||||
# define IRQ_TOUCH IRQ_LPD7A400_TS
|
||||
#endif
|
||||
|
||||
#define NR_IRQS (NR_IRQ_CPU + NR_IRQ_BOARD)
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -18,7 +18,7 @@
|
|||
|
||||
/* Physical register base addresses */
|
||||
|
||||
#define AC97_PHYS (0x80000000) /* AC97 Controller */
|
||||
#define AC97C_PHYS (0x80000000) /* AC97 Controller */
|
||||
#define MMC_PHYS (0x80000100) /* Multimedia Card Controller */
|
||||
#define USB_PHYS (0x80000200) /* USB Client */
|
||||
#define SCI_PHYS (0x80000300) /* Secure Card Interface */
|
||||
|
|
@ -35,6 +35,8 @@
|
|||
#define RTC_PHYS (0x80000d00) /* Real-time Clock */
|
||||
#define GPIO_PHYS (0x80000e00) /* General Purpose IO */
|
||||
#define BMI_PHYS (0x80000f00) /* Battery Monitor Interface */
|
||||
#define HRTFTC_PHYS (0x80001000) /* High-res TFT Controller (LH7A400) */
|
||||
#define ALI_PHYS (0x80001000) /* Advanced LCD Interface (LH7A404) */
|
||||
#define WDT_PHYS (0x80001400) /* Watchdog Timer */
|
||||
#define SMC_PHYS (0x80002000) /* Static Memory Controller */
|
||||
#define SDRC_PHYS (0x80002400) /* SDRAM Controller */
|
||||
|
|
@ -43,6 +45,7 @@
|
|||
|
||||
/* Physical registers of the LH7A404 */
|
||||
|
||||
#define ADC_PHYS (0x80001300) /* A/D & Touchscreen Controller */
|
||||
#define VIC1_PHYS (0x80008000) /* Vectored Interrupt Controller 1 */
|
||||
#define USBH_PHYS (0x80009000) /* USB OHCI host controller */
|
||||
#define VIC2_PHYS (0x8000a000) /* Vectored Interrupt Controller 2 */
|
||||
|
|
@ -53,10 +56,32 @@
|
|||
|
||||
/* Clock/State Controller register */
|
||||
|
||||
#define CSC_PWRSR __REG(CSC_PHYS + 0x00) /* Reset register & ID */
|
||||
#define CSC_PWRCNT __REG(CSC_PHYS + 0x04) /* Power control */
|
||||
#define CSC_CLKSET __REG(CSC_PHYS + 0x20) /* Clock speed control */
|
||||
#define CSC_USBDRESET __REG(CSC_PHYS + 0x4c) /* USB Device resets */
|
||||
|
||||
#define CSC_PWRCNT_USBH_EN (1<<28) /* USB Host power enable */
|
||||
#define CSC_PWRCNT_DMAC_M2M1_EN (1<<27)
|
||||
#define CSC_PWRCNT_DMAC_M2M0_EN (1<<26)
|
||||
#define CSC_PWRCNT_DMAC_M2P8_EN (1<<25)
|
||||
#define CSC_PWRCNT_DMAC_M2P9_EN (1<<24)
|
||||
#define CSC_PWRCNT_DMAC_M2P6_EN (1<<23)
|
||||
#define CSC_PWRCNT_DMAC_M2P7_EN (1<<22)
|
||||
#define CSC_PWRCNT_DMAC_M2P4_EN (1<<21)
|
||||
#define CSC_PWRCNT_DMAC_M2P5_EN (1<<20)
|
||||
#define CSC_PWRCNT_DMAC_M2P2_EN (1<<19)
|
||||
#define CSC_PWRCNT_DMAC_M2P3_EN (1<<18)
|
||||
#define CSC_PWRCNT_DMAC_M2P0_EN (1<<17)
|
||||
#define CSC_PWRCNT_DMAC_M2P1_EN (1<<16)
|
||||
|
||||
#define CSC_PWRSR_CHIPMAN_SHIFT (24)
|
||||
#define CSC_PWRSR_CHIPMAN_MASK (0xff)
|
||||
#define CSC_PWRSR_CHIPID_SHIFT (16)
|
||||
#define CSC_PWRSR_CHIPID_MASK (0xff)
|
||||
|
||||
#define CSC_USBDRESET_APBRESETREG (1<<1)
|
||||
#define CSC_USBDRESET_IORESETREG (1<<0)
|
||||
|
||||
/* Interrupt Controller registers */
|
||||
|
||||
|
|
@ -109,6 +134,13 @@
|
|||
#define GPIO_GPIOFEOI __REG(GPIO_PHYS + 0x54) /* GPIO End-of-Interrupt */
|
||||
#define GPIO_GPIOINTEN __REG(GPIO_PHYS + 0x58) /* GPIO Interrupt Enable */
|
||||
#define GPIO_INTSTATUS __REG(GPIO_PHYS + 0x5c) /* GPIO Interrupt Status */
|
||||
#define GPIO_PINMUX __REG(GPIO_PHYS + 0x2c)
|
||||
#define GPIO_PADD __REG(GPIO_PHYS + 0x10)
|
||||
#define GPIO_PAD __REG(GPIO_PHYS + 0x00)
|
||||
#define GPIO_PCD __REG(GPIO_PHYS + 0x08)
|
||||
#define GPIO_PCDD __REG(GPIO_PHYS + 0x18)
|
||||
#define GPIO_PEDD __REG(GPIO_PHYS + 0x24)
|
||||
#define GPIO_PED __REG(GPIO_PHYS + 0x20)
|
||||
|
||||
|
||||
/* Static Memory Controller registers */
|
||||
|
|
@ -138,20 +170,21 @@
|
|||
#endif
|
||||
|
||||
#if defined (CONFIG_MACH_LPD7A400) || defined (CONFIG_MACH_LPD7A404)
|
||||
# define CPLD_CONTROL __REG8(CPLD02_PHYS)
|
||||
# define CPLD_SPI_DATA __REG8(CPLD06_PHYS)
|
||||
# define CPLD_SPI_CONTROL __REG8(CPLD08_PHYS)
|
||||
# define CPLD_SPI_EEPROM __REG8(CPLD0A_PHYS)
|
||||
# define CPLD_INTERRUPTS __REG8(CPLD0C_PHYS) /* IRQ mask/status */
|
||||
# define CPLD_BOOT_MODE __REG8(CPLD0E_PHYS)
|
||||
# define CPLD_FLASH __REG8(CPLD10_PHYS)
|
||||
# define CPLD_POWER_MGMT __REG8(CPLD12_PHYS)
|
||||
# define CPLD_REVISION __REG8(CPLD14_PHYS)
|
||||
# define CPLD_GPIO_EXT __REG8(CPLD16_PHYS)
|
||||
# define CPLD_GPIO_DATA __REG8(CPLD18_PHYS)
|
||||
# define CPLD_GPIO_DIR __REG8(CPLD1A_PHYS)
|
||||
#endif
|
||||
|
||||
# define CPLD_CONTROL __REG16(CPLD02_PHYS)
|
||||
# define CPLD_SPI_DATA __REG16(CPLD06_PHYS)
|
||||
# define CPLD_SPI_CONTROL __REG16(CPLD08_PHYS)
|
||||
# define CPLD_SPI_EEPROM __REG16(CPLD0A_PHYS)
|
||||
# define CPLD_INTERRUPTS __REG16(CPLD0C_PHYS) /* IRQ mask/status */
|
||||
# define CPLD_BOOT_MODE __REG16(CPLD0E_PHYS)
|
||||
# define CPLD_FLASH __REG16(CPLD10_PHYS)
|
||||
# define CPLD_POWER_MGMT __REG16(CPLD12_PHYS)
|
||||
# define CPLD_REVISION __REG16(CPLD14_PHYS)
|
||||
# define CPLD_GPIO_EXT __REG16(CPLD16_PHYS)
|
||||
# define CPLD_GPIO_DATA __REG16(CPLD18_PHYS)
|
||||
# define CPLD_GPIO_DIR __REG16(CPLD1A_PHYS)
|
||||
|
||||
#endif
|
||||
|
||||
/* Timer registers */
|
||||
|
||||
|
|
@ -190,4 +223,3 @@
|
|||
|
||||
|
||||
#endif /* _ASM_ARCH_REGISTERS_H */
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,71 @@
|
|||
/* ssp.h
|
||||
$Id$
|
||||
|
||||
written by Marc Singer
|
||||
6 Dec 2004
|
||||
|
||||
Copyright (C) 2004 Marc Singer
|
||||
|
||||
-----------
|
||||
DESCRIPTION
|
||||
-----------
|
||||
|
||||
This SSP header is available throughout the kernel, for this
|
||||
machine/architecture, because drivers that use it may be dispersed.
|
||||
|
||||
This file was cloned from the 7952x implementation. It would be
|
||||
better to share them, but we're taking an easier approach for the
|
||||
time being.
|
||||
|
||||
*/
|
||||
|
||||
#if !defined (__SSP_H__)
|
||||
# define __SSP_H__
|
||||
|
||||
/* ----- Includes */
|
||||
|
||||
/* ----- Types */
|
||||
|
||||
struct ssp_driver {
|
||||
int (*init) (void);
|
||||
void (*exit) (void);
|
||||
void (*acquire) (void);
|
||||
void (*release) (void);
|
||||
int (*configure) (int device, int mode, int speed,
|
||||
int frame_size_write, int frame_size_read);
|
||||
void (*chip_select) (int enable);
|
||||
void (*set_callbacks) (void* handle,
|
||||
irqreturn_t (*callback_tx)(void*),
|
||||
irqreturn_t (*callback_rx)(void*));
|
||||
void (*enable) (void);
|
||||
void (*disable) (void);
|
||||
// int (*save_state) (void*);
|
||||
// void (*restore_state) (void*);
|
||||
int (*read) (void);
|
||||
int (*write) (u16 data);
|
||||
int (*write_read) (u16 data);
|
||||
void (*flush) (void);
|
||||
void (*write_async) (void* pv, size_t cb);
|
||||
size_t (*write_pos) (void);
|
||||
};
|
||||
|
||||
/* These modes are only available on the LH79524 */
|
||||
#define SSP_MODE_SPI (1)
|
||||
#define SSP_MODE_SSI (2)
|
||||
#define SSP_MODE_MICROWIRE (3)
|
||||
#define SSP_MODE_I2S (4)
|
||||
|
||||
/* CPLD SPI devices */
|
||||
#define DEVICE_EEPROM 0 /* Configuration eeprom */
|
||||
#define DEVICE_MAC 1 /* MAC eeprom (LPD79524) */
|
||||
#define DEVICE_CODEC 2 /* Audio codec */
|
||||
#define DEVICE_TOUCH 3 /* Touch screen (LPD79520) */
|
||||
|
||||
/* ----- Globals */
|
||||
|
||||
/* ----- Prototypes */
|
||||
|
||||
//extern struct ssp_driver lh79520_i2s_driver;
|
||||
extern struct ssp_driver lh7a400_cpld_ssp_driver;
|
||||
|
||||
#endif /* __SSP_H__ */
|
||||
|
|
@ -16,7 +16,7 @@
|
|||
#ifndef UART_R_STATUS
|
||||
# define UART_R_STATUS (0x10)
|
||||
#endif
|
||||
#define nTxRdy (0x20) /* Not TxReady (literally Tx FIFO full) */
|
||||
#define nTxRdy (0x20) /* Not TxReady (literally Tx FIFO full) */
|
||||
|
||||
/* Access UART with physical addresses before MMU is setup */
|
||||
#define UART_STATUS (*(volatile unsigned long*) (UART2_PHYS + UART_R_STATUS))
|
||||
|
|
|
|||
Loading…
Reference in New Issue