clocksource/drivers/timer-atmel-tcb: Rework 32khz clock selection
On all the supported SoCs, the slow clock is always ATMEL_TC_TIMER_CLOCK5, avoid looking it up and pass it directly to setup_clkevents. Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Link: https://lore.kernel.org/r/20200710230813.1005150-6-alexandre.belloni@bootlin.com
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@ -346,7 +346,7 @@ static void __init tcb_setup_single_chan(struct atmel_tc *tc, int mck_divisor_id
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writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR);
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writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR);
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}
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}
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static const u8 atmel_tcb_divisors[5] = { 2, 8, 32, 128, 0, };
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static const u8 atmel_tcb_divisors[] = { 2, 8, 32, 128 };
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static const struct of_device_id atmel_tcb_of_match[] = {
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static const struct of_device_id atmel_tcb_of_match[] = {
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{ .compatible = "atmel,at91rm9200-tcb", .data = (void *)16, },
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{ .compatible = "atmel,at91rm9200-tcb", .data = (void *)16, },
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@ -362,7 +362,6 @@ static int __init tcb_clksrc_init(struct device_node *node)
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u64 (*tc_sched_clock)(void);
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u64 (*tc_sched_clock)(void);
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u32 rate, divided_rate = 0;
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u32 rate, divided_rate = 0;
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int best_divisor_idx = -1;
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int best_divisor_idx = -1;
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int clk32k_divisor_idx = -1;
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int bits;
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int bits;
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int i;
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int i;
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int ret;
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int ret;
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@ -416,12 +415,6 @@ static int __init tcb_clksrc_init(struct device_node *node)
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unsigned divisor = atmel_tcb_divisors[i];
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unsigned divisor = atmel_tcb_divisors[i];
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unsigned tmp;
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unsigned tmp;
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/* remember 32 KiHz clock for later */
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if (!divisor) {
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clk32k_divisor_idx = i;
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continue;
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}
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tmp = rate / divisor;
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tmp = rate / divisor;
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pr_debug("TC: %u / %-3u [%d] --> %u\n", rate, divisor, i, tmp);
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pr_debug("TC: %u / %-3u [%d] --> %u\n", rate, divisor, i, tmp);
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if (best_divisor_idx > 0) {
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if (best_divisor_idx > 0) {
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@ -467,7 +460,7 @@ static int __init tcb_clksrc_init(struct device_node *node)
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goto err_disable_t1;
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goto err_disable_t1;
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/* channel 2: periodic and oneshot timer support */
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/* channel 2: periodic and oneshot timer support */
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ret = setup_clkevents(&tc, clk32k_divisor_idx);
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ret = setup_clkevents(&tc, ATMEL_TC_TIMER_CLOCK5);
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if (ret)
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if (ret)
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goto err_unregister_clksrc;
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goto err_unregister_clksrc;
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