pinctrl: spear: switch plgpio to irqchip helpers
This switches the SPEAr PLGPIO driver over to using the irqchip helpers. As part of this effort, also get rid of the strange irq_base calculation and failure to use d->hwirq for obtaining a local irqchip offset. Cc: Viresh Kumar <viresh.linux@gmail.com> Cc: Shiraz Hashim <shiraz.linux.kernel@gmail.com> Cc: spear-devel@list.st.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Linus Walleij
parent
aebdc8abc9
commit
22763bf527
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@ -48,6 +48,7 @@ config PINCTRL_SPEAR1340
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config PINCTRL_SPEAR_PLGPIO
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bool "SPEAr SoC PLGPIO Controller"
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depends on GPIOLIB && PINCTRL_SPEAR
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select GPIOLIB_IRQCHIP
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help
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Say yes here to support PLGPIO controller on ST Microelectronics SPEAr
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SoCs.
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@ -11,12 +11,11 @@
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/gpio.h>
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#include <linux/gpio/driver.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/irqdomain.h>
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#include <linux/irqchip/chained_irq.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_platform.h>
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#include <linux/pinctrl/consumer.h>
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#include <linux/platform_device.h>
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#include <linux/pm.h>
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@ -54,7 +53,6 @@ struct plgpio_regs {
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*
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* lock: lock for guarding gpio registers
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* base: base address of plgpio block
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* irq_base: irq number of plgpio0
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* chip: gpio framework specific chip information structure
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* p2o: function ptr for pin to offset conversion. This is required only for
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* machines where mapping b/w pin and offset is not 1-to-1.
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@ -68,8 +66,6 @@ struct plgpio {
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spinlock_t lock;
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void __iomem *base;
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struct clk *clk;
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unsigned irq_base;
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struct irq_domain *irq_domain;
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struct gpio_chip chip;
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int (*p2o)(int pin); /* pin_to_offset */
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int (*o2p)(int offset); /* offset_to_pin */
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@ -280,21 +276,12 @@ disable_clk:
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pinctrl_free_gpio(gpio);
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}
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static int plgpio_to_irq(struct gpio_chip *chip, unsigned offset)
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{
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struct plgpio *plgpio = container_of(chip, struct plgpio, chip);
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if (IS_ERR_VALUE(plgpio->irq_base))
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return -EINVAL;
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return irq_find_mapping(plgpio->irq_domain, offset);
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}
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/* PLGPIO IRQ */
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static void plgpio_irq_disable(struct irq_data *d)
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{
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struct plgpio *plgpio = irq_data_get_irq_chip_data(d);
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int offset = d->irq - plgpio->irq_base;
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct plgpio *plgpio = container_of(gc, struct plgpio, chip);
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int offset = d->hwirq;
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unsigned long flags;
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/* get correct offset for "offset" pin */
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@ -311,8 +298,9 @@ static void plgpio_irq_disable(struct irq_data *d)
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static void plgpio_irq_enable(struct irq_data *d)
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{
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struct plgpio *plgpio = irq_data_get_irq_chip_data(d);
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int offset = d->irq - plgpio->irq_base;
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct plgpio *plgpio = container_of(gc, struct plgpio, chip);
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int offset = d->hwirq;
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unsigned long flags;
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/* get correct offset for "offset" pin */
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@ -329,8 +317,9 @@ static void plgpio_irq_enable(struct irq_data *d)
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static int plgpio_irq_set_type(struct irq_data *d, unsigned trigger)
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{
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struct plgpio *plgpio = irq_data_get_irq_chip_data(d);
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int offset = d->irq - plgpio->irq_base;
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct plgpio *plgpio = container_of(gc, struct plgpio, chip);
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int offset = d->hwirq;
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void __iomem *reg_off;
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unsigned int supported_type = 0, val;
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@ -369,7 +358,8 @@ static struct irq_chip plgpio_irqchip = {
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static void plgpio_irq_handler(unsigned irq, struct irq_desc *desc)
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{
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struct plgpio *plgpio = irq_get_handler_data(irq);
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struct gpio_chip *gc = irq_desc_get_handler_data(desc);
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struct plgpio *plgpio = container_of(gc, struct plgpio, chip);
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struct irq_chip *irqchip = irq_desc_get_chip(desc);
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int regs_count, count, pin, offset, i = 0;
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unsigned long pending;
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@ -410,7 +400,8 @@ static void plgpio_irq_handler(unsigned irq, struct irq_desc *desc)
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/* get correct irq line number */
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pin = i * MAX_GPIO_PER_REG + pin;
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generic_handle_irq(plgpio_to_irq(&plgpio->chip, pin));
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generic_handle_irq(
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irq_find_mapping(gc->irqdomain, pin));
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}
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}
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chained_irq_exit(irqchip, desc);
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@ -523,10 +514,9 @@ end:
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}
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static int plgpio_probe(struct platform_device *pdev)
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{
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struct device_node *np = pdev->dev.of_node;
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struct plgpio *plgpio;
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struct resource *res;
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int ret, irq, i;
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int ret, irq;
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plgpio = devm_kzalloc(&pdev->dev, sizeof(*plgpio), GFP_KERNEL);
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if (!plgpio) {
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@ -563,7 +553,6 @@ static int plgpio_probe(struct platform_device *pdev)
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platform_set_drvdata(pdev, plgpio);
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spin_lock_init(&plgpio->lock);
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plgpio->irq_base = -1;
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plgpio->chip.base = -1;
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plgpio->chip.request = plgpio_request;
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plgpio->chip.free = plgpio_free;
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@ -571,10 +560,10 @@ static int plgpio_probe(struct platform_device *pdev)
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plgpio->chip.direction_output = plgpio_direction_output;
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plgpio->chip.get = plgpio_get_value;
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plgpio->chip.set = plgpio_set_value;
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plgpio->chip.to_irq = plgpio_to_irq;
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plgpio->chip.label = dev_name(&pdev->dev);
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plgpio->chip.dev = &pdev->dev;
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plgpio->chip.owner = THIS_MODULE;
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plgpio->chip.of_node = pdev->dev.of_node;
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if (!IS_ERR(plgpio->clk)) {
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ret = clk_prepare(plgpio->clk);
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@ -592,35 +581,25 @@ static int plgpio_probe(struct platform_device *pdev)
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irq = platform_get_irq(pdev, 0);
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if (irq < 0) {
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dev_info(&pdev->dev, "irqs not supported\n");
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dev_info(&pdev->dev, "PLGPIO registered without IRQs\n");
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return 0;
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}
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plgpio->irq_base = irq_alloc_descs(-1, 0, plgpio->chip.ngpio, 0);
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if (IS_ERR_VALUE(plgpio->irq_base)) {
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/* we would not support irq for gpio */
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dev_warn(&pdev->dev, "couldn't allocate irq base\n");
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return 0;
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}
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plgpio->irq_domain = irq_domain_add_legacy(np, plgpio->chip.ngpio,
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plgpio->irq_base, 0, &irq_domain_simple_ops, NULL);
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if (WARN_ON(!plgpio->irq_domain)) {
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dev_err(&pdev->dev, "irq domain init failed\n");
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irq_free_descs(plgpio->irq_base, plgpio->chip.ngpio);
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ret = -ENXIO;
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ret = gpiochip_irqchip_add(&plgpio->chip,
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&plgpio_irqchip,
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0,
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handle_simple_irq,
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IRQ_TYPE_NONE);
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if (ret) {
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dev_err(&pdev->dev, "failed to add irqchip to gpiochip\n");
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goto remove_gpiochip;
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}
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irq_set_chained_handler(irq, plgpio_irq_handler);
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for (i = 0; i < plgpio->chip.ngpio; i++) {
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irq_set_chip_and_handler(i + plgpio->irq_base, &plgpio_irqchip,
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handle_simple_irq);
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set_irq_flags(i + plgpio->irq_base, IRQF_VALID);
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irq_set_chip_data(i + plgpio->irq_base, plgpio);
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}
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gpiochip_set_chained_irqchip(&plgpio->chip,
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&plgpio_irqchip,
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irq,
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plgpio_irq_handler);
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irq_set_handler_data(irq, plgpio);
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dev_info(&pdev->dev, "PLGPIO registered with IRQs\n");
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return 0;
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