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gpio: mvebu: switch to regmap for register access 

In order to be able to use this driver with the Armada 7K/8K SoCs, we
need to use the regmap to access the registers. Indeed for these new SoCs,
the gpio node will be part of a syscon.

[gregory.clement@free-electrons.com:
 - fixed merge conflcit from 4.10 to 4.12-rc1
 - added a commit log]

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Thomas Petazzoni 2017-05-19 18:09:21 +02:00 committed by Linus Walleij
parent 6ec015d613
commit 2233bf7a92
1 changed files with 246 additions and 192 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

438
drivers/gpio/gpio-mvebu.c
View File

@ -47,6 +47,7 @@
#include <linux/pinctrl/consumer.h> #include <linux/pinctrl/consumer.h>
#include <linux/platform_device.h> #include <linux/platform_device.h>
#include <linux/pwm.h> #include <linux/pwm.h>
#include <linux/regmap.h>
#include <linux/slab.h> #include <linux/slab.h>
#include "gpiolib.h" #include "gpiolib.h"
@ -106,9 +107,8 @@ struct mvebu_pwm {
struct mvebu_gpio_chip { struct mvebu_gpio_chip {
struct gpio_chip chip; struct gpio_chip chip;
spinlock_t lock; struct regmap *regs;
void __iomem *membase; struct regmap *percpu_regs;
void __iomem *percpu_membase;
int irqbase; int irqbase;
struct irq_domain *domain; struct irq_domain *domain;
int soc_variant; int soc_variant;
@ -130,92 +130,149 @@ struct mvebu_gpio_chip {
* Functions returning addresses of individual registers for a given * Functions returning addresses of individual registers for a given
* GPIO controller. * GPIO controller.
*/ */
static void __iomem *mvebu_gpioreg_out(struct mvebu_gpio_chip *mvchip)
{
return mvchip->membase + GPIO_OUT_OFF;
}
static void __iomem *mvebu_gpioreg_blink(struct mvebu_gpio_chip *mvchip) static void mvebu_gpioreg_edge_cause(struct mvebu_gpio_chip *mvchip,
{ struct regmap **map, unsigned int *offset)
return mvchip->membase + GPIO_BLINK_EN_OFF;
}
static void __iomem *mvebu_gpioreg_blink_counter_select(struct mvebu_gpio_chip
*mvchip)
{
return mvchip->membase + GPIO_BLINK_CNT_SELECT_OFF;
}
static void __iomem *mvebu_gpioreg_io_conf(struct mvebu_gpio_chip *mvchip)
{
return mvchip->membase + GPIO_IO_CONF_OFF;
}
static void __iomem *mvebu_gpioreg_in_pol(struct mvebu_gpio_chip *mvchip)
{
return mvchip->membase + GPIO_IN_POL_OFF;
}
static void __iomem *mvebu_gpioreg_data_in(struct mvebu_gpio_chip *mvchip)
{
return mvchip->membase + GPIO_DATA_IN_OFF;
}
static void __iomem *mvebu_gpioreg_edge_cause(struct mvebu_gpio_chip *mvchip)
{ {
int cpu; int cpu;
switch (mvchip->soc_variant) { switch (mvchip->soc_variant) {
case MVEBU_GPIO_SOC_VARIANT_ORION: case MVEBU_GPIO_SOC_VARIANT_ORION:
case MVEBU_GPIO_SOC_VARIANT_MV78200: case MVEBU_GPIO_SOC_VARIANT_MV78200:
return mvchip->membase + GPIO_EDGE_CAUSE_OFF; *map = mvchip->regs;
*offset = GPIO_EDGE_CAUSE_OFF;
break;
case MVEBU_GPIO_SOC_VARIANT_ARMADAXP: case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
cpu = smp_processor_id(); cpu = smp_processor_id();
return mvchip->percpu_membase + *map = mvchip->percpu_regs;
GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu); *offset = GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu);
break;
default: default:
BUG(); BUG();
} }
} }
static void __iomem *mvebu_gpioreg_edge_mask(struct mvebu_gpio_chip *mvchip) static u32
mvebu_gpio_read_edge_cause(struct mvebu_gpio_chip *mvchip)
{
struct regmap *map;
unsigned int offset;
u32 val;
mvebu_gpioreg_edge_cause(mvchip, &map, &offset);
regmap_read(map, offset, &val);
return val;
}
static void
mvebu_gpio_write_edge_cause(struct mvebu_gpio_chip *mvchip, u32 val)
{
struct regmap *map;
unsigned int offset;
mvebu_gpioreg_edge_cause(mvchip, &map, &offset);
regmap_write(map, offset, val);
}
static inline void
mvebu_gpioreg_edge_mask(struct mvebu_gpio_chip *mvchip,
struct regmap **map, unsigned int *offset)
{ {
int cpu; int cpu;
switch (mvchip->soc_variant) { switch (mvchip->soc_variant) {
case MVEBU_GPIO_SOC_VARIANT_ORION: case MVEBU_GPIO_SOC_VARIANT_ORION:
return mvchip->membase + GPIO_EDGE_MASK_OFF; *map = mvchip->regs;
*offset = GPIO_EDGE_MASK_OFF;
break;
case MVEBU_GPIO_SOC_VARIANT_MV78200: case MVEBU_GPIO_SOC_VARIANT_MV78200:
cpu = smp_processor_id(); cpu = smp_processor_id();
return mvchip->membase + GPIO_EDGE_MASK_MV78200_OFF(cpu); *map = mvchip->regs;
*offset = GPIO_EDGE_MASK_MV78200_OFF(cpu);
break;
case MVEBU_GPIO_SOC_VARIANT_ARMADAXP: case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
cpu = smp_processor_id(); cpu = smp_processor_id();
return mvchip->percpu_membase + *map = mvchip->percpu_regs;
GPIO_EDGE_MASK_ARMADAXP_OFF(cpu); *offset = GPIO_EDGE_MASK_ARMADAXP_OFF(cpu);
break;
default: default:
BUG(); BUG();
} }
} }
static void __iomem *mvebu_gpioreg_level_mask(struct mvebu_gpio_chip *mvchip) static u32
mvebu_gpio_read_edge_mask(struct mvebu_gpio_chip *mvchip)
{
struct regmap *map;
unsigned int offset;
u32 val;
mvebu_gpioreg_edge_mask(mvchip, &map, &offset);
regmap_read(map, offset, &val);
return val;
}
static void
mvebu_gpio_write_edge_mask(struct mvebu_gpio_chip *mvchip, u32 val)
{
struct regmap *map;
unsigned int offset;
mvebu_gpioreg_edge_mask(mvchip, &map, &offset);
regmap_write(map, offset, val);
}
static void
mvebu_gpioreg_level_mask(struct mvebu_gpio_chip *mvchip,
struct regmap **map, unsigned int *offset)
{ {
int cpu; int cpu;
switch (mvchip->soc_variant) { switch (mvchip->soc_variant) {
case MVEBU_GPIO_SOC_VARIANT_ORION: case MVEBU_GPIO_SOC_VARIANT_ORION:
return mvchip->membase + GPIO_LEVEL_MASK_OFF; *map = mvchip->regs;
*offset = GPIO_LEVEL_MASK_OFF;
break;
case MVEBU_GPIO_SOC_VARIANT_MV78200: case MVEBU_GPIO_SOC_VARIANT_MV78200:
cpu = smp_processor_id(); cpu = smp_processor_id();
return mvchip->membase + GPIO_LEVEL_MASK_MV78200_OFF(cpu); *map = mvchip->regs;
*offset = GPIO_LEVEL_MASK_MV78200_OFF(cpu);
break;
case MVEBU_GPIO_SOC_VARIANT_ARMADAXP: case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
cpu = smp_processor_id(); cpu = smp_processor_id();
return mvchip->percpu_membase + *map = mvchip->percpu_regs;
GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu); *offset = GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu);
break;
default: default:
BUG(); BUG();
} }
} }
static u32
mvebu_gpio_read_level_mask(struct mvebu_gpio_chip *mvchip)
{
struct regmap *map;
unsigned int offset;
u32 val;
mvebu_gpioreg_level_mask(mvchip, &map, &offset);
regmap_read(map, offset, &val);
return val;
}
static void
mvebu_gpio_write_level_mask(struct mvebu_gpio_chip *mvchip, u32 val)
{
struct regmap *map;
unsigned int offset;
mvebu_gpioreg_level_mask(mvchip, &map, &offset);
regmap_write(map, offset, val);
}
/* /*
* Functions returning addresses of individual registers for a given * Functions returning addresses of individual registers for a given
* PWM controller. * PWM controller.
@ -236,17 +293,9 @@ static void __iomem *mvebu_pwmreg_blink_off_duration(struct mvebu_pwm *mvpwm)
static void mvebu_gpio_set(struct gpio_chip *chip, unsigned int pin, int value) static void mvebu_gpio_set(struct gpio_chip *chip, unsigned int pin, int value)
{ {
struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip); struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
unsigned long flags;
u32 u;
spin_lock_irqsave(&mvchip->lock, flags); regmap_update_bits(mvchip->regs, GPIO_OUT_OFF,
u = readl_relaxed(mvebu_gpioreg_out(mvchip)); BIT(pin), value ? BIT(pin) : 0);
if (value)
u |= BIT(pin);
else
u &= ~BIT(pin);
writel_relaxed(u, mvebu_gpioreg_out(mvchip));
spin_unlock_irqrestore(&mvchip->lock, flags);
} }
static int mvebu_gpio_get(struct gpio_chip *chip, unsigned int pin) static int mvebu_gpio_get(struct gpio_chip *chip, unsigned int pin)
@ -254,11 +303,16 @@ static int mvebu_gpio_get(struct gpio_chip *chip, unsigned int pin)
struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip); struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
u32 u; u32 u;
if (readl_relaxed(mvebu_gpioreg_io_conf(mvchip)) & BIT(pin)) { regmap_read(mvchip->regs, GPIO_IO_CONF_OFF, &u);
u = readl_relaxed(mvebu_gpioreg_data_in(mvchip)) ^
readl_relaxed(mvebu_gpioreg_in_pol(mvchip)); if (u & BIT(pin)) {
u32 data_in, in_pol;
regmap_read(mvchip->regs, GPIO_DATA_IN_OFF, &data_in);
regmap_read(mvchip->regs, GPIO_IN_POL_OFF, &in_pol);
u = data_in ^ in_pol;
} else { } else {
u = readl_relaxed(mvebu_gpioreg_out(mvchip)); regmap_read(mvchip->regs, GPIO_OUT_OFF, &u);
} }
return (u >> pin) & 1; return (u >> pin) & 1;
@ -268,25 +322,15 @@ static void mvebu_gpio_blink(struct gpio_chip *chip, unsigned int pin,
int value) int value)
{ {
struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip); struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
unsigned long flags;
u32 u;
spin_lock_irqsave(&mvchip->lock, flags); regmap_update_bits(mvchip->regs, GPIO_BLINK_EN_OFF,
u = readl_relaxed(mvebu_gpioreg_blink(mvchip)); BIT(pin), value ? BIT(pin) : 0);
if (value)
u |= BIT(pin);
else
u &= ~BIT(pin);
writel_relaxed(u, mvebu_gpioreg_blink(mvchip));
spin_unlock_irqrestore(&mvchip->lock, flags);
} }
static int mvebu_gpio_direction_input(struct gpio_chip *chip, unsigned int pin) static int mvebu_gpio_direction_input(struct gpio_chip *chip, unsigned int pin)
{ {
struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip); struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
unsigned long flags;
int ret; int ret;
u32 u;
/* /*
* Check with the pinctrl driver whether this pin is usable as * Check with the pinctrl driver whether this pin is usable as
@ -296,11 +340,8 @@ static int mvebu_gpio_direction_input(struct gpio_chip *chip, unsigned int pin)
if (ret) if (ret)
return ret; return ret;
spin_lock_irqsave(&mvchip->lock, flags); regmap_update_bits(mvchip->regs, GPIO_IO_CONF_OFF,
u = readl_relaxed(mvebu_gpioreg_io_conf(mvchip)); BIT(pin), 1);
u |= BIT(pin);
writel_relaxed(u, mvebu_gpioreg_io_conf(mvchip));
spin_unlock_irqrestore(&mvchip->lock, flags);
return 0; return 0;
} }
@ -309,9 +350,7 @@ static int mvebu_gpio_direction_output(struct gpio_chip *chip, unsigned int pin,
int value) int value)
{ {
struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip); struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
unsigned long flags;
int ret; int ret;
u32 u;
/* /*
* Check with the pinctrl driver whether this pin is usable as * Check with the pinctrl driver whether this pin is usable as
@ -324,11 +363,8 @@ static int mvebu_gpio_direction_output(struct gpio_chip *chip, unsigned int pin,
mvebu_gpio_blink(chip, pin, 0); mvebu_gpio_blink(chip, pin, 0);
mvebu_gpio_set(chip, pin, value); mvebu_gpio_set(chip, pin, value);
spin_lock_irqsave(&mvchip->lock, flags); regmap_update_bits(mvchip->regs, GPIO_IO_CONF_OFF,
u = readl_relaxed(mvebu_gpioreg_io_conf(mvchip)); BIT(pin), 0);
u &= ~BIT(pin);
writel_relaxed(u, mvebu_gpioreg_io_conf(mvchip));
spin_unlock_irqrestore(&mvchip->lock, flags);
return 0; return 0;
} }
@ -350,7 +386,7 @@ static void mvebu_gpio_irq_ack(struct irq_data *d)
u32 mask = d->mask; u32 mask = d->mask;
irq_gc_lock(gc); irq_gc_lock(gc);
writel_relaxed(~mask, mvebu_gpioreg_edge_cause(mvchip)); mvebu_gpio_write_edge_cause(mvchip, ~mask);
irq_gc_unlock(gc); irq_gc_unlock(gc);
} }
@ -363,8 +399,7 @@ static void mvebu_gpio_edge_irq_mask(struct irq_data *d)
irq_gc_lock(gc); irq_gc_lock(gc);
ct->mask_cache_priv &= ~mask; ct->mask_cache_priv &= ~mask;
mvebu_gpio_write_edge_mask(mvchip, ct->mask_cache_priv);
writel_relaxed(ct->mask_cache_priv, mvebu_gpioreg_edge_mask(mvchip));
irq_gc_unlock(gc); irq_gc_unlock(gc);
} }
@ -377,7 +412,7 @@ static void mvebu_gpio_edge_irq_unmask(struct irq_data *d)
irq_gc_lock(gc); irq_gc_lock(gc);
ct->mask_cache_priv |= mask; ct->mask_cache_priv |= mask;
writel_relaxed(ct->mask_cache_priv, mvebu_gpioreg_edge_mask(mvchip)); mvebu_gpio_write_edge_mask(mvchip, ct->mask_cache_priv);
irq_gc_unlock(gc); irq_gc_unlock(gc);
} }
@ -390,7 +425,7 @@ static void mvebu_gpio_level_irq_mask(struct irq_data *d)
irq_gc_lock(gc); irq_gc_lock(gc);
ct->mask_cache_priv &= ~mask; ct->mask_cache_priv &= ~mask;
writel_relaxed(ct->mask_cache_priv, mvebu_gpioreg_level_mask(mvchip)); mvebu_gpio_write_level_mask(mvchip, ct->mask_cache_priv);
irq_gc_unlock(gc); irq_gc_unlock(gc);
} }
@ -403,7 +438,7 @@ static void mvebu_gpio_level_irq_unmask(struct irq_data *d)
irq_gc_lock(gc); irq_gc_lock(gc);
ct->mask_cache_priv |= mask; ct->mask_cache_priv |= mask;
writel_relaxed(ct->mask_cache_priv, mvebu_gpioreg_level_mask(mvchip)); mvebu_gpio_write_level_mask(mvchip, ct->mask_cache_priv);
irq_gc_unlock(gc); irq_gc_unlock(gc);
} }
@ -443,8 +478,8 @@ static int mvebu_gpio_irq_set_type(struct irq_data *d, unsigned int type)
pin = d->hwirq; pin = d->hwirq;
u = readl_relaxed(mvebu_gpioreg_io_conf(mvchip)) & BIT(pin); regmap_read(mvchip->regs, GPIO_IO_CONF_OFF, &u);
if (!u) if ((u & BIT(pin)) == 0)
return -EINVAL; return -EINVAL;
type &= IRQ_TYPE_SENSE_MASK; type &= IRQ_TYPE_SENSE_MASK;
@ -462,31 +497,30 @@ static int mvebu_gpio_irq_set_type(struct irq_data *d, unsigned int type)
switch (type) { switch (type) {
case IRQ_TYPE_EDGE_RISING: case IRQ_TYPE_EDGE_RISING:
case IRQ_TYPE_LEVEL_HIGH: case IRQ_TYPE_LEVEL_HIGH:
u = readl_relaxed(mvebu_gpioreg_in_pol(mvchip)); regmap_update_bits(mvchip->regs, GPIO_IN_POL_OFF,
u &= ~BIT(pin); BIT(pin), 0);
writel_relaxed(u, mvebu_gpioreg_in_pol(mvchip));
break; break;
case IRQ_TYPE_EDGE_FALLING: case IRQ_TYPE_EDGE_FALLING:
case IRQ_TYPE_LEVEL_LOW: case IRQ_TYPE_LEVEL_LOW:
u = readl_relaxed(mvebu_gpioreg_in_pol(mvchip)); regmap_update_bits(mvchip->regs, GPIO_IN_POL_OFF,
u |= BIT(pin); BIT(pin), 1);
writel_relaxed(u, mvebu_gpioreg_in_pol(mvchip));
break; break;
case IRQ_TYPE_EDGE_BOTH: { case IRQ_TYPE_EDGE_BOTH: {
u32 v; u32 data_in, in_pol, val;
v = readl_relaxed(mvebu_gpioreg_in_pol(mvchip)) ^ regmap_read(mvchip->regs, GPIO_IN_POL_OFF, &in_pol);
readl_relaxed(mvebu_gpioreg_data_in(mvchip)); regmap_read(mvchip->regs, GPIO_DATA_IN_OFF, &data_in);
/* /*
* set initial polarity based on current input level * set initial polarity based on current input level
*/ */
u = readl_relaxed(mvebu_gpioreg_in_pol(mvchip)); if ((data_in ^ in_pol) & BIT(pin))
if (v & BIT(pin)) val = BIT(pin); /* falling */
u |= BIT(pin); /* falling */
else else
u &= ~BIT(pin); /* rising */ val = 0; /* raising */
writel_relaxed(u, mvebu_gpioreg_in_pol(mvchip));
regmap_update_bits(mvchip->regs, GPIO_IN_POL_OFF,
BIT(pin), val);
break; break;
} }
} }
@ -497,7 +531,7 @@ static void mvebu_gpio_irq_handler(struct irq_desc *desc)
{ {
struct mvebu_gpio_chip *mvchip = irq_desc_get_handler_data(desc); struct mvebu_gpio_chip *mvchip = irq_desc_get_handler_data(desc);
struct irq_chip *chip = irq_desc_get_chip(desc); struct irq_chip *chip = irq_desc_get_chip(desc);
u32 cause, type; u32 cause, type, data_in, level_mask, edge_cause, edge_mask;
int i; int i;
if (mvchip == NULL) if (mvchip == NULL)
@ -505,10 +539,12 @@ static void mvebu_gpio_irq_handler(struct irq_desc *desc)
chained_irq_enter(chip, desc); chained_irq_enter(chip, desc);
cause = readl_relaxed(mvebu_gpioreg_data_in(mvchip)) & regmap_read(mvchip->regs, GPIO_DATA_IN_OFF, &data_in);
readl_relaxed(mvebu_gpioreg_level_mask(mvchip)); level_mask = mvebu_gpio_read_level_mask(mvchip);
cause |= readl_relaxed(mvebu_gpioreg_edge_cause(mvchip)) & edge_cause = mvebu_gpio_read_edge_cause(mvchip);
readl_relaxed(mvebu_gpioreg_edge_mask(mvchip)); edge_mask = mvebu_gpio_read_edge_mask(mvchip);
cause = (data_in ^ level_mask) | (edge_cause & edge_mask);
for (i = 0; i < mvchip->chip.ngpio; i++) { for (i = 0; i < mvchip->chip.ngpio; i++) {
int irq; int irq;
@ -523,9 +559,9 @@ static void mvebu_gpio_irq_handler(struct irq_desc *desc)
/* Swap polarity (race with GPIO line) */ /* Swap polarity (race with GPIO line) */
u32 polarity; u32 polarity;
polarity = readl_relaxed(mvebu_gpioreg_in_pol(mvchip)); regmap_read(mvchip->regs, GPIO_IN_POL_OFF, &polarity);
polarity ^= BIT(i); polarity ^= BIT(i);
writel_relaxed(polarity, mvebu_gpioreg_in_pol(mvchip)); regmap_write(mvchip->regs, GPIO_IN_POL_OFF, polarity);
} }
generic_handle_irq(irq); generic_handle_irq(irq);
@ -628,7 +664,7 @@ static void mvebu_pwm_get_state(struct pwm_chip *chip,
state->period = 1; state->period = 1;
} }
u = readl_relaxed(mvebu_gpioreg_blink(mvchip)); regmap_read(mvchip->regs, GPIO_BLINK_EN_OFF, &u);
if (u) if (u)
state->enabled = true; state->enabled = true;
else else
@ -691,8 +727,8 @@ static void __maybe_unused mvebu_pwm_suspend(struct mvebu_gpio_chip *mvchip)
{ {
struct mvebu_pwm *mvpwm = mvchip->mvpwm; struct mvebu_pwm *mvpwm = mvchip->mvpwm;
mvpwm->blink_select = regmap_read(mvchip->regs, GPIO_BLINK_CNT_SELECT_OFF,
readl_relaxed(mvebu_gpioreg_blink_counter_select(mvchip)); &mvpwm->blink_select);
mvpwm->blink_on_duration = mvpwm->blink_on_duration =
readl_relaxed(mvebu_pwmreg_blink_on_duration(mvpwm)); readl_relaxed(mvebu_pwmreg_blink_on_duration(mvpwm));
mvpwm->blink_off_duration = mvpwm->blink_off_duration =
@ -703,8 +739,8 @@ static void __maybe_unused mvebu_pwm_resume(struct mvebu_gpio_chip *mvchip)
{ {
struct mvebu_pwm *mvpwm = mvchip->mvpwm; struct mvebu_pwm *mvpwm = mvchip->mvpwm;
writel_relaxed(mvpwm->blink_select, regmap_write(mvchip->regs, GPIO_BLINK_CNT_SELECT_OFF,
mvebu_gpioreg_blink_counter_select(mvchip)); mvpwm->blink_select);
writel_relaxed(mvpwm->blink_on_duration, writel_relaxed(mvpwm->blink_on_duration,
mvebu_pwmreg_blink_on_duration(mvpwm)); mvebu_pwmreg_blink_on_duration(mvpwm));
writel_relaxed(mvpwm->blink_off_duration, writel_relaxed(mvpwm->blink_off_duration,
@ -747,7 +783,7 @@ static int mvebu_pwm_probe(struct platform_device *pdev,
set = U32_MAX; set = U32_MAX;
else else
return -EINVAL; return -EINVAL;
writel_relaxed(0, mvebu_gpioreg_blink_counter_select(mvchip)); regmap_write(mvchip->regs, GPIO_BLINK_CNT_SELECT_OFF, 0);
mvpwm = devm_kzalloc(dev, sizeof(struct mvebu_pwm), GFP_KERNEL); mvpwm = devm_kzalloc(dev, sizeof(struct mvebu_pwm), GFP_KERNEL);
if (!mvpwm) if (!mvpwm)
@ -783,14 +819,14 @@ static void mvebu_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
u32 out, io_conf, blink, in_pol, data_in, cause, edg_msk, lvl_msk; u32 out, io_conf, blink, in_pol, data_in, cause, edg_msk, lvl_msk;
int i; int i;
out = readl_relaxed(mvebu_gpioreg_out(mvchip)); regmap_read(mvchip->regs, GPIO_OUT_OFF, &out);
io_conf = readl_relaxed(mvebu_gpioreg_io_conf(mvchip)); regmap_read(mvchip->regs, GPIO_IO_CONF_OFF, &io_conf);
blink = readl_relaxed(mvebu_gpioreg_blink(mvchip)); regmap_read(mvchip->regs, GPIO_BLINK_EN_OFF, &blink);
in_pol = readl_relaxed(mvebu_gpioreg_in_pol(mvchip)); regmap_read(mvchip->regs, GPIO_IN_POL_OFF, &in_pol);
data_in = readl_relaxed(mvebu_gpioreg_data_in(mvchip)); regmap_read(mvchip->regs, GPIO_DATA_IN_OFF, &data_in);
cause = readl_relaxed(mvebu_gpioreg_edge_cause(mvchip)); cause = mvebu_gpio_read_edge_cause(mvchip);
edg_msk = readl_relaxed(mvebu_gpioreg_edge_mask(mvchip)); edg_msk = mvebu_gpio_read_edge_mask(mvchip);
lvl_msk = readl_relaxed(mvebu_gpioreg_level_mask(mvchip)); lvl_msk = mvebu_gpio_read_level_mask(mvchip);
for (i = 0; i < chip->ngpio; i++) { for (i = 0; i < chip->ngpio; i++) {
const char *label; const char *label;
@ -858,36 +894,36 @@ static int mvebu_gpio_suspend(struct platform_device *pdev, pm_message_t state)
struct mvebu_gpio_chip *mvchip = platform_get_drvdata(pdev); struct mvebu_gpio_chip *mvchip = platform_get_drvdata(pdev);
int i; int i;
mvchip->out_reg = readl(mvebu_gpioreg_out(mvchip)); regmap_read(mvchip->regs, GPIO_OUT_OFF, &mvchip->out_reg);
mvchip->io_conf_reg = readl(mvebu_gpioreg_io_conf(mvchip)); regmap_read(mvchip->regs, GPIO_IO_CONF_OFF, &mvchip->io_conf_reg);
mvchip->blink_en_reg = readl(mvebu_gpioreg_blink(mvchip)); regmap_read(mvchip->regs, GPIO_BLINK_EN_OFF, &mvchip->blink_en_reg);
mvchip->in_pol_reg = readl(mvebu_gpioreg_in_pol(mvchip)); regmap_read(mvchip->regs, GPIO_IN_POL_OFF, &mvchip->in_pol_reg);
switch (mvchip->soc_variant) { switch (mvchip->soc_variant) {
case MVEBU_GPIO_SOC_VARIANT_ORION: case MVEBU_GPIO_SOC_VARIANT_ORION:
mvchip->edge_mask_regs[0] = regmap_read(mvchip->regs, GPIO_EDGE_MASK_OFF,
readl(mvchip->membase + GPIO_EDGE_MASK_OFF); &mvchip->edge_mask_regs[0]);
mvchip->level_mask_regs[0] = regmap_read(mvchip->regs, GPIO_LEVEL_MASK_OFF,
readl(mvchip->membase + GPIO_LEVEL_MASK_OFF); &mvchip->level_mask_regs[0]);
break; break;
case MVEBU_GPIO_SOC_VARIANT_MV78200: case MVEBU_GPIO_SOC_VARIANT_MV78200:
for (i = 0; i < 2; i++) { for (i = 0; i < 2; i++) {
mvchip->edge_mask_regs[i] = regmap_read(mvchip->regs,
readl(mvchip->membase + GPIO_EDGE_MASK_MV78200_OFF(i),
GPIO_EDGE_MASK_MV78200_OFF(i)); &mvchip->edge_mask_regs[i]);
mvchip->level_mask_regs[i] = regmap_read(mvchip->regs,
readl(mvchip->membase + GPIO_LEVEL_MASK_MV78200_OFF(i),
GPIO_LEVEL_MASK_MV78200_OFF(i)); &mvchip->level_mask_regs[i]);
} }
break; break;
case MVEBU_GPIO_SOC_VARIANT_ARMADAXP: case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
for (i = 0; i < 4; i++) { for (i = 0; i < 4; i++) {
mvchip->edge_mask_regs[i] = regmap_read(mvchip->regs,
readl(mvchip->membase + GPIO_EDGE_MASK_ARMADAXP_OFF(i),
GPIO_EDGE_MASK_ARMADAXP_OFF(i)); &mvchip->edge_mask_regs[i]);
mvchip->level_mask_regs[i] = regmap_read(mvchip->regs,
readl(mvchip->membase + GPIO_LEVEL_MASK_ARMADAXP_OFF(i),
GPIO_LEVEL_MASK_ARMADAXP_OFF(i)); &mvchip->level_mask_regs[i]);
} }
break; break;
default: default:
@ -905,35 +941,36 @@ static int mvebu_gpio_resume(struct platform_device *pdev)
struct mvebu_gpio_chip *mvchip = platform_get_drvdata(pdev); struct mvebu_gpio_chip *mvchip = platform_get_drvdata(pdev);
int i; int i;
writel(mvchip->out_reg, mvebu_gpioreg_out(mvchip)); regmap_write(mvchip->regs, GPIO_OUT_OFF, mvchip->out_reg);
writel(mvchip->io_conf_reg, mvebu_gpioreg_io_conf(mvchip)); regmap_write(mvchip->regs, GPIO_IO_CONF_OFF, mvchip->io_conf_reg);
writel(mvchip->blink_en_reg, mvebu_gpioreg_blink(mvchip)); regmap_write(mvchip->regs, GPIO_BLINK_EN_OFF, mvchip->blink_en_reg);
writel(mvchip->in_pol_reg, mvebu_gpioreg_in_pol(mvchip)); regmap_write(mvchip->regs, GPIO_IN_POL_OFF, mvchip->in_pol_reg);
switch (mvchip->soc_variant) { switch (mvchip->soc_variant) {
case MVEBU_GPIO_SOC_VARIANT_ORION: case MVEBU_GPIO_SOC_VARIANT_ORION:
writel(mvchip->edge_mask_regs[0], regmap_write(mvchip->regs, GPIO_EDGE_MASK_OFF,
mvchip->membase + GPIO_EDGE_MASK_OFF); mvchip->edge_mask_regs[0]);
writel(mvchip->level_mask_regs[0], regmap_write(mvchip->regs, GPIO_LEVEL_MASK_OFF,
mvchip->membase + GPIO_LEVEL_MASK_OFF); mvchip->level_mask_regs[0]);
break; break;
case MVEBU_GPIO_SOC_VARIANT_MV78200: case MVEBU_GPIO_SOC_VARIANT_MV78200:
for (i = 0; i < 2; i++) { for (i = 0; i < 2; i++) {
writel(mvchip->edge_mask_regs[i], regmap_write(mvchip->regs,
mvchip->membase + GPIO_EDGE_MASK_MV78200_OFF(i)); GPIO_EDGE_MASK_MV78200_OFF(i),
writel(mvchip->level_mask_regs[i], mvchip->edge_mask_regs[i]);
mvchip->membase + regmap_write(mvchip->regs,
GPIO_LEVEL_MASK_MV78200_OFF(i)); GPIO_LEVEL_MASK_MV78200_OFF(i),
mvchip->level_mask_regs[i]);
} }
break; break;
case MVEBU_GPIO_SOC_VARIANT_ARMADAXP: case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
for (i = 0; i < 4; i++) { for (i = 0; i < 4; i++) {
writel(mvchip->edge_mask_regs[i], regmap_write(mvchip->regs,
mvchip->membase + GPIO_EDGE_MASK_ARMADAXP_OFF(i),
GPIO_EDGE_MASK_ARMADAXP_OFF(i)); mvchip->edge_mask_regs[i]);
writel(mvchip->level_mask_regs[i], regmap_write(mvchip->regs,
mvchip->membase + GPIO_LEVEL_MASK_ARMADAXP_OFF(i),
GPIO_LEVEL_MASK_ARMADAXP_OFF(i)); mvchip->level_mask_regs[i]);
} }
break; break;
default: default:
@ -946,6 +983,13 @@ static int mvebu_gpio_resume(struct platform_device *pdev)
return 0; return 0;
} }
static const struct regmap_config mvebu_gpio_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.fast_io = true,
};
static int mvebu_gpio_probe(struct platform_device *pdev) static int mvebu_gpio_probe(struct platform_device *pdev)
{ {
struct mvebu_gpio_chip *mvchip; struct mvebu_gpio_chip *mvchip;
@ -954,6 +998,7 @@ static int mvebu_gpio_probe(struct platform_device *pdev)
struct resource *res; struct resource *res;
struct irq_chip_generic *gc; struct irq_chip_generic *gc;
struct irq_chip_type *ct; struct irq_chip_type *ct;
void __iomem *base;
unsigned int ngpios; unsigned int ngpios;
bool have_irqs; bool have_irqs;
int soc_variant; int soc_variant;
@ -1009,11 +1054,15 @@ static int mvebu_gpio_probe(struct platform_device *pdev)
mvchip->chip.of_node = np; mvchip->chip.of_node = np;
mvchip->chip.dbg_show = mvebu_gpio_dbg_show; mvchip->chip.dbg_show = mvebu_gpio_dbg_show;
spin_lock_init(&mvchip->lock);
res = platform_get_resource(pdev, IORESOURCE_MEM, 0); res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
mvchip->membase = devm_ioremap_resource(&pdev->dev, res); base = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(mvchip->membase)) if (IS_ERR(base))
return PTR_ERR(mvchip->membase); return PTR_ERR(base);
mvchip->regs = devm_regmap_init_mmio(&pdev->dev, base,
&mvebu_gpio_regmap_config);
if (IS_ERR(mvchip->regs))
return PTR_ERR(mvchip->regs);
/* /*
* The Armada XP has a second range of registers for the * The Armada XP has a second range of registers for the
@ -1021,10 +1070,15 @@ static int mvebu_gpio_probe(struct platform_device *pdev)
*/ */
if (soc_variant == MVEBU_GPIO_SOC_VARIANT_ARMADAXP) { if (soc_variant == MVEBU_GPIO_SOC_VARIANT_ARMADAXP) {
res = platform_get_resource(pdev, IORESOURCE_MEM, 1); res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
mvchip->percpu_membase = devm_ioremap_resource(&pdev->dev, base = devm_ioremap_resource(&pdev->dev, res);
res); if (IS_ERR(base))
if (IS_ERR(mvchip->percpu_membase)) return PTR_ERR(base);
return PTR_ERR(mvchip->percpu_membase);
mvchip->percpu_regs =
devm_regmap_init_mmio(&pdev->dev, base,
&mvebu_gpio_regmap_config);
if (IS_ERR(mvchip->percpu_regs))
return PTR_ERR(mvchip->percpu_regs);
} }
/* /*
@ -1032,30 +1086,30 @@ static int mvebu_gpio_probe(struct platform_device *pdev)
*/ */
switch (soc_variant) { switch (soc_variant) {
case MVEBU_GPIO_SOC_VARIANT_ORION: case MVEBU_GPIO_SOC_VARIANT_ORION:
writel_relaxed(0, mvchip->membase + GPIO_EDGE_CAUSE_OFF); regmap_write(mvchip->regs, GPIO_EDGE_CAUSE_OFF, 0);
writel_relaxed(0, mvchip->membase + GPIO_EDGE_MASK_OFF); regmap_write(mvchip->regs, GPIO_EDGE_MASK_OFF, 0);
writel_relaxed(0, mvchip->membase + GPIO_LEVEL_MASK_OFF); regmap_write(mvchip->regs, GPIO_LEVEL_MASK_OFF, 0);
break; break;
case MVEBU_GPIO_SOC_VARIANT_MV78200: case MVEBU_GPIO_SOC_VARIANT_MV78200:
writel_relaxed(0, mvchip->membase + GPIO_EDGE_CAUSE_OFF); regmap_write(mvchip->regs, GPIO_EDGE_CAUSE_OFF, 0);
for (cpu = 0; cpu < 2; cpu++) { for (cpu = 0; cpu < 2; cpu++) {
writel_relaxed(0, mvchip->membase + regmap_write(mvchip->regs,
GPIO_EDGE_MASK_MV78200_OFF(cpu)); GPIO_EDGE_MASK_MV78200_OFF(cpu), 0);
writel_relaxed(0, mvchip->membase + regmap_write(mvchip->regs,
GPIO_LEVEL_MASK_MV78200_OFF(cpu)); GPIO_LEVEL_MASK_MV78200_OFF(cpu), 0);
} }
break; break;
case MVEBU_GPIO_SOC_VARIANT_ARMADAXP: case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
writel_relaxed(0, mvchip->membase + GPIO_EDGE_CAUSE_OFF); regmap_write(mvchip->regs, GPIO_EDGE_CAUSE_OFF, 0);
writel_relaxed(0, mvchip->membase + GPIO_EDGE_MASK_OFF); regmap_write(mvchip->regs, GPIO_EDGE_MASK_OFF, 0);
writel_relaxed(0, mvchip->membase + GPIO_LEVEL_MASK_OFF); regmap_write(mvchip->regs, GPIO_LEVEL_MASK_OFF, 0);
for (cpu = 0; cpu < 4; cpu++) { for (cpu = 0; cpu < 4; cpu++) {
writel_relaxed(0, mvchip->percpu_membase + regmap_write(mvchip->percpu_regs,
GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu)); GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu), 0);
writel_relaxed(0, mvchip->percpu_membase + regmap_write(mvchip->percpu_regs,
GPIO_EDGE_MASK_ARMADAXP_OFF(cpu)); GPIO_EDGE_MASK_ARMADAXP_OFF(cpu), 0);
writel_relaxed(0, mvchip->percpu_membase + regmap_write(mvchip->percpu_regs,
GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu)); GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu), 0);
} }
break; break;
default: default: