ARM: mach-bcm: soc updates for 3.17
- BCM Mobile SMP support - BRCM STB platform support -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJT1mChAAoJEOfTILNwq7R4DDYQAJudlSqjwerAjQZwcdoe/xmP 74LjnWeCU3l1PhvtTynjPz3YWp+6VsHPDiHwJ00/ZTotCaa3Nl+zs5EbKs4aDeIb R6YvvIJ4bmAaStmiWV32gM9UzC+4VGV8RsI8zbsbLFLhh6ChMYs47xTyLFeXd9Ks 999CW2T+TIQmvJHhD9hmpVFf6s+TWeDpS1VKagPeZAz1tTB7XTqKItQNalrobi+b j4ak0Qsg/cYKjjG48320I2LuuXvUBZuW1nGLJ6sR90MKj1fWvUnwlJGv0Fyze1eF B1mTBD5OznZyCOJqOUA8zXxesDFoCcPSjq4rrBgCBYu8KLTCeC7ZXUPiuYLihs1B I64y7JzQThTqJghORgOb9oRq+DRHmO2hN6Ssfh41uJIJk9T6tssG3/qcwW6sdJPR r64VknaQR3yyWTOWsCpWQwjY0VgTUvtH5WjVAnnx/MZzp/P8JDDYftYh4TPXnIu+ fhHPl6P1NoFm4hV6cYUNd1dT+tDACJDVOBytxRqgJ6BpcCOyPbe8aODDHES1ZOT7 XVTO0NSrO2ywbDb7JA/OteEHy1Ql7BL85Dx0+AK3WCsgOrZ7YjoODo2/5qr+I8p0 0hyYP+NZNljCrnXy0j4F1DNjJq1saVp1LS03ye9RqclsAdjqsrze9cmupZLNAj5o qzDzm8AMGqRYBrM2gVfJ =lUq9 -----END PGP SIGNATURE----- Merge tag 'for-3.17/bcm-soc' of git://github.com/broadcom/mach-bcm into next/soc Merge "ARM: mach-bcm: soc updates for 3.17" from Matt Porter: - BCM Mobile SMP support - BRCM STB platform support * tag 'for-3.17/bcm-soc' of git://github.com/broadcom/mach-bcm: MAINTAINERS: add entry for Broadcom ARM STB architecture ARM: brcmstb: select GISB arbiter and interrupt drivers ARM: brcmstb: add infrastructure for ARM-based Broadcom STB SoCs ARM: configs: enable SMP in bcm_defconfig ARM: add SMP support for Broadcom mobile SoCs Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
21b9554e7b
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@ -1978,6 +1978,14 @@ F: arch/arm/mach-bcm/bcm_5301x.c
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F: arch/arm/boot/dts/bcm5301x.dtsi
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F: arch/arm/boot/dts/bcm470*
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BROADCOM BCM7XXX ARM ARCHITECTURE
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M: Marc Carino <marc.ceeeee@gmail.com>
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M: Brian Norris <computersforpeace@gmail.com>
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L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
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S: Maintained
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F: arch/arm/mach-bcm/*brcmstb*
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F: arch/arm/boot/dts/bcm7*.dts*
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BROADCOM TG3 GIGABIT ETHERNET DRIVER
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M: Nithin Nayak Sujir <nsujir@broadcom.com>
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M: Michael Chan <mchan@broadcom.com>
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@ -27,6 +27,7 @@ CONFIG_PARTITION_ADVANCED=y
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CONFIG_ARCH_BCM=y
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CONFIG_ARCH_BCM_MOBILE=y
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CONFIG_ARM_THUMBEE=y
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CONFIG_SMP=y
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CONFIG_PREEMPT=y
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CONFIG_AEABI=y
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# CONFIG_COMPACTION is not set
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@ -19,6 +19,7 @@ CONFIG_MACH_DOVE=y
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CONFIG_ARCH_BCM=y
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CONFIG_ARCH_BCM_MOBILE=y
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CONFIG_ARCH_BCM_5301X=y
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CONFIG_ARCH_BRCMSTB=y
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CONFIG_ARCH_BERLIN=y
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CONFIG_MACH_BERLIN_BG2=y
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CONFIG_MACH_BERLIN_BG2CD=y
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@ -9,7 +9,6 @@ config ARCH_BCM_MOBILE
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bool "Broadcom Mobile SoC Support" if ARCH_MULTI_V7
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select ARCH_REQUIRE_GPIOLIB
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select ARM_ERRATA_754322
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select ARM_ERRATA_764369 if SMP
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select ARM_ERRATA_775420
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select ARM_GIC
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select GPIO_BCM_KONA
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@ -26,16 +25,18 @@ menu "Broadcom Mobile SoC Selection"
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config ARCH_BCM_281XX
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bool "Broadcom BCM281XX SoC family"
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default y
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select HAVE_SMP
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help
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Enable support for the the BCM281XX family, which includes
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Enable support for the BCM281XX family, which includes
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BCM11130, BCM11140, BCM11351, BCM28145 and BCM28155
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variants.
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config ARCH_BCM_21664
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bool "Broadcom BCM21664 SoC family"
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default y
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select HAVE_SMP
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help
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Enable support for the the BCM21664 family, which includes
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Enable support for the BCM21664 family, which includes
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BCM21663 and BCM21664 variants.
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config ARCH_BCM_MOBILE_L2_CACHE
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@ -49,6 +50,17 @@ config ARCH_BCM_MOBILE_SMC
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bool
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depends on ARCH_BCM_281XX || ARCH_BCM_21664
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config ARCH_BCM_MOBILE_SMP
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bool "Broadcom mobile SoC SMP support"
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depends on (ARCH_BCM_281XX || ARCH_BCM_21664) && SMP
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default y
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select HAVE_ARM_SCU
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select ARM_ERRATA_764369
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help
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SMP support for the BCM281XX and BCM21664 SoC families.
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Provided as an option so SMP support for SoCs of this type
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can be disabled for an SMP-enabled kernel.
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endmenu
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endif
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@ -87,4 +99,20 @@ config ARCH_BCM_5301X
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different SoC or with the older BCM47XX and BCM53XX based
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network SoC using a MIPS CPU, they are supported by arch/mips/bcm47xx
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config ARCH_BRCMSTB
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bool "Broadcom BCM7XXX based boards" if ARCH_MULTI_V7
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depends on MMU
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select ARM_GIC
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select MIGHT_HAVE_PCI
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select HAVE_SMP
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select HAVE_ARM_ARCH_TIMER
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select BRCMSTB_GISB_ARB
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select BRCMSTB_L2_IRQ
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help
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Say Y if you intend to run the kernel on a Broadcom ARM-based STB
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chipset.
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This enables support for Broadcom ARM-based set-top box chipsets,
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including the 7445 family of chips.
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endif
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@ -16,6 +16,9 @@ obj-$(CONFIG_ARCH_BCM_281XX) += board_bcm281xx.o
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# BCM21664
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obj-$(CONFIG_ARCH_BCM_21664) += board_bcm21664.o
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# BCM281XX and BCM21664 SMP support
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obj-$(CONFIG_ARCH_BCM_MOBILE_SMP) += kona_smp.o
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# BCM281XX and BCM21664 L2 cache control
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obj-$(CONFIG_ARCH_BCM_MOBILE_L2_CACHE) += kona_l2_cache.o
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@ -30,3 +33,8 @@ obj-$(CONFIG_ARCH_BCM2835) += board_bcm2835.o
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# BCM5301X
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obj-$(CONFIG_ARCH_BCM_5301X) += bcm_5301x.o
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ifeq ($(CONFIG_ARCH_BRCMSTB),y)
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obj-y += brcmstb.o
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obj-$(CONFIG_SMP) += headsmp-brcmstb.o platsmp-brcmstb.o
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endif
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@ -0,0 +1,28 @@
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/*
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* Copyright (C) 2013-2014 Broadcom Corporation
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation version 2.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/init.h>
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#include <linux/of_platform.h>
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#include <asm/mach-types.h>
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#include <asm/mach/arch.h>
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static const char *brcmstb_match[] __initconst = {
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"brcm,bcm7445",
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"brcm,brcmstb",
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NULL
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};
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DT_MACHINE_START(BRCMSTB, "Broadcom STB (Flattened Device Tree)")
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.dt_compat = brcmstb_match,
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MACHINE_END
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@ -0,0 +1,19 @@
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/*
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* Copyright (C) 2013-2014 Broadcom Corporation
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation version 2.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __BRCMSTB_H__
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#define __BRCMSTB_H__
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void brcmstb_secondary_startup(void);
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#endif /* __BRCMSTB_H__ */
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@ -0,0 +1,33 @@
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/*
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* SMP boot code for secondary CPUs
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* Based on arch/arm/mach-tegra/headsmp.S
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*
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* Copyright (C) 2010 NVIDIA, Inc.
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* Copyright (C) 2013-2014 Broadcom Corporation
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation version 2.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <asm/assembler.h>
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#include <linux/linkage.h>
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#include <linux/init.h>
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.section ".text.head", "ax"
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ENTRY(brcmstb_secondary_startup)
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/*
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* Ensure CPU is in a sane state by disabling all IRQs and switching
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* into SVC mode.
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*/
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setmode PSR_I_BIT | PSR_F_BIT | SVC_MODE, r0
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bl v7_invalidate_l1
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b secondary_startup
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ENDPROC(brcmstb_secondary_startup)
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@ -0,0 +1,202 @@
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/*
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* Copyright (C) 2014 Broadcom Corporation
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* Copyright 2014 Linaro Limited
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation version 2.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/init.h>
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#include <linux/errno.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/sched.h>
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#include <asm/smp.h>
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#include <asm/smp_plat.h>
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#include <asm/smp_scu.h>
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/* Size of mapped Cortex A9 SCU address space */
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#define CORTEX_A9_SCU_SIZE 0x58
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#define SECONDARY_TIMEOUT_NS NSEC_PER_MSEC /* 1 msec (in nanoseconds) */
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#define BOOT_ADDR_CPUID_MASK 0x3
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/* Name of device node property defining secondary boot register location */
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#define OF_SECONDARY_BOOT "secondary-boot-reg"
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/* I/O address of register used to coordinate secondary core startup */
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static u32 secondary_boot;
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/*
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* Enable the Cortex A9 Snoop Control Unit
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*
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* By the time this is called we already know there are multiple
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* cores present. We assume we're running on a Cortex A9 processor,
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* so any trouble getting the base address register or getting the
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* SCU base is a problem.
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*
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* Return 0 if successful or an error code otherwise.
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*/
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static int __init scu_a9_enable(void)
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{
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unsigned long config_base;
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void __iomem *scu_base;
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if (!scu_a9_has_base()) {
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pr_err("no configuration base address register!\n");
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return -ENXIO;
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}
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/* Config base address register value is zero for uniprocessor */
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config_base = scu_a9_get_base();
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if (!config_base) {
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pr_err("hardware reports only one core\n");
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return -ENOENT;
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}
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scu_base = ioremap((phys_addr_t)config_base, CORTEX_A9_SCU_SIZE);
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if (!scu_base) {
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pr_err("failed to remap config base (%lu/%u) for SCU\n",
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config_base, CORTEX_A9_SCU_SIZE);
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return -ENOMEM;
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}
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scu_enable(scu_base);
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iounmap(scu_base); /* That's the last we'll need of this */
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return 0;
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}
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static void __init bcm_smp_prepare_cpus(unsigned int max_cpus)
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{
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static cpumask_t only_cpu_0 = { CPU_BITS_CPU0 };
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struct device_node *node;
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int ret;
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BUG_ON(secondary_boot); /* We're called only once */
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/*
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* This function is only called via smp_ops->smp_prepare_cpu().
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* That only happens if a "/cpus" device tree node exists
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* and has an "enable-method" property that selects the SMP
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* operations defined herein.
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*/
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node = of_find_node_by_path("/cpus");
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BUG_ON(!node);
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/*
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* Our secondary enable method requires a "secondary-boot-reg"
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* property to specify a register address used to request the
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* ROM code boot a secondary code. If we have any trouble
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* getting this we fall back to uniprocessor mode.
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*/
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if (of_property_read_u32(node, OF_SECONDARY_BOOT, &secondary_boot)) {
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pr_err("%s: missing/invalid " OF_SECONDARY_BOOT " property\n",
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node->name);
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ret = -ENOENT; /* Arrange to disable SMP */
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goto out;
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}
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/*
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* Enable the SCU on Cortex A9 based SoCs. If -ENOENT is
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* returned, the SoC reported a uniprocessor configuration.
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* We bail on any other error.
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*/
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ret = scu_a9_enable();
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out:
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of_node_put(node);
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if (ret) {
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/* Update the CPU present map to reflect uniprocessor mode */
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BUG_ON(ret != -ENOENT);
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pr_warn("disabling SMP\n");
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init_cpu_present(&only_cpu_0);
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}
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}
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/*
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* The ROM code has the secondary cores looping, waiting for an event.
|
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* When an event occurs each core examines the bottom two bits of the
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* secondary boot register. When a core finds those bits contain its
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* own core id, it performs initialization, including computing its boot
|
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* address by clearing the boot register value's bottom two bits. The
|
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* core signals that it is beginning its execution by writing its boot
|
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* address back to the secondary boot register, and finally jumps to
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* that address.
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*
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* So to start a core executing we need to:
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* - Encode the (hardware) CPU id with the bottom bits of the secondary
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* start address.
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* - Write that value into the secondary boot register.
|
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* - Generate an event to wake up the secondary CPU(s).
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* - Wait for the secondary boot register to be re-written, which
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* indicates the secondary core has started.
|
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*/
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static int bcm_boot_secondary(unsigned int cpu, struct task_struct *idle)
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{
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void __iomem *boot_reg;
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phys_addr_t boot_func;
|
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u64 start_clock;
|
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u32 cpu_id;
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u32 boot_val;
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bool timeout = false;
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|
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cpu_id = cpu_logical_map(cpu);
|
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if (cpu_id & ~BOOT_ADDR_CPUID_MASK) {
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pr_err("bad cpu id (%u > %u)\n", cpu_id, BOOT_ADDR_CPUID_MASK);
|
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return -EINVAL;
|
||||
}
|
||||
|
||||
if (!secondary_boot) {
|
||||
pr_err("required secondary boot register not specified\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
boot_reg = ioremap_nocache((phys_addr_t)secondary_boot, sizeof(u32));
|
||||
if (!boot_reg) {
|
||||
pr_err("unable to map boot register for cpu %u\n", cpu_id);
|
||||
return -ENOSYS;
|
||||
}
|
||||
|
||||
/*
|
||||
* Secondary cores will start in secondary_startup(),
|
||||
* defined in "arch/arm/kernel/head.S"
|
||||
*/
|
||||
boot_func = virt_to_phys(secondary_startup);
|
||||
BUG_ON(boot_func & BOOT_ADDR_CPUID_MASK);
|
||||
BUG_ON(boot_func > (phys_addr_t)U32_MAX);
|
||||
|
||||
/* The core to start is encoded in the low bits */
|
||||
boot_val = (u32)boot_func | cpu_id;
|
||||
writel_relaxed(boot_val, boot_reg);
|
||||
|
||||
sev();
|
||||
|
||||
/* The low bits will be cleared once the core has started */
|
||||
start_clock = local_clock();
|
||||
while (!timeout && readl_relaxed(boot_reg) == boot_val)
|
||||
timeout = local_clock() - start_clock > SECONDARY_TIMEOUT_NS;
|
||||
|
||||
iounmap(boot_reg);
|
||||
|
||||
if (!timeout)
|
||||
return 0;
|
||||
|
||||
pr_err("timeout waiting for cpu %u to start\n", cpu_id);
|
||||
|
||||
return -ENOSYS;
|
||||
}
|
||||
|
||||
static struct smp_operations bcm_smp_ops __initdata = {
|
||||
.smp_prepare_cpus = bcm_smp_prepare_cpus,
|
||||
.smp_boot_secondary = bcm_boot_secondary,
|
||||
};
|
||||
CPU_METHOD_OF_DECLARE(bcm_smp_bcm281xx, "brcm,bcm11351-cpu-method",
|
||||
&bcm_smp_ops);
|
||||
|
|
@ -0,0 +1,363 @@
|
|||
/*
|
||||
* Broadcom STB CPU SMP and hotplug support for ARM
|
||||
*
|
||||
* Copyright (C) 2013-2014 Broadcom Corporation
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation version 2.
|
||||
*
|
||||
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
|
||||
* kind, whether express or implied; without even the implied warranty
|
||||
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <linux/delay.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/printk.h>
|
||||
#include <linux/regmap.h>
|
||||
#include <linux/smp.h>
|
||||
#include <linux/mfd/syscon.h>
|
||||
#include <linux/spinlock.h>
|
||||
|
||||
#include <asm/cacheflush.h>
|
||||
#include <asm/cp15.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/smp_plat.h>
|
||||
|
||||
#include "brcmstb.h"
|
||||
|
||||
enum {
|
||||
ZONE_MAN_CLKEN_MASK = BIT(0),
|
||||
ZONE_MAN_RESET_CNTL_MASK = BIT(1),
|
||||
ZONE_MAN_MEM_PWR_MASK = BIT(4),
|
||||
ZONE_RESERVED_1_MASK = BIT(5),
|
||||
ZONE_MAN_ISO_CNTL_MASK = BIT(6),
|
||||
ZONE_MANUAL_CONTROL_MASK = BIT(7),
|
||||
ZONE_PWR_DN_REQ_MASK = BIT(9),
|
||||
ZONE_PWR_UP_REQ_MASK = BIT(10),
|
||||
ZONE_BLK_RST_ASSERT_MASK = BIT(12),
|
||||
ZONE_PWR_OFF_STATE_MASK = BIT(25),
|
||||
ZONE_PWR_ON_STATE_MASK = BIT(26),
|
||||
ZONE_DPG_PWR_STATE_MASK = BIT(28),
|
||||
ZONE_MEM_PWR_STATE_MASK = BIT(29),
|
||||
ZONE_RESET_STATE_MASK = BIT(31),
|
||||
CPU0_PWR_ZONE_CTRL_REG = 1,
|
||||
CPU_RESET_CONFIG_REG = 2,
|
||||
};
|
||||
|
||||
static void __iomem *cpubiuctrl_block;
|
||||
static void __iomem *hif_cont_block;
|
||||
static u32 cpu0_pwr_zone_ctrl_reg;
|
||||
static u32 cpu_rst_cfg_reg;
|
||||
static u32 hif_cont_reg;
|
||||
|
||||
#ifdef CONFIG_HOTPLUG_CPU
|
||||
static DEFINE_PER_CPU_ALIGNED(int, per_cpu_sw_state);
|
||||
|
||||
static int per_cpu_sw_state_rd(u32 cpu)
|
||||
{
|
||||
sync_cache_r(SHIFT_PERCPU_PTR(&per_cpu_sw_state, per_cpu_offset(cpu)));
|
||||
return per_cpu(per_cpu_sw_state, cpu);
|
||||
}
|
||||
|
||||
static void per_cpu_sw_state_wr(u32 cpu, int val)
|
||||
{
|
||||
per_cpu(per_cpu_sw_state, cpu) = val;
|
||||
dmb();
|
||||
sync_cache_w(SHIFT_PERCPU_PTR(&per_cpu_sw_state, per_cpu_offset(cpu)));
|
||||
dsb_sev();
|
||||
}
|
||||
#else
|
||||
static inline void per_cpu_sw_state_wr(u32 cpu, int val) { }
|
||||
#endif
|
||||
|
||||
static void __iomem *pwr_ctrl_get_base(u32 cpu)
|
||||
{
|
||||
void __iomem *base = cpubiuctrl_block + cpu0_pwr_zone_ctrl_reg;
|
||||
base += (cpu_logical_map(cpu) * 4);
|
||||
return base;
|
||||
}
|
||||
|
||||
static u32 pwr_ctrl_rd(u32 cpu)
|
||||
{
|
||||
void __iomem *base = pwr_ctrl_get_base(cpu);
|
||||
return readl_relaxed(base);
|
||||
}
|
||||
|
||||
static void pwr_ctrl_wr(u32 cpu, u32 val)
|
||||
{
|
||||
void __iomem *base = pwr_ctrl_get_base(cpu);
|
||||
writel(val, base);
|
||||
}
|
||||
|
||||
static void cpu_rst_cfg_set(u32 cpu, int set)
|
||||
{
|
||||
u32 val;
|
||||
val = readl_relaxed(cpubiuctrl_block + cpu_rst_cfg_reg);
|
||||
if (set)
|
||||
val |= BIT(cpu_logical_map(cpu));
|
||||
else
|
||||
val &= ~BIT(cpu_logical_map(cpu));
|
||||
writel_relaxed(val, cpubiuctrl_block + cpu_rst_cfg_reg);
|
||||
}
|
||||
|
||||
static void cpu_set_boot_addr(u32 cpu, unsigned long boot_addr)
|
||||
{
|
||||
const int reg_ofs = cpu_logical_map(cpu) * 8;
|
||||
writel_relaxed(0, hif_cont_block + hif_cont_reg + reg_ofs);
|
||||
writel_relaxed(boot_addr, hif_cont_block + hif_cont_reg + 4 + reg_ofs);
|
||||
}
|
||||
|
||||
static void brcmstb_cpu_boot(u32 cpu)
|
||||
{
|
||||
pr_info("SMP: Booting CPU%d...\n", cpu);
|
||||
|
||||
/*
|
||||
* set the reset vector to point to the secondary_startup
|
||||
* routine
|
||||
*/
|
||||
cpu_set_boot_addr(cpu, virt_to_phys(brcmstb_secondary_startup));
|
||||
|
||||
/* unhalt the cpu */
|
||||
cpu_rst_cfg_set(cpu, 0);
|
||||
}
|
||||
|
||||
static void brcmstb_cpu_power_on(u32 cpu)
|
||||
{
|
||||
/*
|
||||
* The secondary cores power was cut, so we must go through
|
||||
* power-on initialization.
|
||||
*/
|
||||
u32 tmp;
|
||||
|
||||
pr_info("SMP: Powering up CPU%d...\n", cpu);
|
||||
|
||||
/* Request zone power up */
|
||||
pwr_ctrl_wr(cpu, ZONE_PWR_UP_REQ_MASK);
|
||||
|
||||
/* Wait for the power up FSM to complete */
|
||||
do {
|
||||
tmp = pwr_ctrl_rd(cpu);
|
||||
} while (!(tmp & ZONE_PWR_ON_STATE_MASK));
|
||||
|
||||
per_cpu_sw_state_wr(cpu, 1);
|
||||
}
|
||||
|
||||
static int brcmstb_cpu_get_power_state(u32 cpu)
|
||||
{
|
||||
int tmp = pwr_ctrl_rd(cpu);
|
||||
return (tmp & ZONE_RESET_STATE_MASK) ? 0 : 1;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_HOTPLUG_CPU
|
||||
|
||||
static void brcmstb_cpu_die(u32 cpu)
|
||||
{
|
||||
v7_exit_coherency_flush(all);
|
||||
|
||||
/* Prevent all interrupts from reaching this CPU. */
|
||||
arch_local_irq_disable();
|
||||
|
||||
/*
|
||||
* Final full barrier to ensure everything before this instruction has
|
||||
* quiesced.
|
||||
*/
|
||||
isb();
|
||||
dsb();
|
||||
|
||||
per_cpu_sw_state_wr(cpu, 0);
|
||||
|
||||
/* Sit and wait to die */
|
||||
wfi();
|
||||
|
||||
/* We should never get here... */
|
||||
panic("Spurious interrupt on CPU %d received!\n", cpu);
|
||||
}
|
||||
|
||||
static int brcmstb_cpu_kill(u32 cpu)
|
||||
{
|
||||
u32 tmp;
|
||||
|
||||
pr_info("SMP: Powering down CPU%d...\n", cpu);
|
||||
|
||||
while (per_cpu_sw_state_rd(cpu))
|
||||
;
|
||||
|
||||
/* Program zone reset */
|
||||
pwr_ctrl_wr(cpu, ZONE_RESET_STATE_MASK | ZONE_BLK_RST_ASSERT_MASK |
|
||||
ZONE_PWR_DN_REQ_MASK);
|
||||
|
||||
/* Verify zone reset */
|
||||
tmp = pwr_ctrl_rd(cpu);
|
||||
if (!(tmp & ZONE_RESET_STATE_MASK))
|
||||
pr_err("%s: Zone reset bit for CPU %d not asserted!\n",
|
||||
__func__, cpu);
|
||||
|
||||
/* Wait for power down */
|
||||
do {
|
||||
tmp = pwr_ctrl_rd(cpu);
|
||||
} while (!(tmp & ZONE_PWR_OFF_STATE_MASK));
|
||||
|
||||
/* Settle-time from Broadcom-internal DVT reference code */
|
||||
udelay(7);
|
||||
|
||||
/* Assert reset on the CPU */
|
||||
cpu_rst_cfg_set(cpu, 1);
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_HOTPLUG_CPU */
|
||||
|
||||
static int __init setup_hifcpubiuctrl_regs(struct device_node *np)
|
||||
{
|
||||
int rc = 0;
|
||||
char *name;
|
||||
struct device_node *syscon_np = NULL;
|
||||
|
||||
name = "syscon-cpu";
|
||||
|
||||
syscon_np = of_parse_phandle(np, name, 0);
|
||||
if (!syscon_np) {
|
||||
pr_err("can't find phandle %s\n", name);
|
||||
rc = -EINVAL;
|
||||
goto cleanup;
|
||||
}
|
||||
|
||||
cpubiuctrl_block = of_iomap(syscon_np, 0);
|
||||
if (!cpubiuctrl_block) {
|
||||
pr_err("iomap failed for cpubiuctrl_block\n");
|
||||
rc = -EINVAL;
|
||||
goto cleanup;
|
||||
}
|
||||
|
||||
rc = of_property_read_u32_index(np, name, CPU0_PWR_ZONE_CTRL_REG,
|
||||
&cpu0_pwr_zone_ctrl_reg);
|
||||
if (rc) {
|
||||
pr_err("failed to read 1st entry from %s property (%d)\n", name,
|
||||
rc);
|
||||
rc = -EINVAL;
|
||||
goto cleanup;
|
||||
}
|
||||
|
||||
rc = of_property_read_u32_index(np, name, CPU_RESET_CONFIG_REG,
|
||||
&cpu_rst_cfg_reg);
|
||||
if (rc) {
|
||||
pr_err("failed to read 2nd entry from %s property (%d)\n", name,
|
||||
rc);
|
||||
rc = -EINVAL;
|
||||
goto cleanup;
|
||||
}
|
||||
|
||||
cleanup:
|
||||
if (syscon_np)
|
||||
of_node_put(syscon_np);
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
static int __init setup_hifcont_regs(struct device_node *np)
|
||||
{
|
||||
int rc = 0;
|
||||
char *name;
|
||||
struct device_node *syscon_np = NULL;
|
||||
|
||||
name = "syscon-cont";
|
||||
|
||||
syscon_np = of_parse_phandle(np, name, 0);
|
||||
if (!syscon_np) {
|
||||
pr_err("can't find phandle %s\n", name);
|
||||
rc = -EINVAL;
|
||||
goto cleanup;
|
||||
}
|
||||
|
||||
hif_cont_block = of_iomap(syscon_np, 0);
|
||||
if (!hif_cont_block) {
|
||||
pr_err("iomap failed for hif_cont_block\n");
|
||||
rc = -EINVAL;
|
||||
goto cleanup;
|
||||
}
|
||||
|
||||
/* offset is at top of hif_cont_block */
|
||||
hif_cont_reg = 0;
|
||||
|
||||
cleanup:
|
||||
if (syscon_np)
|
||||
of_node_put(syscon_np);
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
static void __init brcmstb_cpu_ctrl_setup(unsigned int max_cpus)
|
||||
{
|
||||
int rc;
|
||||
struct device_node *np;
|
||||
char *name;
|
||||
|
||||
name = "brcm,brcmstb-smpboot";
|
||||
np = of_find_compatible_node(NULL, NULL, name);
|
||||
if (!np) {
|
||||
pr_err("can't find compatible node %s\n", name);
|
||||
return;
|
||||
}
|
||||
|
||||
rc = setup_hifcpubiuctrl_regs(np);
|
||||
if (rc)
|
||||
return;
|
||||
|
||||
rc = setup_hifcont_regs(np);
|
||||
if (rc)
|
||||
return;
|
||||
}
|
||||
|
||||
static DEFINE_SPINLOCK(boot_lock);
|
||||
|
||||
static void brcmstb_secondary_init(unsigned int cpu)
|
||||
{
|
||||
/*
|
||||
* Synchronise with the boot thread.
|
||||
*/
|
||||
spin_lock(&boot_lock);
|
||||
spin_unlock(&boot_lock);
|
||||
}
|
||||
|
||||
static int brcmstb_boot_secondary(unsigned int cpu, struct task_struct *idle)
|
||||
{
|
||||
/*
|
||||
* set synchronisation state between this boot processor
|
||||
* and the secondary one
|
||||
*/
|
||||
spin_lock(&boot_lock);
|
||||
|
||||
/* Bring up power to the core if necessary */
|
||||
if (brcmstb_cpu_get_power_state(cpu) == 0)
|
||||
brcmstb_cpu_power_on(cpu);
|
||||
|
||||
brcmstb_cpu_boot(cpu);
|
||||
|
||||
/*
|
||||
* now the secondary core is starting up let it run its
|
||||
* calibrations, then wait for it to finish
|
||||
*/
|
||||
spin_unlock(&boot_lock);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct smp_operations brcmstb_smp_ops __initdata = {
|
||||
.smp_prepare_cpus = brcmstb_cpu_ctrl_setup,
|
||||
.smp_secondary_init = brcmstb_secondary_init,
|
||||
.smp_boot_secondary = brcmstb_boot_secondary,
|
||||
#ifdef CONFIG_HOTPLUG_CPU
|
||||
.cpu_kill = brcmstb_cpu_kill,
|
||||
.cpu_die = brcmstb_cpu_die,
|
||||
#endif
|
||||
};
|
||||
|
||||
CPU_METHOD_OF_DECLARE(brcmstb_smp, "brcm,brahma-b15", &brcmstb_smp_ops);
|
||||
Loading…
Reference in New Issue