mfd: bd70528: Support ROHM bd70528 PMIC core
ROHM BD70528MWV is an ultra-low quiescent current general purpose single-chip power management IC for battery-powered portable devices. Add MFD core which enables chip access for following subdevices: - regulators/LED drivers - battery-charger - gpios - 32.768kHz clk - RTC - watchdog Signed-off-by: Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
This commit is contained in:
Matti Vaittinen
Lee Jones
parent
2a6a7aacd4
commit
21b7c58fc1
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@ -1890,6 +1890,23 @@ config MFD_ROHM_BD718XX
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NXP i.MX8. It contains 8 BUCK outputs and 7 LDOs, voltage monitoring
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and emergency shut down as well as 32,768KHz clock output.
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config MFD_ROHM_BD70528
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tristate "ROHM BD70528 Power Management IC"
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depends on I2C=y
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depends on OF
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select REGMAP_I2C
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select REGMAP_IRQ
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select MFD_CORE
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help
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Select this option to get support for the ROHM BD70528 Power
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Management IC. BD71837 is general purpose single-chip power
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management IC for battery-powered portable devices. It contains
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3 ultra-low current consumption buck converters, 3 LDOs and 2 LED
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drivers. Also included are 4 GPIOs, a real-time clock (RTC), a 32kHz
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crystal oscillator, high-accuracy VREF for use with an external ADC,
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10 bits SAR ADC for battery temperature monitor and 1S battery
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charger.
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config MFD_STM32_LPTIMER
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tristate "Support for STM32 Low-Power Timer"
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depends on (ARCH_STM32 && OF) || COMPILE_TEST
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@ -247,5 +247,7 @@ obj-$(CONFIG_MFD_STM32_TIMERS) += stm32-timers.o
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obj-$(CONFIG_MFD_MXS_LRADC) += mxs-lradc.o
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obj-$(CONFIG_MFD_SC27XX_PMIC) += sprd-sc27xx-spi.o
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obj-$(CONFIG_RAVE_SP_CORE) += rave-sp.o
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obj-$(CONFIG_MFD_ROHM_BD70528) += rohm-bd70528.o
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obj-$(CONFIG_MFD_ROHM_BD718XX) += rohm-bd718x7.o
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obj-$(CONFIG_MFD_STMFX) += stmfx.o
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@ -0,0 +1,316 @@
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// SPDX-License-Identifier: GPL-2.0-or-later
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//
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// Copyright (C) 2019 ROHM Semiconductors
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//
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// ROHM BD70528 PMIC driver
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#include <linux/i2c.h>
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#include <linux/interrupt.h>
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#include <linux/ioport.h>
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#include <linux/irq.h>
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#include <linux/mfd/core.h>
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#include <linux/mfd/rohm-bd70528.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/regmap.h>
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#include <linux/types.h>
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#define BD70528_NUM_OF_GPIOS 4
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static const struct resource rtc_irqs[] = {
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DEFINE_RES_IRQ_NAMED(BD70528_INT_RTC_ALARM, "bd70528-rtc-alm"),
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DEFINE_RES_IRQ_NAMED(BD70528_INT_ELPS_TIM, "bd70528-elapsed-timer"),
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};
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static const struct resource charger_irqs[] = {
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DEFINE_RES_IRQ_NAMED(BD70528_INT_BAT_OV_RES, "bd70528-bat-ov-res"),
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DEFINE_RES_IRQ_NAMED(BD70528_INT_BAT_OV_DET, "bd70528-bat-ov-det"),
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DEFINE_RES_IRQ_NAMED(BD70528_INT_DBAT_DET, "bd70528-bat-dead"),
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DEFINE_RES_IRQ_NAMED(BD70528_INT_BATTSD_COLD_RES, "bd70528-bat-warmed"),
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DEFINE_RES_IRQ_NAMED(BD70528_INT_BATTSD_COLD_DET, "bd70528-bat-cold"),
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DEFINE_RES_IRQ_NAMED(BD70528_INT_BATTSD_HOT_RES, "bd70528-bat-cooled"),
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DEFINE_RES_IRQ_NAMED(BD70528_INT_BATTSD_HOT_DET, "bd70528-bat-hot"),
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DEFINE_RES_IRQ_NAMED(BD70528_INT_CHG_TSD, "bd70528-chg-tshd"),
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DEFINE_RES_IRQ_NAMED(BD70528_INT_BAT_RMV, "bd70528-bat-removed"),
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DEFINE_RES_IRQ_NAMED(BD70528_INT_BAT_DET, "bd70528-bat-detected"),
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DEFINE_RES_IRQ_NAMED(BD70528_INT_DCIN2_OV_RES, "bd70528-dcin2-ov-res"),
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DEFINE_RES_IRQ_NAMED(BD70528_INT_DCIN2_OV_DET, "bd70528-dcin2-ov-det"),
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DEFINE_RES_IRQ_NAMED(BD70528_INT_DCIN2_RMV, "bd70528-dcin2-removed"),
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DEFINE_RES_IRQ_NAMED(BD70528_INT_DCIN2_DET, "bd70528-dcin2-detected"),
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DEFINE_RES_IRQ_NAMED(BD70528_INT_DCIN1_RMV, "bd70528-dcin1-removed"),
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DEFINE_RES_IRQ_NAMED(BD70528_INT_DCIN1_DET, "bd70528-dcin1-detected"),
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};
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static struct mfd_cell bd70528_mfd_cells[] = {
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{ .name = "bd70528-pmic", },
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{ .name = "bd70528-gpio", },
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/*
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* We use BD71837 driver to drive the clock block. Only differences to
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* BD70528 clock gate are the register address and mask.
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*/
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{ .name = "bd718xx-clk", },
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{ .name = "bd70528-wdt", },
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{
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.name = "bd70528-power",
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.resources = charger_irqs,
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.num_resources = ARRAY_SIZE(charger_irqs),
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}, {
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.name = "bd70528-rtc",
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.resources = rtc_irqs,
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.num_resources = ARRAY_SIZE(rtc_irqs),
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},
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};
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static const struct regmap_range volatile_ranges[] = {
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{
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.range_min = BD70528_REG_INT_MAIN,
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.range_max = BD70528_REG_INT_OP_FAIL,
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}, {
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.range_min = BD70528_REG_RTC_COUNT_H,
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.range_max = BD70528_REG_RTC_ALM_REPEAT,
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}, {
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/*
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* WDT control reg is special. Magic values must be written to
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* it in order to change the control. Should not be cached.
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*/
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.range_min = BD70528_REG_WDT_CTRL,
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.range_max = BD70528_REG_WDT_CTRL,
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}, {
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/*
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* BD70528 also contains a few other registers which require
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* magic sequences to be written in order to update the value.
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* At least SHIPMODE, HWRESET, WARMRESET,and STANDBY
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*/
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.range_min = BD70528_REG_SHIPMODE,
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.range_max = BD70528_REG_STANDBY,
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},
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};
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static const struct regmap_access_table volatile_regs = {
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.yes_ranges = &volatile_ranges[0],
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.n_yes_ranges = ARRAY_SIZE(volatile_ranges),
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};
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static struct regmap_config bd70528_regmap = {
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.reg_bits = 8,
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.val_bits = 8,
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.volatile_table = &volatile_regs,
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.max_register = BD70528_MAX_REGISTER,
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.cache_type = REGCACHE_RBTREE,
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};
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/*
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* Mapping of main IRQ register bits to sub-IRQ register offsets so that we can
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* access corect sub-IRQ registers based on bits that are set in main IRQ
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* register.
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*/
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/* bit [0] - Shutdown register */
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unsigned int bit0_offsets[] = {0}; /* Shutdown register */
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unsigned int bit1_offsets[] = {1}; /* Power failure register */
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unsigned int bit2_offsets[] = {2}; /* VR FAULT register */
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unsigned int bit3_offsets[] = {3}; /* PMU register interrupts */
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unsigned int bit4_offsets[] = {4, 5}; /* Charger 1 and Charger 2 registers */
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unsigned int bit5_offsets[] = {6}; /* RTC register */
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unsigned int bit6_offsets[] = {7}; /* GPIO register */
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unsigned int bit7_offsets[] = {8}; /* Invalid operation register */
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static struct regmap_irq_sub_irq_map bd70528_sub_irq_offsets[] = {
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REGMAP_IRQ_MAIN_REG_OFFSET(bit0_offsets),
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REGMAP_IRQ_MAIN_REG_OFFSET(bit1_offsets),
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REGMAP_IRQ_MAIN_REG_OFFSET(bit2_offsets),
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REGMAP_IRQ_MAIN_REG_OFFSET(bit3_offsets),
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REGMAP_IRQ_MAIN_REG_OFFSET(bit4_offsets),
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REGMAP_IRQ_MAIN_REG_OFFSET(bit5_offsets),
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REGMAP_IRQ_MAIN_REG_OFFSET(bit6_offsets),
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REGMAP_IRQ_MAIN_REG_OFFSET(bit7_offsets),
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};
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static struct regmap_irq bd70528_irqs[] = {
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REGMAP_IRQ_REG(BD70528_INT_LONGPUSH, 0, BD70528_INT_LONGPUSH_MASK),
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REGMAP_IRQ_REG(BD70528_INT_WDT, 0, BD70528_INT_WDT_MASK),
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REGMAP_IRQ_REG(BD70528_INT_HWRESET, 0, BD70528_INT_HWRESET_MASK),
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REGMAP_IRQ_REG(BD70528_INT_RSTB_FAULT, 0, BD70528_INT_RSTB_FAULT_MASK),
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REGMAP_IRQ_REG(BD70528_INT_VBAT_UVLO, 0, BD70528_INT_VBAT_UVLO_MASK),
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REGMAP_IRQ_REG(BD70528_INT_TSD, 0, BD70528_INT_TSD_MASK),
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REGMAP_IRQ_REG(BD70528_INT_RSTIN, 0, BD70528_INT_RSTIN_MASK),
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REGMAP_IRQ_REG(BD70528_INT_BUCK1_FAULT, 1,
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BD70528_INT_BUCK1_FAULT_MASK),
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REGMAP_IRQ_REG(BD70528_INT_BUCK2_FAULT, 1,
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BD70528_INT_BUCK2_FAULT_MASK),
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REGMAP_IRQ_REG(BD70528_INT_BUCK3_FAULT, 1,
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BD70528_INT_BUCK3_FAULT_MASK),
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REGMAP_IRQ_REG(BD70528_INT_LDO1_FAULT, 1, BD70528_INT_LDO1_FAULT_MASK),
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REGMAP_IRQ_REG(BD70528_INT_LDO2_FAULT, 1, BD70528_INT_LDO2_FAULT_MASK),
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REGMAP_IRQ_REG(BD70528_INT_LDO3_FAULT, 1, BD70528_INT_LDO3_FAULT_MASK),
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REGMAP_IRQ_REG(BD70528_INT_LED1_FAULT, 1, BD70528_INT_LED1_FAULT_MASK),
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REGMAP_IRQ_REG(BD70528_INT_LED2_FAULT, 1, BD70528_INT_LED2_FAULT_MASK),
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REGMAP_IRQ_REG(BD70528_INT_BUCK1_OCP, 2, BD70528_INT_BUCK1_OCP_MASK),
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REGMAP_IRQ_REG(BD70528_INT_BUCK2_OCP, 2, BD70528_INT_BUCK2_OCP_MASK),
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REGMAP_IRQ_REG(BD70528_INT_BUCK3_OCP, 2, BD70528_INT_BUCK3_OCP_MASK),
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REGMAP_IRQ_REG(BD70528_INT_LED1_OCP, 2, BD70528_INT_LED1_OCP_MASK),
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REGMAP_IRQ_REG(BD70528_INT_LED2_OCP, 2, BD70528_INT_LED2_OCP_MASK),
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REGMAP_IRQ_REG(BD70528_INT_BUCK1_FULLON, 2,
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BD70528_INT_BUCK1_FULLON_MASK),
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REGMAP_IRQ_REG(BD70528_INT_BUCK2_FULLON, 2,
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BD70528_INT_BUCK2_FULLON_MASK),
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REGMAP_IRQ_REG(BD70528_INT_SHORTPUSH, 3, BD70528_INT_SHORTPUSH_MASK),
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REGMAP_IRQ_REG(BD70528_INT_AUTO_WAKEUP, 3,
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BD70528_INT_AUTO_WAKEUP_MASK),
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REGMAP_IRQ_REG(BD70528_INT_STATE_CHANGE, 3,
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BD70528_INT_STATE_CHANGE_MASK),
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REGMAP_IRQ_REG(BD70528_INT_BAT_OV_RES, 4, BD70528_INT_BAT_OV_RES_MASK),
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REGMAP_IRQ_REG(BD70528_INT_BAT_OV_DET, 4, BD70528_INT_BAT_OV_DET_MASK),
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REGMAP_IRQ_REG(BD70528_INT_DBAT_DET, 4, BD70528_INT_DBAT_DET_MASK),
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REGMAP_IRQ_REG(BD70528_INT_BATTSD_COLD_RES, 4,
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BD70528_INT_BATTSD_COLD_RES_MASK),
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REGMAP_IRQ_REG(BD70528_INT_BATTSD_COLD_DET, 4,
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BD70528_INT_BATTSD_COLD_DET_MASK),
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REGMAP_IRQ_REG(BD70528_INT_BATTSD_HOT_RES, 4,
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BD70528_INT_BATTSD_HOT_RES_MASK),
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REGMAP_IRQ_REG(BD70528_INT_BATTSD_HOT_DET, 4,
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BD70528_INT_BATTSD_HOT_DET_MASK),
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REGMAP_IRQ_REG(BD70528_INT_CHG_TSD, 4, BD70528_INT_CHG_TSD_MASK),
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REGMAP_IRQ_REG(BD70528_INT_BAT_RMV, 5, BD70528_INT_BAT_RMV_MASK),
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REGMAP_IRQ_REG(BD70528_INT_BAT_DET, 5, BD70528_INT_BAT_DET_MASK),
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REGMAP_IRQ_REG(BD70528_INT_DCIN2_OV_RES, 5,
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BD70528_INT_DCIN2_OV_RES_MASK),
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REGMAP_IRQ_REG(BD70528_INT_DCIN2_OV_DET, 5,
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BD70528_INT_DCIN2_OV_DET_MASK),
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REGMAP_IRQ_REG(BD70528_INT_DCIN2_RMV, 5, BD70528_INT_DCIN2_RMV_MASK),
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REGMAP_IRQ_REG(BD70528_INT_DCIN2_DET, 5, BD70528_INT_DCIN2_DET_MASK),
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REGMAP_IRQ_REG(BD70528_INT_DCIN1_RMV, 5, BD70528_INT_DCIN1_RMV_MASK),
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REGMAP_IRQ_REG(BD70528_INT_DCIN1_DET, 5, BD70528_INT_DCIN1_DET_MASK),
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REGMAP_IRQ_REG(BD70528_INT_RTC_ALARM, 6, BD70528_INT_RTC_ALARM_MASK),
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REGMAP_IRQ_REG(BD70528_INT_ELPS_TIM, 6, BD70528_INT_ELPS_TIM_MASK),
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REGMAP_IRQ_REG(BD70528_INT_GPIO0, 7, BD70528_INT_GPIO0_MASK),
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REGMAP_IRQ_REG(BD70528_INT_GPIO1, 7, BD70528_INT_GPIO1_MASK),
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REGMAP_IRQ_REG(BD70528_INT_GPIO2, 7, BD70528_INT_GPIO2_MASK),
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REGMAP_IRQ_REG(BD70528_INT_GPIO3, 7, BD70528_INT_GPIO3_MASK),
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REGMAP_IRQ_REG(BD70528_INT_BUCK1_DVS_OPFAIL, 8,
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BD70528_INT_BUCK1_DVS_OPFAIL_MASK),
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REGMAP_IRQ_REG(BD70528_INT_BUCK2_DVS_OPFAIL, 8,
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BD70528_INT_BUCK2_DVS_OPFAIL_MASK),
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REGMAP_IRQ_REG(BD70528_INT_BUCK3_DVS_OPFAIL, 8,
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BD70528_INT_BUCK3_DVS_OPFAIL_MASK),
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REGMAP_IRQ_REG(BD70528_INT_LED1_VOLT_OPFAIL, 8,
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BD70528_INT_LED1_VOLT_OPFAIL_MASK),
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REGMAP_IRQ_REG(BD70528_INT_LED2_VOLT_OPFAIL, 8,
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BD70528_INT_LED2_VOLT_OPFAIL_MASK),
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};
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static struct regmap_irq_chip bd70528_irq_chip = {
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.name = "bd70528_irq",
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.main_status = BD70528_REG_INT_MAIN,
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.irqs = &bd70528_irqs[0],
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.num_irqs = ARRAY_SIZE(bd70528_irqs),
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.status_base = BD70528_REG_INT_SHDN,
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.mask_base = BD70528_REG_INT_SHDN_MASK,
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.ack_base = BD70528_REG_INT_SHDN,
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.type_base = BD70528_REG_GPIO1_IN,
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.init_ack_masked = true,
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.num_regs = 9,
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.num_main_regs = 1,
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.num_type_reg = 4,
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.sub_reg_offsets = &bd70528_sub_irq_offsets[0],
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.num_main_status_bits = 8,
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.irq_reg_stride = 1,
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};
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static int bd70528_i2c_probe(struct i2c_client *i2c,
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const struct i2c_device_id *id)
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{
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struct bd70528_data *bd70528;
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struct regmap_irq_chip_data *irq_data;
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int ret, i;
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if (!i2c->irq) {
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dev_err(&i2c->dev, "No IRQ configured\n");
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return -EINVAL;
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}
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bd70528 = devm_kzalloc(&i2c->dev, sizeof(*bd70528), GFP_KERNEL);
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if (!bd70528)
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return -ENOMEM;
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mutex_init(&bd70528->rtc_timer_lock);
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dev_set_drvdata(&i2c->dev, &bd70528->chip);
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bd70528->chip.chip_type = ROHM_CHIP_TYPE_BD70528;
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bd70528->chip.regmap = devm_regmap_init_i2c(i2c, &bd70528_regmap);
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if (IS_ERR(bd70528->chip.regmap)) {
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dev_err(&i2c->dev, "Failed to initialize Regmap\n");
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return PTR_ERR(bd70528->chip.regmap);
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}
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/*
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* Disallow type setting for all IRQs by default as most of them do not
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* support setting type.
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*/
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for (i = 0; i < ARRAY_SIZE(bd70528_irqs); i++)
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bd70528_irqs[i].type.types_supported = 0;
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/* Set IRQ typesetting information for GPIO pins 0 - 3 */
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for (i = 0; i < BD70528_NUM_OF_GPIOS; i++) {
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struct regmap_irq_type *type;
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type = &bd70528_irqs[BD70528_INT_GPIO0 + i].type;
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type->type_reg_offset = 2 * i;
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type->type_rising_val = 0x20;
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type->type_falling_val = 0x10;
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type->type_level_high_val = 0x40;
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type->type_level_low_val = 0x50;
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type->types_supported = (IRQ_TYPE_EDGE_BOTH |
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IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW);
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}
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ret = devm_regmap_add_irq_chip(&i2c->dev, bd70528->chip.regmap,
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i2c->irq, IRQF_ONESHOT, 0,
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&bd70528_irq_chip, &irq_data);
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if (ret) {
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dev_err(&i2c->dev, "Failed to add IRQ chip\n");
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return ret;
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}
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dev_dbg(&i2c->dev, "Registered %d IRQs for chip\n",
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bd70528_irq_chip.num_irqs);
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/*
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* BD70528 IRQ controller is not touching the main mask register.
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* So enable the GPIO block interrupts at main level. We can just leave
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* them enabled as the IRQ controller should disable IRQs from
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* sub-registers when IRQ is disabled or freed.
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*/
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ret = regmap_update_bits(bd70528->chip.regmap,
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BD70528_REG_INT_MAIN_MASK,
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BD70528_INT_GPIO_MASK, 0);
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ret = devm_mfd_add_devices(&i2c->dev, PLATFORM_DEVID_AUTO,
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bd70528_mfd_cells,
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ARRAY_SIZE(bd70528_mfd_cells), NULL, 0,
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regmap_irq_get_domain(irq_data));
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if (ret)
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dev_err(&i2c->dev, "Failed to create subdevices\n");
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return ret;
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}
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static const struct of_device_id bd70528_of_match[] = {
|
||||
{ .compatible = "rohm,bd70528", },
|
||||
{ },
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, bd70528_of_match);
|
||||
|
||||
static struct i2c_driver bd70528_drv = {
|
||||
.driver = {
|
||||
.name = "rohm-bd70528",
|
||||
.of_match_table = bd70528_of_match,
|
||||
},
|
||||
.probe = &bd70528_i2c_probe,
|
||||
};
|
||||
|
||||
module_i2c_driver(bd70528_drv);
|
||||
|
||||
MODULE_AUTHOR("Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com>");
|
||||
MODULE_DESCRIPTION("ROHM BD70528 Power Management IC driver");
|
||||
MODULE_LICENSE("GPL");
|
||||
|
|
@ -0,0 +1,408 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
/* Copyright (C) 2018 ROHM Semiconductors */
|
||||
|
||||
#ifndef __LINUX_MFD_BD70528_H__
|
||||
#define __LINUX_MFD_BD70528_H__
|
||||
|
||||
#include <linux/bits.h>
|
||||
#include <linux/device.h>
|
||||
#include <linux/mfd/rohm-generic.h>
|
||||
#include <linux/regmap.h>
|
||||
|
||||
enum {
|
||||
BD70528_BUCK1,
|
||||
BD70528_BUCK2,
|
||||
BD70528_BUCK3,
|
||||
BD70528_LDO1,
|
||||
BD70528_LDO2,
|
||||
BD70528_LDO3,
|
||||
BD70528_LED1,
|
||||
BD70528_LED2,
|
||||
};
|
||||
|
||||
struct bd70528_data {
|
||||
struct rohm_regmap_dev chip;
|
||||
struct mutex rtc_timer_lock;
|
||||
};
|
||||
|
||||
#define BD70528_BUCK_VOLTS 17
|
||||
#define BD70528_BUCK_VOLTS 17
|
||||
#define BD70528_BUCK_VOLTS 17
|
||||
#define BD70528_LDO_VOLTS 0x20
|
||||
|
||||
#define BD70528_REG_BUCK1_EN 0x0F
|
||||
#define BD70528_REG_BUCK1_VOLT 0x15
|
||||
#define BD70528_REG_BUCK2_EN 0x10
|
||||
#define BD70528_REG_BUCK2_VOLT 0x16
|
||||
#define BD70528_REG_BUCK3_EN 0x11
|
||||
#define BD70528_REG_BUCK3_VOLT 0x17
|
||||
#define BD70528_REG_LDO1_EN 0x1b
|
||||
#define BD70528_REG_LDO1_VOLT 0x1e
|
||||
#define BD70528_REG_LDO2_EN 0x1c
|
||||
#define BD70528_REG_LDO2_VOLT 0x1f
|
||||
#define BD70528_REG_LDO3_EN 0x1d
|
||||
#define BD70528_REG_LDO3_VOLT 0x20
|
||||
#define BD70528_REG_LED_CTRL 0x2b
|
||||
#define BD70528_REG_LED_VOLT 0x29
|
||||
#define BD70528_REG_LED_EN 0x2a
|
||||
|
||||
/* main irq registers */
|
||||
#define BD70528_REG_INT_MAIN 0x7E
|
||||
#define BD70528_REG_INT_MAIN_MASK 0x74
|
||||
|
||||
/* 'sub irq' registers */
|
||||
#define BD70528_REG_INT_SHDN 0x7F
|
||||
#define BD70528_REG_INT_PWR_FLT 0x80
|
||||
#define BD70528_REG_INT_VR_FLT 0x81
|
||||
#define BD70528_REG_INT_MISC 0x82
|
||||
#define BD70528_REG_INT_BAT1 0x83
|
||||
#define BD70528_REG_INT_BAT2 0x84
|
||||
#define BD70528_REG_INT_RTC 0x85
|
||||
#define BD70528_REG_INT_GPIO 0x86
|
||||
#define BD70528_REG_INT_OP_FAIL 0x87
|
||||
|
||||
#define BD70528_REG_INT_SHDN_MASK 0x75
|
||||
#define BD70528_REG_INT_PWR_FLT_MASK 0x76
|
||||
#define BD70528_REG_INT_VR_FLT_MASK 0x77
|
||||
#define BD70528_REG_INT_MISC_MASK 0x78
|
||||
#define BD70528_REG_INT_BAT1_MASK 0x79
|
||||
#define BD70528_REG_INT_BAT2_MASK 0x7a
|
||||
#define BD70528_REG_INT_RTC_MASK 0x7b
|
||||
#define BD70528_REG_INT_GPIO_MASK 0x7c
|
||||
#define BD70528_REG_INT_OP_FAIL_MASK 0x7d
|
||||
|
||||
/* Reset related 'magic' registers */
|
||||
#define BD70528_REG_SHIPMODE 0x03
|
||||
#define BD70528_REG_HWRESET 0x04
|
||||
#define BD70528_REG_WARMRESET 0x05
|
||||
#define BD70528_REG_STANDBY 0x06
|
||||
|
||||
/* GPIO registers */
|
||||
#define BD70528_REG_GPIO_STATE 0x8F
|
||||
|
||||
#define BD70528_REG_GPIO1_IN 0x4d
|
||||
#define BD70528_REG_GPIO2_IN 0x4f
|
||||
#define BD70528_REG_GPIO3_IN 0x51
|
||||
#define BD70528_REG_GPIO4_IN 0x53
|
||||
#define BD70528_REG_GPIO1_OUT 0x4e
|
||||
#define BD70528_REG_GPIO2_OUT 0x50
|
||||
#define BD70528_REG_GPIO3_OUT 0x52
|
||||
#define BD70528_REG_GPIO4_OUT 0x54
|
||||
|
||||
/* clk control */
|
||||
|
||||
#define BD70528_REG_CLK_OUT 0x2c
|
||||
|
||||
/* RTC */
|
||||
|
||||
#define BD70528_REG_RTC_COUNT_H 0x2d
|
||||
#define BD70528_REG_RTC_COUNT_L 0x2e
|
||||
#define BD70528_REG_RTC_SEC 0x2f
|
||||
#define BD70528_REG_RTC_MINUTE 0x30
|
||||
#define BD70528_REG_RTC_HOUR 0x31
|
||||
#define BD70528_REG_RTC_WEEK 0x32
|
||||
#define BD70528_REG_RTC_DAY 0x33
|
||||
#define BD70528_REG_RTC_MONTH 0x34
|
||||
#define BD70528_REG_RTC_YEAR 0x35
|
||||
|
||||
#define BD70528_REG_RTC_ALM_SEC 0x36
|
||||
#define BD70528_REG_RTC_ALM_START BD70528_REG_RTC_ALM_SEC
|
||||
#define BD70528_REG_RTC_ALM_MINUTE 0x37
|
||||
#define BD70528_REG_RTC_ALM_HOUR 0x38
|
||||
#define BD70528_REG_RTC_ALM_WEEK 0x39
|
||||
#define BD70528_REG_RTC_ALM_DAY 0x3a
|
||||
#define BD70528_REG_RTC_ALM_MONTH 0x3b
|
||||
#define BD70528_REG_RTC_ALM_YEAR 0x3c
|
||||
#define BD70528_REG_RTC_ALM_MASK 0x3d
|
||||
#define BD70528_REG_RTC_ALM_REPEAT 0x3e
|
||||
#define BD70528_REG_RTC_START BD70528_REG_RTC_SEC
|
||||
|
||||
#define BD70528_REG_RTC_WAKE_SEC 0x43
|
||||
#define BD70528_REG_RTC_WAKE_START BD70528_REG_RTC_WAKE_SEC
|
||||
#define BD70528_REG_RTC_WAKE_MIN 0x44
|
||||
#define BD70528_REG_RTC_WAKE_HOUR 0x45
|
||||
#define BD70528_REG_RTC_WAKE_CTRL 0x46
|
||||
|
||||
#define BD70528_REG_ELAPSED_TIMER_EN 0x42
|
||||
#define BD70528_REG_WAKE_EN 0x46
|
||||
|
||||
/* WDT registers */
|
||||
#define BD70528_REG_WDT_CTRL 0x4A
|
||||
#define BD70528_REG_WDT_HOUR 0x49
|
||||
#define BD70528_REG_WDT_MINUTE 0x48
|
||||
#define BD70528_REG_WDT_SEC 0x47
|
||||
|
||||
/* Charger / Battery */
|
||||
#define BD70528_REG_CHG_CURR_STAT 0x59
|
||||
#define BD70528_REG_CHG_BAT_STAT 0x57
|
||||
#define BD70528_REG_CHG_BAT_TEMP 0x58
|
||||
#define BD70528_REG_CHG_IN_STAT 0x56
|
||||
#define BD70528_REG_CHG_DCIN_ILIM 0x5d
|
||||
#define BD70528_REG_CHG_CHG_CURR_WARM 0x61
|
||||
#define BD70528_REG_CHG_CHG_CURR_COLD 0x62
|
||||
|
||||
/* Masks for main IRQ register bits */
|
||||
enum {
|
||||
BD70528_INT_SHDN,
|
||||
#define BD70528_INT_SHDN_MASK BIT(BD70528_INT_SHDN)
|
||||
BD70528_INT_PWR_FLT,
|
||||
#define BD70528_INT_PWR_FLT_MASK BIT(BD70528_INT_PWR_FLT)
|
||||
BD70528_INT_VR_FLT,
|
||||
#define BD70528_INT_VR_FLT_MASK BIT(BD70528_INT_VR_FLT)
|
||||
BD70528_INT_MISC,
|
||||
#define BD70528_INT_MISC_MASK BIT(BD70528_INT_MISC)
|
||||
BD70528_INT_BAT1,
|
||||
#define BD70528_INT_BAT1_MASK BIT(BD70528_INT_BAT1)
|
||||
BD70528_INT_RTC,
|
||||
#define BD70528_INT_RTC_MASK BIT(BD70528_INT_RTC)
|
||||
BD70528_INT_GPIO,
|
||||
#define BD70528_INT_GPIO_MASK BIT(BD70528_INT_GPIO)
|
||||
BD70528_INT_OP_FAIL,
|
||||
#define BD70528_INT_OP_FAIL_MASK BIT(BD70528_INT_OP_FAIL)
|
||||
};
|
||||
|
||||
/* IRQs */
|
||||
enum {
|
||||
/* Shutdown register IRQs */
|
||||
BD70528_INT_LONGPUSH,
|
||||
BD70528_INT_WDT,
|
||||
BD70528_INT_HWRESET,
|
||||
BD70528_INT_RSTB_FAULT,
|
||||
BD70528_INT_VBAT_UVLO,
|
||||
BD70528_INT_TSD,
|
||||
BD70528_INT_RSTIN,
|
||||
/* Power failure register IRQs */
|
||||
BD70528_INT_BUCK1_FAULT,
|
||||
BD70528_INT_BUCK2_FAULT,
|
||||
BD70528_INT_BUCK3_FAULT,
|
||||
BD70528_INT_LDO1_FAULT,
|
||||
BD70528_INT_LDO2_FAULT,
|
||||
BD70528_INT_LDO3_FAULT,
|
||||
BD70528_INT_LED1_FAULT,
|
||||
BD70528_INT_LED2_FAULT,
|
||||
/* VR FAULT register IRQs */
|
||||
BD70528_INT_BUCK1_OCP,
|
||||
BD70528_INT_BUCK2_OCP,
|
||||
BD70528_INT_BUCK3_OCP,
|
||||
BD70528_INT_LED1_OCP,
|
||||
BD70528_INT_LED2_OCP,
|
||||
BD70528_INT_BUCK1_FULLON,
|
||||
BD70528_INT_BUCK2_FULLON,
|
||||
/* PMU register interrupts */
|
||||
BD70528_INT_SHORTPUSH,
|
||||
BD70528_INT_AUTO_WAKEUP,
|
||||
BD70528_INT_STATE_CHANGE,
|
||||
/* Charger 1 register IRQs */
|
||||
BD70528_INT_BAT_OV_RES,
|
||||
BD70528_INT_BAT_OV_DET,
|
||||
BD70528_INT_DBAT_DET,
|
||||
BD70528_INT_BATTSD_COLD_RES,
|
||||
BD70528_INT_BATTSD_COLD_DET,
|
||||
BD70528_INT_BATTSD_HOT_RES,
|
||||
BD70528_INT_BATTSD_HOT_DET,
|
||||
BD70528_INT_CHG_TSD,
|
||||
/* Charger 2 register IRQs */
|
||||
BD70528_INT_BAT_RMV,
|
||||
BD70528_INT_BAT_DET,
|
||||
BD70528_INT_DCIN2_OV_RES,
|
||||
BD70528_INT_DCIN2_OV_DET,
|
||||
BD70528_INT_DCIN2_RMV,
|
||||
BD70528_INT_DCIN2_DET,
|
||||
BD70528_INT_DCIN1_RMV,
|
||||
BD70528_INT_DCIN1_DET,
|
||||
/* RTC register IRQs */
|
||||
BD70528_INT_RTC_ALARM,
|
||||
BD70528_INT_ELPS_TIM,
|
||||
/* GPIO register IRQs */
|
||||
BD70528_INT_GPIO0,
|
||||
BD70528_INT_GPIO1,
|
||||
BD70528_INT_GPIO2,
|
||||
BD70528_INT_GPIO3,
|
||||
/* Invalid operation register IRQs */
|
||||
BD70528_INT_BUCK1_DVS_OPFAIL,
|
||||
BD70528_INT_BUCK2_DVS_OPFAIL,
|
||||
BD70528_INT_BUCK3_DVS_OPFAIL,
|
||||
BD70528_INT_LED1_VOLT_OPFAIL,
|
||||
BD70528_INT_LED2_VOLT_OPFAIL,
|
||||
};
|
||||
|
||||
/* Masks */
|
||||
#define BD70528_INT_LONGPUSH_MASK 0x1
|
||||
#define BD70528_INT_WDT_MASK 0x2
|
||||
#define BD70528_INT_HWRESET_MASK 0x4
|
||||
#define BD70528_INT_RSTB_FAULT_MASK 0x8
|
||||
#define BD70528_INT_VBAT_UVLO_MASK 0x10
|
||||
#define BD70528_INT_TSD_MASK 0x20
|
||||
#define BD70528_INT_RSTIN_MASK 0x40
|
||||
|
||||
#define BD70528_INT_BUCK1_FAULT_MASK 0x1
|
||||
#define BD70528_INT_BUCK2_FAULT_MASK 0x2
|
||||
#define BD70528_INT_BUCK3_FAULT_MASK 0x4
|
||||
#define BD70528_INT_LDO1_FAULT_MASK 0x8
|
||||
#define BD70528_INT_LDO2_FAULT_MASK 0x10
|
||||
#define BD70528_INT_LDO3_FAULT_MASK 0x20
|
||||
#define BD70528_INT_LED1_FAULT_MASK 0x40
|
||||
#define BD70528_INT_LED2_FAULT_MASK 0x80
|
||||
|
||||
#define BD70528_INT_BUCK1_OCP_MASK 0x1
|
||||
#define BD70528_INT_BUCK2_OCP_MASK 0x2
|
||||
#define BD70528_INT_BUCK3_OCP_MASK 0x4
|
||||
#define BD70528_INT_LED1_OCP_MASK 0x8
|
||||
#define BD70528_INT_LED2_OCP_MASK 0x10
|
||||
#define BD70528_INT_BUCK1_FULLON_MASK 0x20
|
||||
#define BD70528_INT_BUCK2_FULLON_MASK 0x40
|
||||
|
||||
#define BD70528_INT_SHORTPUSH_MASK 0x1
|
||||
#define BD70528_INT_AUTO_WAKEUP_MASK 0x2
|
||||
#define BD70528_INT_STATE_CHANGE_MASK 0x10
|
||||
|
||||
#define BD70528_INT_BAT_OV_RES_MASK 0x1
|
||||
#define BD70528_INT_BAT_OV_DET_MASK 0x2
|
||||
#define BD70528_INT_DBAT_DET_MASK 0x4
|
||||
#define BD70528_INT_BATTSD_COLD_RES_MASK 0x8
|
||||
#define BD70528_INT_BATTSD_COLD_DET_MASK 0x10
|
||||
#define BD70528_INT_BATTSD_HOT_RES_MASK 0x20
|
||||
#define BD70528_INT_BATTSD_HOT_DET_MASK 0x40
|
||||
#define BD70528_INT_CHG_TSD_MASK 0x80
|
||||
|
||||
#define BD70528_INT_BAT_RMV_MASK 0x1
|
||||
#define BD70528_INT_BAT_DET_MASK 0x2
|
||||
#define BD70528_INT_DCIN2_OV_RES_MASK 0x4
|
||||
#define BD70528_INT_DCIN2_OV_DET_MASK 0x8
|
||||
#define BD70528_INT_DCIN2_RMV_MASK 0x10
|
||||
#define BD70528_INT_DCIN2_DET_MASK 0x20
|
||||
#define BD70528_INT_DCIN1_RMV_MASK 0x40
|
||||
#define BD70528_INT_DCIN1_DET_MASK 0x80
|
||||
|
||||
#define BD70528_INT_RTC_ALARM_MASK 0x1
|
||||
#define BD70528_INT_ELPS_TIM_MASK 0x2
|
||||
|
||||
#define BD70528_INT_GPIO0_MASK 0x1
|
||||
#define BD70528_INT_GPIO1_MASK 0x2
|
||||
#define BD70528_INT_GPIO2_MASK 0x4
|
||||
#define BD70528_INT_GPIO3_MASK 0x8
|
||||
|
||||
#define BD70528_INT_BUCK1_DVS_OPFAIL_MASK 0x1
|
||||
#define BD70528_INT_BUCK2_DVS_OPFAIL_MASK 0x2
|
||||
#define BD70528_INT_BUCK3_DVS_OPFAIL_MASK 0x4
|
||||
#define BD70528_INT_LED1_VOLT_OPFAIL_MASK 0x10
|
||||
#define BD70528_INT_LED2_VOLT_OPFAIL_MASK 0x20
|
||||
|
||||
#define BD70528_DEBOUNCE_MASK 0x3
|
||||
|
||||
#define BD70528_DEBOUNCE_DISABLE 0
|
||||
#define BD70528_DEBOUNCE_15MS 1
|
||||
#define BD70528_DEBOUNCE_30MS 2
|
||||
#define BD70528_DEBOUNCE_50MS 3
|
||||
|
||||
#define BD70528_GPIO_DRIVE_MASK 0x2
|
||||
#define BD70528_GPIO_PUSH_PULL 0x0
|
||||
#define BD70528_GPIO_OPEN_DRAIN 0x2
|
||||
|
||||
#define BD70528_GPIO_OUT_EN_MASK 0x80
|
||||
#define BD70528_GPIO_OUT_ENABLE 0x80
|
||||
#define BD70528_GPIO_OUT_DISABLE 0x0
|
||||
|
||||
#define BD70528_GPIO_OUT_HI 0x1
|
||||
#define BD70528_GPIO_OUT_LO 0x0
|
||||
#define BD70528_GPIO_OUT_MASK 0x1
|
||||
|
||||
#define BD70528_GPIO_IN_STATE_BASE 1
|
||||
|
||||
#define BD70528_CLK_OUT_EN_MASK 0x1
|
||||
|
||||
/* RTC masks to mask out reserved bits */
|
||||
|
||||
#define BD70528_MASK_RTC_SEC 0x7f
|
||||
#define BD70528_MASK_RTC_MINUTE 0x7f
|
||||
#define BD70528_MASK_RTC_HOUR_24H 0x80
|
||||
#define BD70528_MASK_RTC_HOUR_PM 0x20
|
||||
#define BD70528_MASK_RTC_HOUR 0x1f
|
||||
#define BD70528_MASK_RTC_DAY 0x3f
|
||||
#define BD70528_MASK_RTC_WEEK 0x07
|
||||
#define BD70528_MASK_RTC_MONTH 0x1f
|
||||
#define BD70528_MASK_RTC_YEAR 0xff
|
||||
#define BD70528_MASK_RTC_COUNT_L 0x7f
|
||||
|
||||
#define BD70528_MASK_ELAPSED_TIMER_EN 0x1
|
||||
/* Mask second, min and hour fields
|
||||
* HW would support ALM irq for over 24h
|
||||
* (by setting day, month and year too)
|
||||
* but as we wish to keep this same as for
|
||||
* wake-up we limit ALM to 24H and only
|
||||
* unmask sec, min and hour
|
||||
*/
|
||||
#define BD70528_MASK_ALM_EN 0x7
|
||||
#define BD70528_MASK_WAKE_EN 0x1
|
||||
|
||||
/* WDT masks */
|
||||
#define BD70528_MASK_WDT_EN 0x1
|
||||
#define BD70528_MASK_WDT_HOUR 0x1
|
||||
#define BD70528_MASK_WDT_MINUTE 0x7f
|
||||
#define BD70528_MASK_WDT_SEC 0x7f
|
||||
|
||||
#define BD70528_WDT_STATE_BIT 0x1
|
||||
#define BD70528_ELAPSED_STATE_BIT 0x2
|
||||
#define BD70528_WAKE_STATE_BIT 0x4
|
||||
|
||||
/* Charger masks */
|
||||
#define BD70528_MASK_CHG_STAT 0x7f
|
||||
#define BD70528_MASK_CHG_BAT_TIMER 0x20
|
||||
#define BD70528_MASK_CHG_BAT_OVERVOLT 0x10
|
||||
#define BD70528_MASK_CHG_BAT_DETECT 0x1
|
||||
#define BD70528_MASK_CHG_DCIN1_UVLO 0x1
|
||||
#define BD70528_MASK_CHG_DCIN_ILIM 0x3f
|
||||
#define BD70528_MASK_CHG_CHG_CURR 0x1f
|
||||
#define BD70528_MASK_CHG_TRICKLE_CURR 0x10
|
||||
|
||||
/*
|
||||
* Note, external battery register is the lonely rider at
|
||||
* address 0xc5. See how to stuff that in the regmap
|
||||
*/
|
||||
#define BD70528_MAX_REGISTER 0x94
|
||||
|
||||
/* Buck control masks */
|
||||
#define BD70528_MASK_RUN_EN 0x4
|
||||
#define BD70528_MASK_STBY_EN 0x2
|
||||
#define BD70528_MASK_IDLE_EN 0x1
|
||||
#define BD70528_MASK_LED1_EN 0x1
|
||||
#define BD70528_MASK_LED2_EN 0x10
|
||||
|
||||
#define BD70528_MASK_BUCK_VOLT 0xf
|
||||
#define BD70528_MASK_LDO_VOLT 0x1f
|
||||
#define BD70528_MASK_LED1_VOLT 0x1
|
||||
#define BD70528_MASK_LED2_VOLT 0x10
|
||||
|
||||
/* Misc irq masks */
|
||||
#define BD70528_INT_MASK_SHORT_PUSH 1
|
||||
#define BD70528_INT_MASK_AUTO_WAKE 2
|
||||
#define BD70528_INT_MASK_POWER_STATE 4
|
||||
|
||||
#define BD70528_MASK_BUCK_RAMP 0x10
|
||||
#define BD70528_SIFT_BUCK_RAMP 4
|
||||
|
||||
#if IS_ENABLED(CONFIG_BD70528_WATCHDOG)
|
||||
|
||||
int bd70528_wdt_set(struct rohm_regmap_dev *data, int enable, int *old_state);
|
||||
void bd70528_wdt_lock(struct rohm_regmap_dev *data);
|
||||
void bd70528_wdt_unlock(struct rohm_regmap_dev *data);
|
||||
|
||||
#else /* CONFIG_BD70528_WATCHDOG */
|
||||
|
||||
static inline int bd70528_wdt_set(struct rohm_regmap_dev *data, int enable,
|
||||
int *old_state)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline void bd70528_wdt_lock(struct rohm_regmap_dev *data)
|
||||
{
|
||||
}
|
||||
|
||||
static inline void bd70528_wdt_unlock(struct rohm_regmap_dev *data)
|
||||
{
|
||||
}
|
||||
|
||||
#endif /* CONFIG_BD70528_WATCHDOG */
|
||||
|
||||
#endif /* __LINUX_MFD_BD70528_H__ */
|
||||
Loading…
Reference in New Issue