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ARM: SoC fixes for 3.20-rc1 

A few fixes that came in too late to make it into the first set of pull
 requests but would still be nice to have in -rc1. The majority of these
 are trivial build fixes for bugs that I found myself using randconfig
 testing, and a set of two patches from Uwe to mark DT strings as 'const'
 where appropriate, to resolve inconsistent section attributes.
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Merge tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC fixes from Arnd Bergmann:
 "A few fixes that came in too late to make it into the first set of
  pull requests but would still be nice to have in -rc1.

  The majority of these are trivial build fixes for bugs that I found
  myself using randconfig testing, and a set of two patches from Uwe to
  mark DT strings as 'const' where appropriate, to resolve inconsistent
  section attributes"

* tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
  ARM: make of_device_ids const
  ARM: make arrays containing machine compatible strings const
  ARM: mm: Remove Kconfig symbol CACHE_PL310
  ARM: rockchip: force built-in regulator support for PM
  ARM: mvebu: build armada375-smp code conditionally
  ARM: sti: always enable RESET_CONTROLLER
  ARM: rockchip: make rockchip_suspend_init conditional
  ARM: ixp4xx: fix {in,out}s{bwl} data types
  ARM: prima2: do not select SMP_ON_UP
  ARM: at91: fix pm declarations
  ARM: davinci: multi-soc kernels require AUTO_ZRELADDR
  ARM: davinci: davinci_cfg_reg cannot be init
  ARM: BCM: put back ARCH_MULTI_V7 dependency for mobile
  ARM: vexpress: use ARM_CPU_SUSPEND if needed
  ARM: dts: add I2C device nodes for Broadcom Cygnus
  ARM: dts: BCM63xx: fix L2 cache properties
This commit is contained in:
Linus Torvalds 2015-02-21 19:21:54 -08:00
parent c8c6c9ba39 444d2d33d8
commit 2177033233
41 changed files with 88 additions and 58 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

20
arch/arm/boot/dts/bcm-cygnus.dtsi
View File

@ -70,6 +70,26 @@
};
};
i2c0: i2c@18008000 {
compatible = "brcm,cygnus-iproc-i2c", "brcm,iproc-i2c";
reg = <0x18008000 0x100>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 85 IRQ_TYPE_NONE>;
clock-frequency = <100000>;
status = "disabled";
};
i2c1: i2c@1800b000 {
compatible = "brcm,cygnus-iproc-i2c", "brcm,iproc-i2c";
reg = <0x1800b000 0x100>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 86 IRQ_TYPE_NONE>;
clock-frequency = <100000>;
status = "disabled";
};
uart0: serial@18020000 {
compatible = "snps,dw-apb-uart";
reg = <0x18020000 0x100>;

5
arch/arm/boot/dts/bcm63138.dtsi
View File

@ -66,8 +66,9 @@
reg = <0x1d000 0x1000>;
cache-unified;
cache-level = <2>;
cache-sets = <16>;
cache-size = <0x80000>;
cache-size = <524288>;
cache-sets = <1024>;
cache-line-size = <32>;
interrupts = <GIC_PPI 0 IRQ_TYPE_LEVEL_HIGH>;
};

2
arch/arm/kernel/perf_event_cpu.c
View File

@ -231,7 +231,7 @@ static void cpu_pmu_destroy(struct arm_pmu *cpu_pmu)
/*
* PMU platform driver and devicetree bindings.
*/
static struct of_device_id cpu_pmu_of_device_ids[] = {
static const struct of_device_id cpu_pmu_of_device_ids[] = {
{.compatible = "arm,cortex-a17-pmu", .data = armv7_a17_pmu_init},
{.compatible = "arm,cortex-a15-pmu", .data = armv7_a15_pmu_init},
{.compatible = "arm,cortex-a12-pmu", .data = armv7_a12_pmu_init},

1
arch/arm/mach-at91/Kconfig
View File

@ -64,7 +64,6 @@ config SOC_SAMA5D4
select SOC_SAMA5
select CLKSRC_MMIO
select CACHE_L2X0
select CACHE_PL310
select HAVE_FB_ATMEL
select HAVE_AT91_UTMI
select HAVE_AT91_SMD

2
arch/arm/mach-at91/at91rm9200_time.c
View File

@ -183,7 +183,7 @@ static struct clock_event_device clkevt = {
void __iomem *at91_st_base;
EXPORT_SYMBOL_GPL(at91_st_base);
static struct of_device_id at91rm9200_st_timer_ids[] = {
static const struct of_device_id at91rm9200_st_timer_ids[] = {
{ .compatible = "atmel,at91rm9200-st" },
{ /* sentinel */ }
};

8
arch/arm/mach-at91/generic.h
View File

@ -35,10 +35,10 @@ extern void __init at91sam9260_pm_init(void);
extern void __init at91sam9g45_pm_init(void);
extern void __init at91sam9x5_pm_init(void);
#else
void __init at91rm9200_pm_init(void) { }
void __init at91sam9260_pm_init(void) { }
void __init at91sam9g45_pm_init(void) { }
void __init at91sam9x5_pm_init(void) { }
static inline void __init at91rm9200_pm_init(void) { }
static inline void __init at91sam9260_pm_init(void) { }
static inline void __init at91sam9g45_pm_init(void) { }
static inline void __init at91sam9x5_pm_init(void) { }
#endif
#endif /* _AT91_GENERIC_H */

4
arch/arm/mach-at91/pm.c
View File

@ -226,7 +226,7 @@ void at91_pm_set_standby(void (*at91_standby)(void))
}
}
static struct of_device_id ramc_ids[] = {
static const struct of_device_id ramc_ids[] __initconst = {
{ .compatible = "atmel,at91rm9200-sdramc", .data = at91rm9200_standby },
{ .compatible = "atmel,at91sam9260-sdramc", .data = at91sam9_sdram_standby },
{ .compatible = "atmel,at91sam9g45-ddramc", .data = at91_ddr_standby },
@ -234,7 +234,7 @@ static struct of_device_id ramc_ids[] = {
{ /*sentinel*/ }
};
static void at91_dt_ramc(void)
static __init void at91_dt_ramc(void)
{
struct device_node *np;
const struct of_device_id *of_id;

2
arch/arm/mach-axxia/axxia.c
View File

@ -16,7 +16,7 @@
#include <linux/init.h>
#include <asm/mach/arch.h>
static const char *axxia_dt_match[] __initconst = {
static const char *const axxia_dt_match[] __initconst = {
"lsi,axm5516",
"lsi,axm5516-sim",
"lsi,axm5516-emu",

4
arch/arm/mach-bcm/Kconfig
View File

@ -68,7 +68,7 @@ config ARCH_BCM_MOBILE
This enables support for systems based on Broadcom mobile SoCs.
config ARCH_BCM_281XX
bool "Broadcom BCM281XX SoC family"
bool "Broadcom BCM281XX SoC family" if ARCH_MULTI_V7
select ARCH_BCM_MOBILE
select HAVE_SMP
help
@ -77,7 +77,7 @@ config ARCH_BCM_281XX
variants.
config ARCH_BCM_21664
bool "Broadcom BCM21664 SoC family"
bool "Broadcom BCM21664 SoC family" if ARCH_MULTI_V7
select ARCH_BCM_MOBILE
select HAVE_SMP
help

2
arch/arm/mach-bcm/brcmstb.c
View File

@ -17,7 +17,7 @@
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
static const char *brcmstb_match[] __initconst = {
static const char *const brcmstb_match[] __initconst = {
"brcm,bcm7445",
"brcm,brcmstb",
NULL

2
arch/arm/mach-davinci/Kconfig
View File

@ -32,12 +32,14 @@ config ARCH_DAVINCI_DM646x
config ARCH_DAVINCI_DA830
bool "DA830/OMAP-L137/AM17x based system"
depends on !ARCH_DAVINCI_DMx || AUTO_ZRELADDR
select ARCH_DAVINCI_DA8XX
select CPU_DCACHE_WRITETHROUGH # needed on silicon revs 1.0, 1.1
select CP_INTC
config ARCH_DAVINCI_DA850
bool "DA850/OMAP-L138/AM18x based system"
depends on !ARCH_DAVINCI_DMx || AUTO_ZRELADDR
select ARCH_DAVINCI_DA8XX
select CP_INTC

2
arch/arm/mach-davinci/da8xx-dt.c
View File

@ -20,7 +20,7 @@
#define DA8XX_NUM_UARTS 3
static struct of_device_id da8xx_irq_match[] __initdata = {
static const struct of_device_id da8xx_irq_match[] __initconst = {
{ .compatible = "ti,cp-intc", .data = cp_intc_of_init, },
{ }
};

4
arch/arm/mach-davinci/mux.c
View File

@ -30,7 +30,7 @@ static void __iomem *pinmux_base;
/*
* Sets the DAVINCI MUX register based on the table
*/
int __init_or_module davinci_cfg_reg(const unsigned long index)
int davinci_cfg_reg(const unsigned long index)
{
static DEFINE_SPINLOCK(mux_spin_lock);
struct davinci_soc_info *soc_info = &davinci_soc_info;
@ -101,7 +101,7 @@ int __init_or_module davinci_cfg_reg(const unsigned long index)
}
EXPORT_SYMBOL(davinci_cfg_reg);
int __init_or_module davinci_cfg_reg_list(const short pins[])
int davinci_cfg_reg_list(const short pins[])
{
int i, error = -EINVAL;

2
arch/arm/mach-exynos/exynos.c
View File

@ -227,7 +227,7 @@ static void __init exynos_dt_machine_init(void)
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
}
static char const *exynos_dt_compat[] __initconst = {
static char const *const exynos_dt_compat[] __initconst = {
"samsung,exynos3",
"samsung,exynos3250",
"samsung,exynos4",

2
arch/arm/mach-exynos/suspend.c
View File

@ -587,7 +587,7 @@ static struct exynos_pm_data exynos5420_pm_data = {
.cpu_suspend = exynos5420_cpu_suspend,
};
static struct of_device_id exynos_pmu_of_device_ids[] = {
static const struct of_device_id exynos_pmu_of_device_ids[] __initconst = {
{
.compatible = "samsung,exynos3250-pmu",
.data = &exynos3250_pm_data,

2
arch/arm/mach-highbank/highbank.c
View File

@ -169,7 +169,7 @@ static void __init highbank_init(void)
platform_device_register(&highbank_cpuidle_device);
}
static const char *highbank_match[] __initconst = {
static const char *const highbank_match[] __initconst = {
"calxeda,highbank",
"calxeda,ecx-2000",
NULL,

8
arch/arm/mach-hisi/hisilicon.c
View File

@ -45,7 +45,7 @@ static void __init hi3620_map_io(void)
iotable_init(hi3620_io_desc, ARRAY_SIZE(hi3620_io_desc));
}
static const char *hi3xxx_compat[] __initconst = {
static const char *const hi3xxx_compat[] __initconst = {
"hisilicon,hi3620-hi4511",
NULL,
};
@ -55,7 +55,7 @@ DT_MACHINE_START(HI3620, "Hisilicon Hi3620 (Flattened Device Tree)")
.dt_compat = hi3xxx_compat,
MACHINE_END
static const char *hix5hd2_compat[] __initconst = {
static const char *const hix5hd2_compat[] __initconst = {
"hisilicon,hix5hd2",
NULL,
};
@ -64,7 +64,7 @@ DT_MACHINE_START(HIX5HD2_DT, "Hisilicon HIX5HD2 (Flattened Device Tree)")
.dt_compat = hix5hd2_compat,
MACHINE_END
static const char *hip04_compat[] __initconst = {
static const char *const hip04_compat[] __initconst = {
"hisilicon,hip04-d01",
NULL,
};
@ -73,7 +73,7 @@ DT_MACHINE_START(HIP04, "Hisilicon HiP04 (Flattened Device Tree)")
.dt_compat = hip04_compat,
MACHINE_END
static const char *hip01_compat[] __initconst = {
static const char *const hip01_compat[] __initconst = {
"hisilicon,hip01",
"hisilicon,hip01-ca9x2",
NULL,

2
arch/arm/mach-imx/mmdc.c
View File

@ -68,7 +68,7 @@ int imx_mmdc_get_ddr_type(void)
return ddr_type;
}
static struct of_device_id imx_mmdc_dt_ids[] = {
static const struct of_device_id imx_mmdc_dt_ids[] = {
{ .compatible = "fsl,imx6q-mmdc", },
{ /* sentinel */ }
};

19
arch/arm/mach-ixp4xx/include/mach/io.h
View File

@ -245,8 +245,10 @@ static inline void outb(u8 value, u32 addr)
}
#define outsb outsb
static inline void outsb(u32 io_addr, const u8 *vaddr, u32 count)
static inline void outsb(u32 io_addr, const void *p, u32 count)
{
const u8 *vaddr = p;
while (count--)
outb(*vaddr++, io_addr);
}
@ -262,8 +264,9 @@ static inline void outw(u16 value, u32 addr)
}
#define outsw outsw
static inline void outsw(u32 io_addr, const u16 *vaddr, u32 count)
static inline void outsw(u32 io_addr, const void *p, u32 count)
{
const u16 *vaddr = p;
while (count--)
outw(cpu_to_le16(*vaddr++), io_addr);
}
@ -275,8 +278,9 @@ static inline void outl(u32 value, u32 addr)
}
#define outsl outsl
static inline void outsl(u32 io_addr, const u32 *vaddr, u32 count)
static inline void outsl(u32 io_addr, const void *p, u32 count)
{
const u32 *vaddr = p;
while (count--)
outl(cpu_to_le32(*vaddr++), io_addr);
}
@ -294,8 +298,9 @@ static inline u8 inb(u32 addr)
}
#define insb insb
static inline void insb(u32 io_addr, u8 *vaddr, u32 count)
static inline void insb(u32 io_addr, void *p, u32 count)
{
u8 *vaddr = p;
while (count--)
*vaddr++ = inb(io_addr);
}
@ -313,8 +318,9 @@ static inline u16 inw(u32 addr)
}
#define insw insw
static inline void insw(u32 io_addr, u16 *vaddr, u32 count)
static inline void insw(u32 io_addr, void *p, u32 count)
{
u16 *vaddr = p;
while (count--)
*vaddr++ = le16_to_cpu(inw(io_addr));
}
@ -330,8 +336,9 @@ static inline u32 inl(u32 addr)
}
#define insl insl
static inline void insl(u32 io_addr, u32 *vaddr, u32 count)
static inline void insl(u32 io_addr, void *p, u32 count)
{
u32 *vaddr = p;
while (count--)
*vaddr++ = le32_to_cpu(inl(io_addr));
}

2
arch/arm/mach-keystone/keystone.c
View File

@ -103,7 +103,7 @@ static void __init keystone_init_meminfo(void)
pr_info("Switching to high address space at 0x%llx\n", (u64)offset);
}
static const char *keystone_match[] __initconst = {
static const char *const keystone_match[] __initconst = {
"ti,keystone",
NULL,
};

2
arch/arm/mach-keystone/pm_domain.c
View File

@ -61,7 +61,7 @@ static struct pm_clk_notifier_block platform_domain_notifier = {
.pm_domain = &keystone_pm_domain,
};
static struct of_device_id of_keystone_table[] = {
static const struct of_device_id of_keystone_table[] = {
{.compatible = "ti,keystone"},
{ /* end of list */ },
};

2
arch/arm/mach-mmp/time.c
View File

@ -213,7 +213,7 @@ void __init timer_init(int irq)
}
#ifdef CONFIG_OF
static struct of_device_id mmp_timer_dt_ids[] = {
static const struct of_device_id mmp_timer_dt_ids[] = {
{ .compatible = "mrvl,mmp-timer", },
{}
};

2
arch/arm/mach-mvebu/coherency.c
View File

@ -51,7 +51,7 @@ enum {
COHERENCY_FABRIC_TYPE_ARMADA_380,
};
static struct of_device_id of_coherency_table[] = {
static const struct of_device_id of_coherency_table[] = {
{.compatible = "marvell,coherency-fabric",
.data = (void *) COHERENCY_FABRIC_TYPE_ARMADA_370_XP },
{.compatible = "marvell,armada-375-coherency-fabric",

2
arch/arm/mach-mvebu/pmsu.c
View File

@ -104,7 +104,7 @@ static void __iomem *pmsu_mp_base;
static void *mvebu_cpu_resume;
static struct of_device_id of_pmsu_table[] = {
static const struct of_device_id of_pmsu_table[] = {
{ .compatible = "marvell,armada-370-pmsu", },
{ .compatible = "marvell,armada-370-xp-pmsu", },
{ .compatible = "marvell,armada-380-pmsu", },

2
arch/arm/mach-mvebu/system-controller.c
View File

@ -126,7 +126,7 @@ int mvebu_system_controller_get_soc_id(u32 *dev, u32 *rev)
return -ENODEV;
}
#ifdef CONFIG_SMP
#if defined(CONFIG_SMP) && defined(CONFIG_MACH_MVEBU_V7)
void mvebu_armada375_smp_wa_init(void)
{
u32 dev, rev;

2
arch/arm/mach-nspire/nspire.c
View File

@ -27,7 +27,7 @@
#include "mmio.h"
#include "clcd.h"
static const char *nspire_dt_match[] __initconst = {
static const char *const nspire_dt_match[] __initconst = {
"ti,nspire",
"ti,nspire-cx",
"ti,nspire-tp",

2
arch/arm/mach-omap2/omap4-common.c
View File

@ -242,7 +242,7 @@ static int __init omap4_sar_ram_init(void)
}
omap_early_initcall(omap4_sar_ram_init);
static struct of_device_id gic_match[] = {
static const struct of_device_id gic_match[] = {
{ .compatible = "arm,cortex-a9-gic", },
{ .compatible = "arm,cortex-a15-gic", },
{ },

2
arch/arm/mach-omap2/prm3xxx.c
View File

@ -674,7 +674,7 @@ int __init omap3xxx_prm_init(void)
return prm_register(&omap3xxx_prm_ll_data);
}
static struct of_device_id omap3_prm_dt_match_table[] = {
static const struct of_device_id omap3_prm_dt_match_table[] = {
{ .compatible = "ti,omap3-prm" },
{ }
};

2
arch/arm/mach-omap2/prm44xx.c
View File

@ -712,7 +712,7 @@ int __init omap44xx_prm_init(void)
return prm_register(&omap44xx_prm_ll_data);
}
static struct of_device_id omap_prm_dt_match_table[] = {
static const struct of_device_id omap_prm_dt_match_table[] = {
{ .compatible = "ti,omap4-prm" },
{ .compatible = "ti,omap5-prm" },
{ .compatible = "ti,dra7-prm" },

1
arch/arm/mach-prima2/Kconfig
View File

@ -27,7 +27,6 @@ config ARCH_ATLAS7
select CPU_V7
select HAVE_ARM_SCU if SMP
select HAVE_SMP
select SMP_ON_UP if SMP
help
Support for CSR SiRFSoC ARM Cortex A7 Platform

6
arch/arm/mach-prima2/common.c
View File

@ -21,7 +21,7 @@ static void __init sirfsoc_init_late(void)
}
#ifdef CONFIG_ARCH_ATLAS6
static const char *atlas6_dt_match[] __initconst = {
static const char *const atlas6_dt_match[] __initconst = {
"sirf,atlas6",
NULL
};
@ -36,7 +36,7 @@ MACHINE_END
#endif
#ifdef CONFIG_ARCH_PRIMA2
static const char *prima2_dt_match[] __initconst = {
static const char *const prima2_dt_match[] __initconst = {
"sirf,prima2",
NULL
};
@ -52,7 +52,7 @@ MACHINE_END
#endif
#ifdef CONFIG_ARCH_ATLAS7
static const char *atlas7_dt_match[] __initdata = {
static const char *const atlas7_dt_match[] __initconst = {
"sirf,atlas7",
NULL
};

2
arch/arm/mach-prima2/platsmp.c
View File

@ -40,7 +40,7 @@ static void sirfsoc_secondary_init(unsigned int cpu)
spin_unlock(&boot_lock);
}
static struct of_device_id clk_ids[] = {
static const struct of_device_id clk_ids[] = {
{ .compatible = "sirf,atlas7-clkc" },
{},
};

1
arch/arm/mach-rockchip/Kconfig
View File

@ -11,6 +11,7 @@ config ARCH_ROCKCHIP
select HAVE_ARM_SCU if SMP
select HAVE_ARM_TWD if SMP
select DW_APB_TIMER_OF
select REGULATOR if PM
select ROCKCHIP_TIMER
select ARM_GLOBAL_TIMER
select CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK

6
arch/arm/mach-rockchip/pm.h
View File

@ -24,7 +24,13 @@ extern unsigned long rkpm_bootdata_ddr_data;
extern unsigned long rk3288_bootram_sz;
void rockchip_slp_cpu_resume(void);
#ifdef CONFIG_PM_SLEEP
void __init rockchip_suspend_init(void);
#else
static inline void rockchip_suspend_init(void)
{
}
#endif
/****** following is rk3288 defined **********/
#define RK3288_PMU_WAKEUP_CFG0 0x00

2
arch/arm/mach-s5pv210/s5pv210.c
View File

@ -63,7 +63,7 @@ static void __init s5pv210_dt_init_late(void)
s5pv210_pm_init();
}
static char const *s5pv210_dt_compat[] __initconst = {
static char const *const s5pv210_dt_compat[] __initconst = {
"samsung,s5pc110",
"samsung,s5pv210",
NULL

2
arch/arm/mach-shmobile/setup-emev2.c
View File

@ -37,7 +37,7 @@ static void __init emev2_map_io(void)
iotable_init(emev2_io_desc, ARRAY_SIZE(emev2_io_desc));
}
static const char *emev2_boards_compat_dt[] __initconst = {
static const char *const emev2_boards_compat_dt[] __initconst = {
"renesas,emev2",
NULL,
};

1
arch/arm/mach-sti/Kconfig
View File

@ -13,6 +13,7 @@ menuconfig ARCH_STI
select ARM_ERRATA_775420
select PL310_ERRATA_753970 if CACHE_L2X0
select PL310_ERRATA_769419 if CACHE_L2X0
select RESET_CONTROLLER
help
Include support for STiH41x SOCs like STiH415/416 using the device tree
for discovery

2
arch/arm/mach-ux500/pm_domains.c
View File

@ -49,7 +49,7 @@ static struct generic_pm_domain *ux500_pm_domains[NR_DOMAINS] = {
[DOMAIN_VAPE] = &ux500_pm_domain_vape,
};
static struct of_device_id ux500_pm_domain_matches[] = {
static const struct of_device_id ux500_pm_domain_matches[] __initconst = {
{ .compatible = "stericsson,ux500-pm-domains", },
{ },
};

2
arch/arm/mach-versatile/versatile_dt.c
View File

@ -35,7 +35,7 @@ static void __init versatile_dt_init(void)
versatile_auxdata_lookup, NULL);
}
static const char *versatile_dt_match[] __initconst = {
static const char *const versatile_dt_match[] __initconst = {
"arm,versatile-ab",
"arm,versatile-pb",
NULL,

1
arch/arm/mach-vexpress/Kconfig
View File

@ -73,6 +73,7 @@ config ARCH_VEXPRESS_TC2_PM
depends on MCPM
select ARM_CCI
select ARCH_VEXPRESS_SPC
select ARM_CPU_SUSPEND
help
Support for CPU and cluster power management on Versatile Express
with a TC2 (A15x2 A7x3) big.LITTLE core tile.

7
arch/arm/mm/Kconfig
View File

@ -892,13 +892,6 @@ config CACHE_L2X0
if CACHE_L2X0
config CACHE_PL310
bool
default y if CPU_V7 && !(CPU_V6 || CPU_V6K)
help
This option enables optimisations for the PL310 cache
controller.
config PL310_ERRATA_588369
bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
help