staging:r819xU: coding style: Fixed commenting style
This is a patch to the r819xU_phyreg.h file that fixes commenting style warning Signed-off-by: Sanjeev Sharma <Sanjeev_Sharma@mentor.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Sanjeev Sharma
Greg Kroah-Hartman
parent
2892d39797
commit
2160e944a9
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@ -2,10 +2,11 @@
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#define _R819XU_PHYREG_H
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#define RF_DATA 0x1d4 // FW will write RF data in the register.
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#define RF_DATA 0x1d4 /* FW will write RF data in the register.*/
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//Register //duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF
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//page 1
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/* Register duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF
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* page 1
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*/
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#define rPMAC_Reset 0x100
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#define rPMAC_TxStart 0x104
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#define rPMAC_TxLegacySIG 0x108
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@ -34,15 +35,16 @@
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#define rPMAC_CCKCRxRC32OK 0x188
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#define rPMAC_TxStatus 0x18c
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//page8
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#define rFPGA0_RFMOD 0x800 //RF mode & CCK TxSC
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/* page8 */
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#define rFPGA0_RFMOD 0x800 /* RF mode & CCK TxSC */
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#define rFPGA0_TxInfo 0x804
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#define rFPGA0_PSDFunction 0x808
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#define rFPGA0_TxGainStage 0x80c
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#define rFPGA0_RFTiming1 0x810
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#define rFPGA0_RFTiming2 0x814
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//#define rFPGA0_XC_RFTiming 0x818
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//#define rFPGA0_XD_RFTiming 0x81c
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/* #define rFPGA0_XC_RFTiming 0x818
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* #define rFPGA0_XD_RFTiming 0x81c
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*/
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#define rFPGA0_XA_HSSIParameter1 0x820
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#define rFPGA0_XA_HSSIParameter2 0x824
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#define rFPGA0_XB_HSSIParameter1 0x828
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@ -79,51 +81,51 @@
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#define rFPGA0_XAB_RFInterfaceRB 0x8e0
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#define rFPGA0_XCD_RFInterfaceRB 0x8e4
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//page 9
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#define rFPGA1_RFMOD 0x900 //RF mode & OFDM TxSC
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/* page 9 */
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#define rFPGA1_RFMOD 0x900 /* RF mode & OFDM TxSC */
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#define rFPGA1_TxBlock 0x904
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#define rFPGA1_DebugSelect 0x908
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#define rFPGA1_TxInfo 0x90c
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//page a
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/* page a */
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#define rCCK0_System 0xa00
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#define rCCK0_AFESetting 0xa04
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#define rCCK0_CCA 0xa08
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#define rCCK0_RxAGC1 0xa0c //AGC default value, saturation level
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#define rCCK0_RxAGC2 0xa10 //AGC & DAGC
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#define rCCK0_RxAGC1 0xa0c /* AGC default value, saturation level */
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#define rCCK0_RxAGC2 0xa10 /* AGC & DAGC */
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#define rCCK0_RxHP 0xa14
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#define rCCK0_DSPParameter1 0xa18 //Timing recovery & Channel estimation threshold
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#define rCCK0_DSPParameter2 0xa1c //SQ threshold
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#define rCCK0_DSPParameter1 0xa18 /* Timing recovery & Channel estimation threshold */
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#define rCCK0_DSPParameter2 0xa1c /* SQ threshold */
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#define rCCK0_TxFilter1 0xa20
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#define rCCK0_TxFilter2 0xa24
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#define rCCK0_DebugPort 0xa28 //debug port and Tx filter3
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#define rCCK0_FalseAlarmReport 0xa2c //0xa2d
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#define rCCK0_DebugPort 0xa28 /* debug port and Tx filter3 */
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#define rCCK0_FalseAlarmReport 0xa2c /* 0xa2d */
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#define rCCK0_TRSSIReport 0xa50
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#define rCCK0_RxReport 0xa54 //0xa57
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#define rCCK0_FACounterLower 0xa5c //0xa5b
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#define rCCK0_FACounterUpper 0xa58 //0xa5c
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#define rCCK0_RxReport 0xa54 /* 0xa57 */
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#define rCCK0_FACounterLower 0xa5c /* 0xa5b */
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#define rCCK0_FACounterUpper 0xa58 /* 0xa5c */
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//page c
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/* page c */
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#define rOFDM0_LSTF 0xc00
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#define rOFDM0_TRxPathEnable 0xc04
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#define rOFDM0_TRMuxPar 0xc08
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#define rOFDM0_TRSWIsolation 0xc0c
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#define rOFDM0_XARxAFE 0xc10 //RxIQ DC offset, Rx digital filter, DC notch filter
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#define rOFDM0_XARxIQImbalance 0xc14 //RxIQ imblance matrix
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#define rOFDM0_XARxAFE 0xc10 /* RxIQ DC offset, Rx digital filter, DC notch filter */
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#define rOFDM0_XARxIQImbalance 0xc14 /* RxIQ imblance matrix */
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#define rOFDM0_XBRxAFE 0xc18
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#define rOFDM0_XBRxIQImbalance 0xc1c
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#define rOFDM0_XCRxAFE 0xc20
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#define rOFDM0_XCRxIQImbalance 0xc24
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#define rOFDM0_XDRxAFE 0xc28
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#define rOFDM0_XDRxIQImbalance 0xc2c
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#define rOFDM0_RxDetector1 0xc30 //PD,BW & SBD
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#define rOFDM0_RxDetector2 0xc34 //SBD & Fame Sync.
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#define rOFDM0_RxDetector3 0xc38 //Frame Sync.
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#define rOFDM0_RxDetector4 0xc3c //PD, SBD, Frame Sync & Short-GI
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#define rOFDM0_RxDSP 0xc40 //Rx Sync Path
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#define rOFDM0_CFOandDAGC 0xc44 //CFO & DAGC
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#define rOFDM0_CCADropThreshold 0xc48 //CCA Drop threshold
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#define rOFDM0_ECCAThreshold 0xc4c // energy CCA
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#define rOFDM0_RxDetector1 0xc30 /* PD,BW & SBD */
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#define rOFDM0_RxDetector2 0xc34 /* SBD & Fame Sync.*/
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#define rOFDM0_RxDetector3 0xc38 /* Frame Sync.*/
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#define rOFDM0_RxDetector4 0xc3c /* PD, SBD, Frame Sync & Short-GI */
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#define rOFDM0_RxDSP 0xc40 /* Rx Sync Path */
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#define rOFDM0_CFOandDAGC 0xc44 /* CFO & DAGC */
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#define rOFDM0_CCADropThreshold 0xc48 /* CCA Drop threshold */
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#define rOFDM0_ECCAThreshold 0xc4c /* energy CCA */
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#define rOFDM0_XAAGCCore1 0xc50
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#define rOFDM0_XAAGCCore2 0xc54
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#define rOFDM0_XBAGCCore1 0xc58
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@ -156,7 +158,7 @@
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#define rOFDM0_TxCoeff6 0xcb8
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//page d
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/* page d */
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#define rOFDM1_LSTF 0xd00
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#define rOFDM1_TRxPathEnable 0xd04
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#define rOFDM1_CFO 0xd08
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@ -169,9 +171,10 @@
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#define rOFDM1_PseudoNoiseStateAB 0xd50
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#define rOFDM1_PseudoNoiseStateCD 0xd54
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#define rOFDM1_RxPseudoNoiseWgt 0xd58
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#define rOFDM_PHYCounter1 0xda0 //cca, parity fail
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#define rOFDM_PHYCounter2 0xda4 //rate illegal, crc8 fail
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#define rOFDM_PHYCounter3 0xda8 //MCS not support
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#define rOFDM_PHYCounter1 0xda0 /* cca, parity fail */
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#define rOFDM_PHYCounter2 0xda4 /* rate illegal, crc8 fail */
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#define rOFDM_PHYCounter3 0xda8 /* MCS not support */
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#define rOFDM_ShortCFOAB 0xdac
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#define rOFDM_ShortCFOCD 0xdb0
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#define rOFDM_LongCFOAB 0xdb4
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@ -186,7 +189,7 @@
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#define rOFDM_RxEVMCSI 0xdd8
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#define rOFDM_SIGReport 0xddc
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//page e
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/* page e */
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#define rTxAGC_Rate18_06 0xe00
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#define rTxAGC_Rate54_24 0xe04
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#define rTxAGC_CCK_Mcs32 0xe08
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@ -196,8 +199,9 @@
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#define rTxAGC_Mcs15_Mcs12 0xe1c
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//RF
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//Zebra1
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/* RF
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* Zebra1
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*/
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#define rZebra1_HSSIEnable 0x0
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#define rZebra1_TRxEnable1 0x1
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#define rZebra1_TRxEnable2 0x2
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@ -209,18 +213,19 @@
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#define rZebra1_RxLPF 0xb
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#define rZebra1_RxHPFCorner 0xc
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//Zebra4
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/* Zebra4 */
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#define rGlobalCtrl 0
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#define rRTL8256_TxLPF 19
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#define rRTL8256_RxLPF 11
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//RTL8258
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/* RTL8258 */
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#define rRTL8258_TxLPF 0x11
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#define rRTL8258_RxLPF 0x13
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#define rRTL8258_RSSILPF 0xa
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//Bit Mask
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//page-1
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/* Bit Mask
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* page-1
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*/
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#define bBBResetB 0x100
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#define bGlobalResetB 0x200
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#define bOFDMTxStart 0x4
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@ -266,7 +271,7 @@
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#define bCCKTxStatus 0x1
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#define bOFDMTxStatus 0x2
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//page-8
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/* page-8 */
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#define bRFMOD 0x1
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#define bJapanMode 0x2
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#define bCCKTxSC 0x30
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@ -283,14 +288,14 @@
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#define bRFStart 0x0000f000
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#define bBBStart 0x000000f0
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#define bBBCCKStart 0x0000000f
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#define bPAEnd 0xf //Reg0x814
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#define bPAEnd 0xf /* Reg0x814 */
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#define bTREnd 0x0f000000
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#define bRFEnd 0x000f0000
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#define bCCAMask 0x000000f0 //T2R
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#define bCCAMask 0x000000f0 /* T2R */
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#define bR2RCCAMask 0x00000f00
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#define bHSSI_R2TDelay 0xf8000000
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#define bHSSI_T2RDelay 0xf80000
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#define bContTxHSSI 0x400 //chane gain at continue Tx
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#define bContTxHSSI 0x400 /* chane gain at continue Tx */
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#define bIGFromCCK 0x200
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#define bAGCAddress 0x3f
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#define bRxHPTx 0x7000
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@ -301,7 +306,7 @@
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#define b3WireDataLength 0x800
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#define b3WireAddressLength 0x400
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#define b3WireRFPowerDown 0x1
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//#define bHWSISelect 0x8
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/* #define bHWSISelect 0x8 */
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#define b5GPAPEPolarity 0x40000000
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#define b2GPAPEPolarity 0x80000000
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#define bRFSW_TxDefaultAnt 0x3
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@ -312,7 +317,7 @@
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#define bRFSI_3WireClock 0x2
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#define bRFSI_3WireLoad 0x4
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#define bRFSI_3WireRW 0x8
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#define bRFSI_3Wire 0xf //3-wire total control
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#define bRFSI_3Wire 0xf /* 3-wire total control */
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#define bRFSI_RFENV 0x10
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#define bRFSI_TRSW 0x20
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#define bRFSI_TRSWB 0x40
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@ -337,12 +342,11 @@
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#define bLSIG_Length 0x1fffe
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#define bLSIG_Parity 0x20
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#define bCCKRxPhase 0x4
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#define bLSSIReadAddress 0x3f000000 //LSSI "Read" Address
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#define bLSSIReadEdge 0x80000000 //LSSI "Read" edge signal
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#define bLSSIReadAddress 0x3f000000 /* LSSI "Read" Address */
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#define bLSSIReadEdge 0x80000000 /* LSSI "Read" edge signal */
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#define bLSSIReadBackData 0xfff
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#define bLSSIReadOKFlag 0x1000
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#define bCCKSampleRate 0x8 //0: 44MHz, 1:88MHz
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#define bCCKSampleRate 0x8 /* 0: 44MHz, 1:88MHz */
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#define bRegulator0Standby 0x1
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#define bRegulatorPLLStandby 0x2
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#define bRegulator1Standby 0x4
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@ -395,12 +399,12 @@
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#define bPSDSineToneScale 0x7f000000
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#define bPSDReport 0xffff
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//page-9
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/* page-9 */
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#define bOFDMTxSC 0x30000000
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#define bCCKTxOn 0x1
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#define bOFDMTxOn 0x2
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#define bDebugPage 0xfff //reset debug page and also HWord, LWord
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#define bDebugItem 0xff //reset debug page and LWord
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#define bDebugPage 0xfff /* reset debug page and also HWord, LWord */
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#define bDebugItem 0xff /* reset debug page and LWord */
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#define bAntL 0x10
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#define bAntNonHT 0x100
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#define bAntHT1 0x1000
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@ -408,7 +412,7 @@
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#define bAntHT1S1 0x100000
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#define bAntNonHTS1 0x1000000
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//page-a
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/* page-a */
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#define bCCKBBMode 0x3
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#define bCCKTxPowerSaving 0x80
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#define bCCKRxPowerSaving 0x40
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@ -429,7 +433,7 @@
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#define bCCKBistMode 0x80000000
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#define bCCKCCAMask 0x40000000
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#define bCCKTxDACPhase 0x4
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#define bCCKRxADCPhase 0x20000000 //r_rx_clk
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#define bCCKRxADCPhase 0x20000000 /* r_rx_clk */
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#define bCCKr_cp_mode0 0x0100
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#define bCCKTxDCOffset 0xf0
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#define bCCKRxDCOffset 0xf
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@ -443,12 +447,12 @@
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#define bCCKRxIG 0x7f00
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#define bCCKLNAPolarity 0x800000
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#define bCCKRx1stGain 0x7f0000
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#define bCCKRFExtend 0x20000000 //CCK Rx initial gain polarity
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#define bCCKRFExtend 0x20000000 /* CCK Rx initial gain polarity */
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#define bCCKRxAGCSatLevel 0x1f000000
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#define bCCKRxAGCSatCount 0xe0
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#define bCCKRxRFSettle 0x1f //AGCsamp_dly
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#define bCCKRxRFSettle 0x1f /* AGCsamp_dly */
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#define bCCKFixedRxAGC 0x8000
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//#define bCCKRxAGCFormat 0x4000 //remove to HSSI register 0x824
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/* #define bCCKRxAGCFormat 0x4000 */ /* remove to HSSI register 0x824 */
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#define bCCKAntennaPolarity 0x2000
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#define bCCKTxFilterType 0x0c00
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#define bCCKRxAGCReportType 0x0300
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@ -489,7 +493,7 @@
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#define bCCKDefaultRxPath 0xc000000
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#define bCCKOptionRxPath 0x3000000
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//page c
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/* page c */
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#define bNumOfSTF 0x3
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#define bShift_L 0xc0
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#define bGI_TH 0xc
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@ -591,8 +595,8 @@
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#define bRxHP_BBP1 0x7000
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#define bRxHP_BBP2 0x70000
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#define bRxHP_BBP3 0x700000
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#define bRSSI_H 0x7f0000 //the threshold for high power
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#define bRSSI_Gen 0x7f000000 //the threshold for ant diversity
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#define bRSSI_H 0x7f0000 /* the threshold for high power */
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#define bRSSI_Gen 0x7f000000 /* the threshold for ant diversity */
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#define bRxSettle_TRSW 0x7
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#define bRxSettle_LNA 0x38
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#define bRxSettle_RSSI 0x1c0
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@ -626,7 +630,7 @@
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#define bRxPD_Delay_TH1 0x38
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#define bRxPD_Delay_TH2 0x1c0
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#define bRxPD_DC_COUNT_MAX 0x600
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//#define bRxMF_Hold 0x3800
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/* #define bRxMF_Hold 0x3800 */
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#define bRxPD_Delay_TH 0x8000
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#define bRxProcess_Delay 0xf0000
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#define bRxSearchrange_GI2_Early 0x700000
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@ -652,7 +656,7 @@
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#define bExtLNAGain 0x7c00
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//page d
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/* page d */
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#define bSTBCEn 0x4
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#define bAntennaMapping 0x10
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#define bNss 0x20
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@ -662,12 +666,13 @@
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#define bOFDMContinueTx 0x10000000
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#define bOFDMSingleCarrier 0x20000000
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#define bOFDMSingleTone 0x40000000
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//#define bRxPath1 0x01
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//#define bRxPath2 0x02
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//#define bRxPath3 0x04
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//#define bRxPath4 0x08
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//#define bTxPath1 0x10
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//#define bTxPath2 0x20
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/* #define bRxPath1 0x01
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* #define bRxPath2 0x02
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* #define bRxPath3 0x04
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* #define bRxPath4 0x08
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* #define bTxPath1 0x10
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* #define bTxPath2 0x20
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*/
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#define bHTDetect 0x100
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#define bCFOEn 0x10000
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#define bCFOValue 0xfff00000
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@ -680,8 +685,8 @@
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#define bCounter_MCSNoSupport 0xffff
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#define bCounter_FastSync 0xffff
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#define bShortCFO 0xfff
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#define bShortCFOTLength 12 //total
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#define bShortCFOFLength 11 //fraction
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#define bShortCFOTLength 12 /* total */
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#define bShortCFOFLength 11 /* fraction */
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#define bLongCFO 0x7ff
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#define bLongCFOTLength 11
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#define bLongCFOFLength 11
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@ -758,7 +763,7 @@
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#define bUChCfg 0x7000000
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#define bUpdEqz 0x8000000
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//page e
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/* page e */
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#define bTxAGCRate18_06 0x7f7f7f7f
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#define bTxAGCRate54_24 0x7f7f7f7f
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#define bTxAGCRateMCS32 0x7f
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@ -769,7 +774,7 @@
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#define bTxAGCRateMCS15_MCS12 0x7f7f7f7f
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//Rx Pseduo noise
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/* Rx Pseduo noise */
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#define bRxPesudoNoiseOn 0x20000000
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#define bRxPesudoNoise_A 0xff
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||||
#define bRxPesudoNoise_B 0xff00
|
||||
|
|
@ -780,8 +785,9 @@
|
|||
#define bPesudoNoiseState_C 0xffff
|
||||
#define bPesudoNoiseState_D 0xffff0000
|
||||
|
||||
//RF
|
||||
//Zebra1
|
||||
/* RF
|
||||
* Zebra1
|
||||
*/
|
||||
#define bZebra1_HSSIEnable 0x8
|
||||
#define bZebra1_TRxControl 0xc00
|
||||
#define bZebra1_TRxGainSetting 0x07f
|
||||
|
|
@ -792,18 +798,18 @@
|
|||
#define bZebra1_TxLPFBW 0x400
|
||||
#define bZebra1_RxLPFBW 0x600
|
||||
|
||||
//Zebra4
|
||||
/* Zebra4 */
|
||||
#define bRTL8256RegModeCtrl1 0x100
|
||||
#define bRTL8256RegModeCtrl0 0x40
|
||||
#define bRTL8256_TxLPFBW 0x18
|
||||
#define bRTL8256_RxLPFBW 0x600
|
||||
|
||||
//RTL8258
|
||||
/* RTL8258 */
|
||||
#define bRTL8258_TxLPFBW 0xc
|
||||
#define bRTL8258_RxLPFBW 0xc00
|
||||
#define bRTL8258_RSSILPFBW 0xc0
|
||||
|
||||
//byte endable for sb_write
|
||||
/* byte endable for sb_write */
|
||||
#define bByte0 0x1
|
||||
#define bByte1 0x2
|
||||
#define bByte2 0x4
|
||||
|
|
@ -812,7 +818,7 @@
|
|||
#define bWord1 0xc
|
||||
#define bDWord 0xf
|
||||
|
||||
//for PutRegsetting & GetRegSetting BitMask
|
||||
/* for PutRegsetting & GetRegSetting BitMask */
|
||||
#define bMaskByte0 0xff
|
||||
#define bMaskByte1 0xff00
|
||||
#define bMaskByte2 0xff0000
|
||||
|
|
@ -821,7 +827,7 @@
|
|||
#define bMaskLWord 0x0000ffff
|
||||
#define bMaskDWord 0xffffffff
|
||||
|
||||
//for PutRFRegsetting & GetRFRegSetting BitMask
|
||||
/* for PutRFRegsetting & GetRFRegSetting BitMask */
|
||||
#define bMask12Bits 0xfff
|
||||
|
||||
#define bEnable 0x1
|
||||
|
|
@ -830,14 +836,14 @@
|
|||
#define LeftAntenna 0x0
|
||||
#define RightAntenna 0x1
|
||||
|
||||
#define tCheckTxStatus 500 //500ms
|
||||
#define tUpdateRxCounter 100 //100ms
|
||||
#define tCheckTxStatus 500 /* 500ms */
|
||||
#define tUpdateRxCounter 100 /* 100ms */
|
||||
|
||||
#define rateCCK 0
|
||||
#define rateOFDM 1
|
||||
#define rateHT 2
|
||||
|
||||
//define Register-End
|
||||
/* define Register-End */
|
||||
#define bPMAC_End 0x1ff
|
||||
#define bFPGAPHY0_End 0x8ff
|
||||
#define bFPGAPHY1_End 0x9ff
|
||||
|
|
@ -845,12 +851,13 @@
|
|||
#define bOFDMPHY0_End 0xcff
|
||||
#define bOFDMPHY1_End 0xdff
|
||||
|
||||
//define max debug item in each debug page
|
||||
//#define bMaxItem_FPGA_PHY0 0x9
|
||||
//#define bMaxItem_FPGA_PHY1 0x3
|
||||
//#define bMaxItem_PHY_11B 0x16
|
||||
//#define bMaxItem_OFDM_PHY0 0x29
|
||||
//#define bMaxItem_OFDM_PHY1 0x0
|
||||
/* define max debug item in each debug page
|
||||
* #define bMaxItem_FPGA_PHY0 0x9
|
||||
* #define bMaxItem_FPGA_PHY1 0x3
|
||||
* #define bMaxItem_PHY_11B 0x16
|
||||
* #define bMaxItem_OFDM_PHY0 0x29
|
||||
* #define bMaxItem_OFDM_PHY1 0x0
|
||||
*/
|
||||
|
||||
#define bPMACControl 0x0
|
||||
#define bWMACControl 0x1
|
||||
|
|
@ -868,4 +875,4 @@
|
|||
#define rRTL8256TxBBBW 19
|
||||
#define bRTL8256TxBBBW 0x18
|
||||
|
||||
#endif //__INC_HAL8190PCIPHYREG_H
|
||||
#endif /* __INC_HAL8190PCIPHYREG_H */
|
||||
|
|
|
|||
Loading…
Reference in New Issue