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drm/nva3: somewhat improve clock reporting 

Definitely not 100% correct, but, for the configurations I've seen used
it'll read back the correct clocks now.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ben Skeggs 2011-04-14 15:02:03 +10:00
parent ce521846b9
commit 215f902e15
1 changed files with 46 additions and 10 deletions
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56
drivers/gpu/drm/nouveau/nva3_pm.c
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@ -27,10 +27,10 @@
#include "nouveau_bios.h" #include "nouveau_bios.h"
#include "nouveau_pm.h" #include "nouveau_pm.h"
/*XXX: boards using limits 0x40 need fixing, the register layout /* This is actually a lot more complex than it appears here, but hopefully
* is correct here, but, there's some other funny magic * this should be able to deal with what the VBIOS leaves for us..
* that modifies things, so it's not likely we'll set/read *
* the correct timings yet.. working on it... * If not, well, I'll jump off that bridge when I come to it.
*/ */
struct nva3_pm_state { struct nva3_pm_state {
@ -38,21 +38,57 @@ struct nva3_pm_state {
int N, M, P; int N, M, P;
}; };
static int
nva3_pm_pll_offset(u32 id)
{
static const u32 pll_map[] = {
0x00, PLL_CORE,
0x01, PLL_SHADER,
0x02, PLL_MEMORY,
0x00, 0x00
};
const u32 *map = pll_map;
while (map[1]) {
if (id == map[1])
return map[0];
map += 2;
}
return -ENOENT;
}
int int
nva3_pm_clock_get(struct drm_device *dev, u32 id) nva3_pm_clock_get(struct drm_device *dev, u32 id)
{ {
u32 src0, src1, ctrl, coef;
struct pll_lims pll; struct pll_lims pll;
int P, N, M, ret; int ret, off;
u32 reg; int P, N, M;
ret = get_pll_limits(dev, id, &pll); ret = get_pll_limits(dev, id, &pll);
if (ret) if (ret)
return ret; return ret;
reg = nv_rd32(dev, pll.reg + 4); off = nva3_pm_pll_offset(id);
P = (reg & 0x003f0000) >> 16; if (off < 0)
N = (reg & 0x0000ff00) >> 8; return off;
M = (reg & 0x000000ff);
src0 = nv_rd32(dev, 0x4120 + (off * 4));
src1 = nv_rd32(dev, 0x4160 + (off * 4));
ctrl = nv_rd32(dev, pll.reg + 0);
coef = nv_rd32(dev, pll.reg + 4);
NV_DEBUG(dev, "PLL %02x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
id, src0, src1, ctrl, coef);
if (ctrl & 0x00000008) {
u32 div = ((src1 & 0x003c0000) >> 18) + 1;
return (pll.refclk * 2) / div;
}
P = (coef & 0x003f0000) >> 16;
N = (coef & 0x0000ff00) >> 8;
M = (coef & 0x000000ff);
return pll.refclk * N / M / P; return pll.refclk * N / M / P;
} }