Merge branch 'ux500/devel' into next/devel
* ux500/devel: ARM: ux500: fix the smp_twd clock calculation ARM: ux500: remove support for early silicon revisions ARM: ux500: update register files ARM: ux500: register DB5500 PMU dynamically ARM: ux500: update ASIC detection for U5500 ARM: ux500: support DB8520
This commit is contained in:
Olof Johansson
commit
2123b16bb6
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@ -21,6 +21,12 @@
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#include "board-mop500.h"
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#include "ste-dma40-db8500.h"
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/*
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* v2 has a new version of this block that need to be forced, the number found
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* in hardware is incorrect
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*/
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#define U8500_SDI_V2_PERIPHID 0x10480180
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/*
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* SDI 0 (MicroSD slot)
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*/
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@ -117,10 +123,7 @@ static void sdi0_configure(void)
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gpio_direction_output(sdi0_en, 1);
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/* Add the device, force v2 to subrevision 1 */
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if (cpu_is_u8500v2())
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db8500_add_sdi0(&mop500_sdi0_data, 0x10480180);
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else
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db8500_add_sdi0(&mop500_sdi0_data, 0);
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db8500_add_sdi0(&mop500_sdi0_data, U8500_SDI_V2_PERIPHID);
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}
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void mop500_sdi_tc35892_init(void)
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@ -194,7 +197,8 @@ static struct stedma40_chan_cfg mop500_sdi2_dma_cfg_tx = {
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static struct mmci_platform_data mop500_sdi2_data = {
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.ocr_mask = MMC_VDD_165_195,
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.f_max = 50000000,
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.capabilities = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
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.capabilities = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA |
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MMC_CAP_MMC_HIGHSPEED,
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.gpio_cd = -1,
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.gpio_wp = -1,
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#ifdef CONFIG_STE_DMA40
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@ -244,20 +248,10 @@ static struct mmci_platform_data mop500_sdi4_data = {
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void __init mop500_sdi_init(void)
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{
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u32 periphid = 0;
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/* v2 has a new version of this block that need to be forced */
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if (cpu_is_u8500v2())
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periphid = 0x10480180;
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/* PoP:ed eMMC on top of DB8500 v1.0 has problems with high speed */
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if (!cpu_is_u8500v10())
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mop500_sdi2_data.capabilities |= MMC_CAP_MMC_HIGHSPEED;
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db8500_add_sdi2(&mop500_sdi2_data, periphid);
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/* PoP:ed eMMC */
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db8500_add_sdi2(&mop500_sdi2_data, U8500_SDI_V2_PERIPHID);
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/* On-board eMMC */
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db8500_add_sdi4(&mop500_sdi4_data, periphid);
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db8500_add_sdi4(&mop500_sdi4_data, U8500_SDI_V2_PERIPHID);
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/*
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* On boards with the TC35892 GPIO expander, sdi0 will finally
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* be added when the TC35892 initializes and calls
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@ -267,13 +261,9 @@ void __init mop500_sdi_init(void)
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void __init snowball_sdi_init(void)
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{
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u32 periphid = 0x10480180;
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mop500_sdi2_data.capabilities |= MMC_CAP_MMC_HIGHSPEED;
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/* On-board eMMC */
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db8500_add_sdi4(&mop500_sdi4_data, periphid);
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db8500_add_sdi4(&mop500_sdi4_data, U8500_SDI_V2_PERIPHID);
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/* External Micro SD slot */
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mop500_sdi0_data.gpio_cd = SNOWBALL_SDMMC_CD_GPIO;
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mop500_sdi0_data.cd_invert = true;
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sdi0_en = SNOWBALL_SDMMC_EN_GPIO;
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@ -283,19 +273,15 @@ void __init snowball_sdi_init(void)
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void __init hrefv60_sdi_init(void)
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{
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u32 periphid = 0x10480180;
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mop500_sdi2_data.capabilities |= MMC_CAP_MMC_HIGHSPEED;
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db8500_add_sdi2(&mop500_sdi2_data, periphid);
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/* PoP:ed eMMC */
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db8500_add_sdi2(&mop500_sdi2_data, U8500_SDI_V2_PERIPHID);
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/* On-board eMMC */
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db8500_add_sdi4(&mop500_sdi4_data, periphid);
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db8500_add_sdi4(&mop500_sdi4_data, U8500_SDI_V2_PERIPHID);
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/* External Micro SD slot */
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mop500_sdi0_data.gpio_cd = HREFV60_SDMMC_CD_GPIO;
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sdi0_en = HREFV60_SDMMC_EN_GPIO;
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sdi0_vsel = HREFV60_SDMMC_1V8_3V_GPIO;
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sdi0_configure();
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db8500_add_sdi1(&mop500_sdi1_data, periphid);
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/* WLAN SDIO channel */
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db8500_add_sdi1(&mop500_sdi1_data, U8500_SDI_V2_PERIPHID);
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}
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@ -239,23 +239,6 @@ static void clk_prcmu_disable(struct clk *clk)
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writel(1 << clk->prcmu_cg_bit, cg_clr_reg);
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}
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/* ED doesn't have the combined set/clr registers */
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static void clk_prcmu_ed_enable(struct clk *clk)
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{
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void __iomem *addr = __io_address(U8500_PRCMU_BASE)
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+ clk->prcmu_cg_mgt;
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writel(readl(addr) | PRCM_MGT_ENABLE, addr);
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}
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static void clk_prcmu_ed_disable(struct clk *clk)
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{
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void __iomem *addr = __io_address(U8500_PRCMU_BASE)
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+ clk->prcmu_cg_mgt;
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writel(readl(addr) & ~PRCM_MGT_ENABLE, addr);
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}
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static struct clkops clk_prcmu_ops = {
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.enable = clk_prcmu_enable,
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.disable = clk_prcmu_disable,
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@ -267,7 +250,6 @@ static unsigned int clkrst_base[] = {
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[3] = U8500_CLKRST3_BASE,
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[5] = U8500_CLKRST5_BASE,
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[6] = U8500_CLKRST6_BASE,
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[7] = U8500_CLKRST7_BASE_ED,
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};
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static void clk_prcc_enable(struct clk *clk)
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@ -321,7 +303,6 @@ static DEFINE_PRCMU_CLK(per2clk, 0x0, 12, PER2CLK);
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static DEFINE_PRCMU_CLK(per3clk, 0x0, 13, PER3CLK);
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static DEFINE_PRCMU_CLK(per5clk, 0x0, 14, PER5CLK);
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static DEFINE_PRCMU_CLK_RATE(per6clk, 0x0, 15, PER6CLK, 133330000);
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static DEFINE_PRCMU_CLK_RATE(per7clk, 0x0, 16, PER7CLK, 100000000);
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static DEFINE_PRCMU_CLK(lcdclk, 0x0, 17, LCDCLK);
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static DEFINE_PRCMU_CLK(bmlclk, 0x0, 18, BMLCLK);
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static DEFINE_PRCMU_CLK(hsitxclk, 0x0, 19, HSITXCLK);
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@ -351,44 +332,28 @@ static DEFINE_PRCMU_CLK(uiccclk, 0x4, 1, UICCCLK); /* v1 */
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static DEFINE_PRCC_CLK(1, i2c4, 10, 9, &clk_i2cclk);
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static DEFINE_PRCC_CLK(1, gpio0, 9, -1, NULL);
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static DEFINE_PRCC_CLK(1, slimbus0, 8, 8, &clk_slimclk);
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static DEFINE_PRCC_CLK(1, spi3_ed, 7, 7, NULL);
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static DEFINE_PRCC_CLK(1, spi3_v1, 7, -1, NULL);
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static DEFINE_PRCC_CLK(1, spi3, 7, -1, NULL);
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static DEFINE_PRCC_CLK(1, i2c2, 6, 6, &clk_i2cclk);
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static DEFINE_PRCC_CLK(1, sdi0, 5, 5, &clk_sdmmcclk);
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static DEFINE_PRCC_CLK(1, msp1_ed, 4, 4, &clk_msp02clk);
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static DEFINE_PRCC_CLK(1, msp1_v1, 4, 4, &clk_msp1clk);
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static DEFINE_PRCC_CLK(1, msp1, 4, 4, &clk_msp1clk);
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static DEFINE_PRCC_CLK(1, msp0, 3, 3, &clk_msp02clk);
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static DEFINE_PRCC_CLK(1, i2c1, 2, 2, &clk_i2cclk);
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static DEFINE_PRCC_CLK(1, uart1, 1, 1, &clk_uartclk);
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static DEFINE_PRCC_CLK(1, uart0, 0, 0, &clk_uartclk);
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/* Peripheral Cluster #2 */
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static DEFINE_PRCC_CLK(2, gpio1_ed, 12, -1, NULL);
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static DEFINE_PRCC_CLK(2, ssitx_ed, 11, -1, NULL);
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static DEFINE_PRCC_CLK(2, ssirx_ed, 10, -1, NULL);
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static DEFINE_PRCC_CLK(2, spi0_ed, 9, -1, NULL);
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static DEFINE_PRCC_CLK(2, sdi3_ed, 8, 6, &clk_sdmmcclk);
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static DEFINE_PRCC_CLK(2, sdi1_ed, 7, 5, &clk_sdmmcclk);
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static DEFINE_PRCC_CLK(2, msp2_ed, 6, 4, &clk_msp02clk);
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static DEFINE_PRCC_CLK(2, sdi4_ed, 4, 2, &clk_sdmmcclk);
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static DEFINE_PRCC_CLK(2, pwl_ed, 3, 1, NULL);
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static DEFINE_PRCC_CLK(2, spi1_ed, 2, -1, NULL);
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static DEFINE_PRCC_CLK(2, spi2_ed, 1, -1, NULL);
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static DEFINE_PRCC_CLK(2, i2c3_ed, 0, 0, &clk_i2cclk);
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static DEFINE_PRCC_CLK(2, gpio1_v1, 11, -1, NULL);
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static DEFINE_PRCC_CLK(2, ssitx_v1, 10, 7, NULL);
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static DEFINE_PRCC_CLK(2, ssirx_v1, 9, 6, NULL);
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static DEFINE_PRCC_CLK(2, spi0_v1, 8, -1, NULL);
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static DEFINE_PRCC_CLK(2, sdi3_v1, 7, 5, &clk_sdmmcclk);
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static DEFINE_PRCC_CLK(2, sdi1_v1, 6, 4, &clk_sdmmcclk);
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static DEFINE_PRCC_CLK(2, msp2_v1, 5, 3, &clk_msp02clk);
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static DEFINE_PRCC_CLK(2, sdi4_v1, 4, 2, &clk_sdmmcclk);
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static DEFINE_PRCC_CLK(2, pwl_v1, 3, 1, NULL);
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static DEFINE_PRCC_CLK(2, spi1_v1, 2, -1, NULL);
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static DEFINE_PRCC_CLK(2, spi2_v1, 1, -1, NULL);
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static DEFINE_PRCC_CLK(2, i2c3_v1, 0, 0, &clk_i2cclk);
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static DEFINE_PRCC_CLK(2, gpio1, 11, -1, NULL);
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static DEFINE_PRCC_CLK(2, ssitx, 10, 7, NULL);
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static DEFINE_PRCC_CLK(2, ssirx, 9, 6, NULL);
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static DEFINE_PRCC_CLK(2, spi0, 8, -1, NULL);
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static DEFINE_PRCC_CLK(2, sdi3, 7, 5, &clk_sdmmcclk);
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static DEFINE_PRCC_CLK(2, sdi1, 6, 4, &clk_sdmmcclk);
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static DEFINE_PRCC_CLK(2, msp2, 5, 3, &clk_msp02clk);
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static DEFINE_PRCC_CLK(2, sdi4, 4, 2, &clk_sdmmcclk);
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static DEFINE_PRCC_CLK(2, pwl, 3, 1, NULL);
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static DEFINE_PRCC_CLK(2, spi1, 2, -1, NULL);
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static DEFINE_PRCC_CLK(2, spi2, 1, -1, NULL);
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static DEFINE_PRCC_CLK(2, i2c3, 0, 0, &clk_i2cclk);
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/* Peripheral Cluster #3 */
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static DEFINE_PRCC_CLK(3, gpio2, 8, -1, NULL);
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@ -397,49 +362,34 @@ static DEFINE_PRCC_CLK(3, uart2, 6, 6, &clk_uartclk);
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static DEFINE_PRCC_CLK(3, ske, 5, 5, &clk_32khz);
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static DEFINE_PRCC_CLK(3, sdi2, 4, 4, &clk_sdmmcclk);
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static DEFINE_PRCC_CLK(3, i2c0, 3, 3, &clk_i2cclk);
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static DEFINE_PRCC_CLK(3, ssp1_ed, 2, 2, &clk_i2cclk);
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static DEFINE_PRCC_CLK(3, ssp0_ed, 1, 1, &clk_i2cclk);
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static DEFINE_PRCC_CLK(3, ssp1_v1, 2, 2, &clk_sspclk);
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static DEFINE_PRCC_CLK(3, ssp0_v1, 1, 1, &clk_sspclk);
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static DEFINE_PRCC_CLK(3, ssp1, 2, 2, &clk_sspclk);
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static DEFINE_PRCC_CLK(3, ssp0, 1, 1, &clk_sspclk);
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static DEFINE_PRCC_CLK(3, fsmc, 0, -1, NULL);
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/* Peripheral Cluster #4 is in the always on domain */
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/* Peripheral Cluster #5 */
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static DEFINE_PRCC_CLK(5, gpio3, 1, -1, NULL);
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static DEFINE_PRCC_CLK(5, usb_ed, 0, 0, &clk_i2cclk);
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static DEFINE_PRCC_CLK(5, usb_v1, 0, 0, NULL);
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static DEFINE_PRCC_CLK(5, usb, 0, 0, NULL);
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/* Peripheral Cluster #6 */
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/* MTU ID in data */
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static DEFINE_PRCC_CLK_CUSTOM(6, mtu1_v1, 8, -1, NULL, clk_mtu_get_rate, 1);
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static DEFINE_PRCC_CLK_CUSTOM(6, mtu0_v1, 7, -1, NULL, clk_mtu_get_rate, 0);
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static DEFINE_PRCC_CLK(6, cfgreg_v1, 6, 6, NULL);
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static DEFINE_PRCC_CLK(6, dmc_ed, 6, 6, NULL);
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static DEFINE_PRCC_CLK_CUSTOM(6, mtu1, 8, -1, NULL, clk_mtu_get_rate, 1);
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static DEFINE_PRCC_CLK_CUSTOM(6, mtu0, 7, -1, NULL, clk_mtu_get_rate, 0);
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static DEFINE_PRCC_CLK(6, cfgreg, 6, 6, NULL);
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static DEFINE_PRCC_CLK(6, hash1, 5, -1, NULL);
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static DEFINE_PRCC_CLK(6, unipro_v1, 4, 1, &clk_uniproclk);
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static DEFINE_PRCC_CLK(6, cryp1_ed, 4, -1, NULL);
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static DEFINE_PRCC_CLK(6, unipro, 4, 1, &clk_uniproclk);
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static DEFINE_PRCC_CLK(6, pka, 3, -1, NULL);
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static DEFINE_PRCC_CLK(6, hash0, 2, -1, NULL);
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static DEFINE_PRCC_CLK(6, cryp0, 1, -1, NULL);
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static DEFINE_PRCC_CLK(6, rng_ed, 0, 0, &clk_i2cclk);
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static DEFINE_PRCC_CLK(6, rng_v1, 0, 0, &clk_rngclk);
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/* Peripheral Cluster #7 */
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static DEFINE_PRCC_CLK(7, tzpc0_ed, 4, -1, NULL);
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/* MTU ID in data */
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static DEFINE_PRCC_CLK_CUSTOM(7, mtu1_ed, 3, -1, NULL, clk_mtu_get_rate, 1);
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static DEFINE_PRCC_CLK_CUSTOM(7, mtu0_ed, 2, -1, NULL, clk_mtu_get_rate, 0);
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static DEFINE_PRCC_CLK(7, wdg_ed, 1, -1, NULL);
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static DEFINE_PRCC_CLK(7, cfgreg_ed, 0, -1, NULL);
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static DEFINE_PRCC_CLK(6, rng, 0, 0, &clk_rngclk);
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static struct clk clk_dummy_apb_pclk = {
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.name = "apb_pclk",
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};
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static struct clk_lookup u8500_common_clks[] = {
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static struct clk_lookup u8500_clks[] = {
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CLK(dummy_apb_pclk, NULL, "apb_pclk"),
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/* Peripheral Cluster #1 */
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@ -494,83 +444,41 @@ static struct clk_lookup u8500_common_clks[] = {
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CLK(dmaclk, "dma40.0", NULL),
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CLK(b2r2clk, "b2r2", NULL),
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CLK(tvclk, "tv", NULL),
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};
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static struct clk_lookup u8500_ed_clks[] = {
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/* Peripheral Cluster #1 */
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CLK(spi3_ed, "spi3", NULL),
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CLK(msp1_ed, "msp1", NULL),
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/* Peripheral Cluster #2 */
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CLK(gpio1_ed, "gpio.6", NULL),
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CLK(gpio1_ed, "gpio.7", NULL),
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CLK(ssitx_ed, "ssitx", NULL),
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CLK(ssirx_ed, "ssirx", NULL),
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CLK(spi0_ed, "spi0", NULL),
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CLK(sdi3_ed, "sdi3", NULL),
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CLK(sdi1_ed, "sdi1", NULL),
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CLK(msp2_ed, "msp2", NULL),
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CLK(sdi4_ed, "sdi4", NULL),
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CLK(pwl_ed, "pwl", NULL),
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CLK(spi1_ed, "spi1", NULL),
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CLK(spi2_ed, "spi2", NULL),
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CLK(i2c3_ed, "nmk-i2c.3", NULL),
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/* Peripheral Cluster #3 */
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CLK(ssp1_ed, "ssp1", NULL),
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CLK(ssp0_ed, "ssp0", NULL),
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/* Peripheral Cluster #5 */
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CLK(usb_ed, "musb-ux500.0", "usb"),
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/* Peripheral Cluster #6 */
|
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CLK(dmc_ed, "dmc", NULL),
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CLK(cryp1_ed, "cryp1", NULL),
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CLK(rng_ed, "rng", NULL),
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/* Peripheral Cluster #7 */
|
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CLK(tzpc0_ed, "tzpc0", NULL),
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CLK(mtu1_ed, "mtu1", NULL),
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CLK(mtu0_ed, "mtu0", NULL),
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CLK(wdg_ed, "wdg", NULL),
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CLK(cfgreg_ed, "cfgreg", NULL),
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};
|
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|
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static struct clk_lookup u8500_v1_clks[] = {
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/* Peripheral Cluster #1 */
|
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CLK(i2c4, "nmk-i2c.4", NULL),
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CLK(spi3_v1, "spi3", NULL),
|
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CLK(msp1_v1, "msp1", NULL),
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CLK(spi3, "spi3", NULL),
|
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CLK(msp1, "msp1", NULL),
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|
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/* Peripheral Cluster #2 */
|
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CLK(gpio1_v1, "gpio.6", NULL),
|
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CLK(gpio1_v1, "gpio.7", NULL),
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CLK(ssitx_v1, "ssitx", NULL),
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CLK(ssirx_v1, "ssirx", NULL),
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CLK(spi0_v1, "spi0", NULL),
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CLK(sdi3_v1, "sdi3", NULL),
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CLK(sdi1_v1, "sdi1", NULL),
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CLK(msp2_v1, "msp2", NULL),
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CLK(sdi4_v1, "sdi4", NULL),
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CLK(pwl_v1, "pwl", NULL),
|
||||
CLK(spi1_v1, "spi1", NULL),
|
||||
CLK(spi2_v1, "spi2", NULL),
|
||||
CLK(i2c3_v1, "nmk-i2c.3", NULL),
|
||||
CLK(gpio1, "gpio.6", NULL),
|
||||
CLK(gpio1, "gpio.7", NULL),
|
||||
CLK(ssitx, "ssitx", NULL),
|
||||
CLK(ssirx, "ssirx", NULL),
|
||||
CLK(spi0, "spi0", NULL),
|
||||
CLK(sdi3, "sdi3", NULL),
|
||||
CLK(sdi1, "sdi1", NULL),
|
||||
CLK(msp2, "msp2", NULL),
|
||||
CLK(sdi4, "sdi4", NULL),
|
||||
CLK(pwl, "pwl", NULL),
|
||||
CLK(spi1, "spi1", NULL),
|
||||
CLK(spi2, "spi2", NULL),
|
||||
CLK(i2c3, "nmk-i2c.3", NULL),
|
||||
|
||||
/* Peripheral Cluster #3 */
|
||||
CLK(ssp1_v1, "ssp1", NULL),
|
||||
CLK(ssp0_v1, "ssp0", NULL),
|
||||
CLK(ssp1, "ssp1", NULL),
|
||||
CLK(ssp0, "ssp0", NULL),
|
||||
|
||||
/* Peripheral Cluster #5 */
|
||||
CLK(usb_v1, "musb-ux500.0", "usb"),
|
||||
CLK(usb, "musb-ux500.0", "usb"),
|
||||
|
||||
/* Peripheral Cluster #6 */
|
||||
CLK(mtu1_v1, "mtu1", NULL),
|
||||
CLK(mtu0_v1, "mtu0", NULL),
|
||||
CLK(cfgreg_v1, "cfgreg", NULL),
|
||||
CLK(mtu1, "mtu1", NULL),
|
||||
CLK(mtu0, "mtu0", NULL),
|
||||
CLK(cfgreg, "cfgreg", NULL),
|
||||
CLK(hash1, "hash1", NULL),
|
||||
CLK(unipro_v1, "unipro", NULL),
|
||||
CLK(rng_v1, "rng", NULL),
|
||||
CLK(unipro, "unipro", NULL),
|
||||
CLK(rng, "rng", NULL),
|
||||
|
||||
/* PRCMU level clock gating */
|
||||
|
||||
|
|
@ -743,7 +651,7 @@ err_out:
|
|||
late_initcall(clk_debugfs_init);
|
||||
#endif /* defined(CONFIG_DEBUG_FS) */
|
||||
|
||||
unsigned long clk_smp_twd_rate = 400000000;
|
||||
unsigned long clk_smp_twd_rate = 500000000;
|
||||
|
||||
unsigned long clk_smp_twd_get_rate(struct clk *clk)
|
||||
{
|
||||
|
|
@ -769,7 +677,7 @@ static int clk_twd_cpufreq_transition(struct notifier_block *nb,
|
|||
|
||||
if (state == CPUFREQ_PRECHANGE) {
|
||||
/* Save frequency in simple Hz */
|
||||
clk_smp_twd_rate = f->new * 1000;
|
||||
clk_smp_twd_rate = (f->new * 1000) / 2;
|
||||
}
|
||||
|
||||
return NOTIFY_OK;
|
||||
|
|
@ -790,11 +698,7 @@ late_initcall(clk_init_smp_twd_cpufreq);
|
|||
|
||||
int __init clk_init(void)
|
||||
{
|
||||
if (cpu_is_u8500ed()) {
|
||||
clk_prcmu_ops.enable = clk_prcmu_ed_enable;
|
||||
clk_prcmu_ops.disable = clk_prcmu_ed_disable;
|
||||
clk_per6clk.rate = 100000000;
|
||||
} else if (cpu_is_u5500()) {
|
||||
if (cpu_is_u5500()) {
|
||||
/* Clock tree for U5500 not implemented yet */
|
||||
clk_prcc_ops.enable = clk_prcc_ops.disable = NULL;
|
||||
clk_prcmu_ops.enable = clk_prcmu_ops.disable = NULL;
|
||||
|
|
@ -802,20 +706,11 @@ int __init clk_init(void)
|
|||
clk_sdmmcclk.rate = 99900000;
|
||||
}
|
||||
|
||||
clkdev_add_table(u8500_common_clks, ARRAY_SIZE(u8500_common_clks));
|
||||
if (cpu_is_u8500ed())
|
||||
clkdev_add_table(u8500_ed_clks, ARRAY_SIZE(u8500_ed_clks));
|
||||
else
|
||||
clkdev_add_table(u8500_v1_clks, ARRAY_SIZE(u8500_v1_clks));
|
||||
|
||||
clkdev_add_table(u8500_clks, ARRAY_SIZE(u8500_clks));
|
||||
clkdev_add(&clk_smp_twd_lookup);
|
||||
|
||||
#ifdef CONFIG_DEBUG_FS
|
||||
clk_debugfs_add_table(u8500_common_clks, ARRAY_SIZE(u8500_common_clks));
|
||||
if (cpu_is_u8500ed())
|
||||
clk_debugfs_add_table(u8500_ed_clks, ARRAY_SIZE(u8500_ed_clks));
|
||||
else
|
||||
clk_debugfs_add_table(u8500_v1_clks, ARRAY_SIZE(u8500_v1_clks));
|
||||
clk_debugfs_add_table(u8500_clks, ARRAY_SIZE(u8500_clks));
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -47,26 +47,6 @@ static struct map_desc u5500_io_desc[] __initdata = {
|
|||
__IO_DEV_DESC(U5500_PRCMU_TCDM_BASE, SZ_4K),
|
||||
};
|
||||
|
||||
static struct resource db5500_pmu_resources[] = {
|
||||
[0] = {
|
||||
.start = IRQ_DB5500_PMU0,
|
||||
.end = IRQ_DB5500_PMU0,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
[1] = {
|
||||
.start = IRQ_DB5500_PMU1,
|
||||
.end = IRQ_DB5500_PMU1,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device db5500_pmu_device = {
|
||||
.name = "arm-pmu",
|
||||
.id = ARM_PMU_DEVICE_CPU,
|
||||
.num_resources = ARRAY_SIZE(db5500_pmu_resources),
|
||||
.resource = db5500_pmu_resources,
|
||||
};
|
||||
|
||||
static struct resource mbox0_resources[] = {
|
||||
{
|
||||
.name = "mbox_peer",
|
||||
|
|
@ -152,7 +132,6 @@ static struct platform_device mbox2_device = {
|
|||
};
|
||||
|
||||
static struct platform_device *db5500_platform_devs[] __initdata = {
|
||||
&db5500_pmu_device,
|
||||
&mbox0_device,
|
||||
&mbox1_device,
|
||||
&mbox2_device,
|
||||
|
|
@ -193,6 +172,25 @@ void __init u5500_map_io(void)
|
|||
_PRCMU_BASE = __io_address(U5500_PRCMU_BASE);
|
||||
}
|
||||
|
||||
static void __init db5500_pmu_init(void)
|
||||
{
|
||||
struct resource res[] = {
|
||||
[0] = {
|
||||
.start = IRQ_DB5500_PMU0,
|
||||
.end = IRQ_DB5500_PMU0,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
[1] = {
|
||||
.start = IRQ_DB5500_PMU1,
|
||||
.end = IRQ_DB5500_PMU1,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
platform_device_register_simple("arm-pmu", ARM_PMU_DEVICE_CPU,
|
||||
res, ARRAY_SIZE(res));
|
||||
}
|
||||
|
||||
static int usb_db5500_rx_dma_cfg[] = {
|
||||
DB5500_DMA_DEV4_USB_OTG_IEP_1_9,
|
||||
DB5500_DMA_DEV5_USB_OTG_IEP_2_10,
|
||||
|
|
@ -218,6 +216,7 @@ static int usb_db5500_tx_dma_cfg[] = {
|
|||
void __init u5500_init_devices(void)
|
||||
{
|
||||
db5500_add_gpios();
|
||||
db5500_pmu_init();
|
||||
db5500_dma_init();
|
||||
db5500_add_rtc();
|
||||
db5500_add_usb(usb_db5500_rx_dma_cfg, usb_db5500_tx_dma_cfg);
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (C) 2008-2009 ST-Ericsson
|
||||
* Copyright (C) 2008-2009 ST-Ericsson SA
|
||||
*
|
||||
* Author: Srinidhi KASAGAR <srinidhi.kasagar@stericsson.com>
|
||||
*
|
||||
|
|
@ -54,19 +54,6 @@ static struct map_desc u8500_io_desc[] __initdata = {
|
|||
__IO_DEV_DESC(U8500_GPIO1_BASE, SZ_4K),
|
||||
__IO_DEV_DESC(U8500_GPIO2_BASE, SZ_4K),
|
||||
__IO_DEV_DESC(U8500_GPIO3_BASE, SZ_4K),
|
||||
};
|
||||
|
||||
static struct map_desc u8500_ed_io_desc[] __initdata = {
|
||||
__IO_DEV_DESC(U8500_MTU0_BASE_ED, SZ_4K),
|
||||
__IO_DEV_DESC(U8500_CLKRST7_BASE_ED, SZ_8K),
|
||||
};
|
||||
|
||||
static struct map_desc u8500_v1_io_desc[] __initdata = {
|
||||
__IO_DEV_DESC(U8500_MTU0_BASE, SZ_4K),
|
||||
__IO_DEV_DESC(U8500_PRCMU_TCDM_BASE_V1, SZ_4K),
|
||||
};
|
||||
|
||||
static struct map_desc u8500_v2_io_desc[] __initdata = {
|
||||
__IO_DEV_DESC(U8500_PRCMU_TCDM_BASE, SZ_4K),
|
||||
};
|
||||
|
||||
|
|
@ -81,13 +68,6 @@ void __init u8500_map_io(void)
|
|||
|
||||
iotable_init(u8500_io_desc, ARRAY_SIZE(u8500_io_desc));
|
||||
|
||||
if (cpu_is_u8500ed())
|
||||
iotable_init(u8500_ed_io_desc, ARRAY_SIZE(u8500_ed_io_desc));
|
||||
else if (cpu_is_u8500v1())
|
||||
iotable_init(u8500_v1_io_desc, ARRAY_SIZE(u8500_v1_io_desc));
|
||||
else if (cpu_is_u8500v2())
|
||||
iotable_init(u8500_v2_io_desc, ARRAY_SIZE(u8500_v2_io_desc));
|
||||
|
||||
_PRCMU_BASE = __io_address(U8500_PRCMU_BASE);
|
||||
}
|
||||
|
||||
|
|
@ -156,12 +136,9 @@ static resource_size_t __initdata db8500_gpio_base[] = {
|
|||
static void __init db8500_add_gpios(void)
|
||||
{
|
||||
struct nmk_gpio_platform_data pdata = {
|
||||
/* No custom data yet */
|
||||
.supports_sleepmode = true,
|
||||
};
|
||||
|
||||
if (cpu_is_u8500v2())
|
||||
pdata.supports_sleepmode = true;
|
||||
|
||||
dbx500_add_gpios(ARRAY_AND_SIZE(db8500_gpio_base),
|
||||
IRQ_DB8500_GPIO0, &pdata);
|
||||
}
|
||||
|
|
@ -193,9 +170,6 @@ static int usb_db8500_tx_dma_cfg[] = {
|
|||
*/
|
||||
void __init u8500_init_devices(void)
|
||||
{
|
||||
if (cpu_is_u8500ed())
|
||||
dma40_u8500ed_fixup();
|
||||
|
||||
db8500_add_rtc();
|
||||
db8500_add_gpios();
|
||||
db8500_add_usb(usb_db8500_rx_dma_cfg, usb_db8500_tx_dma_cfg);
|
||||
|
|
|
|||
|
|
@ -166,16 +166,6 @@ struct platform_device u8500_dma40_device = {
|
|||
.resource = dma40_resources
|
||||
};
|
||||
|
||||
void dma40_u8500ed_fixup(void)
|
||||
{
|
||||
dma40_plat_data.memcpy = NULL;
|
||||
dma40_plat_data.memcpy_len = 0;
|
||||
dma40_resources[0].start = U8500_DMA_BASE_ED;
|
||||
dma40_resources[0].end = U8500_DMA_BASE_ED + SZ_4K - 1;
|
||||
dma40_resources[1].start = U8500_DMA_LCPA_BASE_ED;
|
||||
dma40_resources[1].end = U8500_DMA_LCPA_BASE_ED + 2 * SZ_1K - 1;
|
||||
}
|
||||
|
||||
struct resource keypad_resources[] = {
|
||||
[0] = {
|
||||
.start = U8500_SKE_BASE,
|
||||
|
|
|
|||
|
|
@ -65,6 +65,7 @@ static unsigned int partnumber(unsigned int asicid)
|
|||
* DB8500v1 0x411fc091 0x9001FFF4 0x008500A0
|
||||
* DB8500v1.1 0x411fc091 0x9001FFF4 0x008500A1
|
||||
* DB8500v2 0x412fc091 0x9001DBF4 0x008500B0
|
||||
* DB8520v2.2 0x412fc091 0x9001DBF4 0x008500B2
|
||||
* DB5500v1 0x412fc091 0x9001FFF4 0x005500A0
|
||||
*/
|
||||
|
||||
|
|
@ -80,9 +81,10 @@ void __init ux500_map_io(void)
|
|||
addr = 0x9001FFF4;
|
||||
break;
|
||||
|
||||
case 0x412fc091: /* DB8500v2 / DB5500v1 */
|
||||
case 0x412fc091: /* DB8520 / DB8500v2 / DB5500v1 */
|
||||
asicid = ux500_read_asicid(0x9001DBF4);
|
||||
if (partnumber(asicid) == 0x8500)
|
||||
if (partnumber(asicid) == 0x8500 ||
|
||||
partnumber(asicid) == 0x8520)
|
||||
/* DB8500v2 */
|
||||
break;
|
||||
|
||||
|
|
|
|||
|
|
@ -65,8 +65,11 @@
|
|||
#define U5500_PRCMU_TIMER_4_BASE (U5500_PER4_BASE + 0x07450)
|
||||
#define U5500_MSP1_BASE (U5500_PER4_BASE + 0x9000)
|
||||
#define U5500_GPIO2_BASE (U5500_PER4_BASE + 0xA000)
|
||||
#define U5500_MTIMER_BASE (U5500_PER4_BASE + 0xC000)
|
||||
#define U5500_CDETECT_BASE (U5500_PER4_BASE + 0xF000)
|
||||
#define U5500_PRCMU_TCDM_BASE (U5500_PER4_BASE + 0x18000)
|
||||
#define U5500_PRCMU_TCPM_BASE (U5500_PER4_BASE + 0x10000)
|
||||
#define U5500_TPIU_BASE (U5500_PER4_BASE + 0x50000)
|
||||
|
||||
#define U5500_SPI0_BASE (U5500_PER5_BASE + 0x0000)
|
||||
#define U5500_SPI1_BASE (U5500_PER5_BASE + 0x1000)
|
||||
|
|
@ -125,6 +128,7 @@
|
|||
#define U5500_ACCCON_BASE (0xBFFF1000)
|
||||
#define U5500_ACCCON_CPUVEC_RESET_ADDR_OFFSET (0x00000020)
|
||||
#define U5500_ACCCON_ACC_CPU_CTRL_OFFSET (0x000000BC)
|
||||
#define U5500_INTCON_MBOX1_INT_RESET_ADDR (0xBFFD31A4)
|
||||
|
||||
#define U5500_ESRAM_BASE 0x40000000
|
||||
#define U5500_ESRAM_DMA_LCPA_OFFSET 0x10000
|
||||
|
|
|
|||
|
|
@ -22,7 +22,9 @@
|
|||
#define U8500_ESRAM_DMA_LCPA_OFFSET 0x10000
|
||||
|
||||
#define U8500_DMA_LCPA_BASE (U8500_ESRAM_BANK0 + U8500_ESRAM_DMA_LCPA_OFFSET)
|
||||
#define U8500_DMA_LCPA_BASE_ED (U8500_ESRAM_BANK4 + 0x4000)
|
||||
|
||||
/* This address fulfills the 256k alignment requirement of the lcla base */
|
||||
#define U8500_DMA_LCLA_BASE U8500_ESRAM_BANK4
|
||||
|
||||
#define U8500_PER3_BASE 0x80000000
|
||||
#define U8500_STM_BASE 0x80100000
|
||||
|
|
@ -40,15 +42,14 @@
|
|||
#define U8500_ASIC_ID_BASE 0x9001D000
|
||||
|
||||
#define U8500_PER6_BASE 0xa03c0000
|
||||
#define U8500_PER7_BASE 0xa03d0000
|
||||
#define U8500_PER5_BASE 0xa03e0000
|
||||
#define U8500_PER7_BASE_ED 0xa03d0000
|
||||
|
||||
#define U8500_SVA_BASE 0xa0100000
|
||||
#define U8500_SIA_BASE 0xa0200000
|
||||
|
||||
#define U8500_SGA_BASE 0xa0300000
|
||||
#define U8500_MCDE_BASE 0xa0350000
|
||||
#define U8500_DMA_BASE_ED 0xa0362000
|
||||
#define U8500_DMA_BASE 0x801C0000 /* v1 */
|
||||
|
||||
#define U8500_SBAG_BASE 0xa0390000
|
||||
|
|
@ -66,13 +67,6 @@
|
|||
#define U8500_GPIO2_BASE (U8500_PER2_BASE + 0xE000)
|
||||
#define U8500_GPIO3_BASE (U8500_PER5_BASE + 0x1E000)
|
||||
|
||||
/* per7 base addresses */
|
||||
#define U8500_CR_BASE_ED (U8500_PER7_BASE_ED + 0x8000)
|
||||
#define U8500_MTU0_BASE_ED (U8500_PER7_BASE_ED + 0xa000)
|
||||
#define U8500_MTU1_BASE_ED (U8500_PER7_BASE_ED + 0xb000)
|
||||
#define U8500_TZPC0_BASE_ED (U8500_PER7_BASE_ED + 0xc000)
|
||||
#define U8500_CLKRST7_BASE_ED (U8500_PER7_BASE_ED + 0xf000)
|
||||
|
||||
#define U8500_UART0_BASE (U8500_PER1_BASE + 0x0000)
|
||||
#define U8500_UART1_BASE (U8500_PER1_BASE + 0x1000)
|
||||
|
||||
|
|
@ -102,12 +96,10 @@
|
|||
#define U8500_SCR_BASE (U8500_PER4_BASE + 0x05000)
|
||||
#define U8500_DMC_BASE (U8500_PER4_BASE + 0x06000)
|
||||
#define U8500_PRCMU_BASE (U8500_PER4_BASE + 0x07000)
|
||||
#define U8500_PRCMU_TIMER_3_BASE (U8500_PER4_BASE + 0x07338)
|
||||
#define U8500_PRCMU_TIMER_4_BASE (U8500_PER4_BASE + 0x07450)
|
||||
#define U8500_PRCMU_TCDM_BASE_V1 (U8500_PER4_BASE + 0x0f000)
|
||||
#define U8500_PRCMU_TCDM_BASE (U8500_PER4_BASE + 0x68000)
|
||||
#define U8500_PRCMU_TCPM_BASE (U8500_PER4_BASE + 0x60000)
|
||||
|
||||
#define U8500_PRCMU_TIMER_3_BASE (U8500_PER4_BASE + 0x07338)
|
||||
#define U8500_PRCMU_TIMER_4_BASE (U8500_PER4_BASE + 0x07450)
|
||||
|
||||
/* per3 base addresses */
|
||||
#define U8500_FSMC_BASE (U8500_PER3_BASE + 0x0000)
|
||||
|
|
|
|||
|
|
@ -18,6 +18,4 @@ extern struct amba_device ux500_pl031_device;
|
|||
extern struct platform_device u8500_dma40_device;
|
||||
extern struct platform_device ux500_ske_keypad_device;
|
||||
|
||||
void dma40_u8500ed_fixup(void);
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -10,20 +10,21 @@
|
|||
#ifndef __MACH_HARDWARE_H
|
||||
#define __MACH_HARDWARE_H
|
||||
|
||||
/* macros to get at IO space when running virtually
|
||||
/*
|
||||
* Macros to get at IO space when running virtually
|
||||
* We dont map all the peripherals, let ioremap do
|
||||
* this for us. We map only very basic peripherals here.
|
||||
*/
|
||||
#define U8500_IO_VIRTUAL 0xf0000000
|
||||
#define U8500_IO_PHYSICAL 0xa0000000
|
||||
|
||||
/* this macro is used in assembly, so no cast */
|
||||
/* This macro is used in assembly, so no cast */
|
||||
#define IO_ADDRESS(x) \
|
||||
(((x) & 0x0fffffff) + (((x) >> 4) & 0x0f000000) + U8500_IO_VIRTUAL)
|
||||
|
||||
/* typesafe io address */
|
||||
#define __io_address(n) __io(IO_ADDRESS(n))
|
||||
/* used by some plat-nomadik code */
|
||||
/* Used by some plat-nomadik code */
|
||||
#define io_p2v(n) __io_address(n)
|
||||
|
||||
#include <mach/db8500-regs.h>
|
||||
|
|
@ -36,6 +37,5 @@ extern void __iomem *_PRCMU_BASE;
|
|||
|
||||
#define ARRAY_AND_SIZE(x) (x), ARRAY_SIZE(x)
|
||||
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __MACH_HARDWARE_H */
|
||||
|
|
|
|||
|
|
@ -46,6 +46,30 @@ static inline bool __attribute_const__ cpu_is_u5500(void)
|
|||
return dbx500_partnumber() == 0x5500;
|
||||
}
|
||||
|
||||
/*
|
||||
* 5500 revisions
|
||||
*/
|
||||
|
||||
static inline bool __attribute_const__ cpu_is_u5500v1(void)
|
||||
{
|
||||
return cpu_is_u5500() && (dbx500_revision() & 0xf0) == 0xA0;
|
||||
}
|
||||
|
||||
static inline bool __attribute_const__ cpu_is_u5500v2(void)
|
||||
{
|
||||
return (dbx500_id.revision & 0xf0) == 0xB0;
|
||||
}
|
||||
|
||||
static inline bool __attribute_const__ cpu_is_u5500v20(void)
|
||||
{
|
||||
return cpu_is_u5500() && ((dbx500_revision() & 0xf0) == 0xB0);
|
||||
}
|
||||
|
||||
static inline bool __attribute_const__ cpu_is_u5500v21(void)
|
||||
{
|
||||
return cpu_is_u5500() && (dbx500_revision() == 0xB1);
|
||||
}
|
||||
|
||||
/*
|
||||
* 8500 revisions
|
||||
*/
|
||||
|
|
|
|||
Loading…
Reference in New Issue