gianfar: Cleanup/Fix gfar_probe and the hw init code
Factor out gfar_hw_init() to contain all the controller hw initialization steps for a better control of register writes, and to significantly simplify the tangled code from gfar_probe(). This results in code size and stack usage reduction (besides code readability). Fix memory leak on device removal, by freeing the rx_/tx_queue structures. Replace custom bit swapping function with a library one (bitrev8). Move allocation of rx_/tx_queue struct arrays before the group structure init, because in order to assign Rx/Tx queues to groups we need to have the queues first. This also allows earlier bail out of gfar_probe(), in case the memory allocation fails. The flow control checks for maccfg1 were removed from gfar_probe(), since flow control is disabled at probe time (priv->rx_/tx_pause_en are 0). Redundant initializations (by 0) also removed. Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Claudiu Manoil
David S. Miller
parent
c85fde8336
commit
208627883e
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@ -9,7 +9,7 @@
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* Maintainer: Kumar Gala
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* Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>
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*
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* Copyright 2002-2009, 2011 Freescale Semiconductor, Inc.
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* Copyright 2002-2009, 2011-2013 Freescale Semiconductor, Inc.
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* Copyright 2007 MontaVista Software, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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@ -511,7 +511,43 @@ void unlock_tx_qs(struct gfar_private *priv)
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spin_unlock(&priv->tx_queue[i]->txlock);
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}
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static void free_tx_pointers(struct gfar_private *priv)
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static int gfar_alloc_tx_queues(struct gfar_private *priv)
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{
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int i;
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for (i = 0; i < priv->num_tx_queues; i++) {
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priv->tx_queue[i] = kzalloc(sizeof(struct gfar_priv_tx_q),
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GFP_KERNEL);
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if (!priv->tx_queue[i])
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return -ENOMEM;
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priv->tx_queue[i]->tx_skbuff = NULL;
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priv->tx_queue[i]->qindex = i;
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priv->tx_queue[i]->dev = priv->ndev;
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spin_lock_init(&(priv->tx_queue[i]->txlock));
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}
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return 0;
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}
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static int gfar_alloc_rx_queues(struct gfar_private *priv)
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{
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int i;
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for (i = 0; i < priv->num_rx_queues; i++) {
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priv->rx_queue[i] = kzalloc(sizeof(struct gfar_priv_rx_q),
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GFP_KERNEL);
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if (!priv->rx_queue[i])
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return -ENOMEM;
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priv->rx_queue[i]->rx_skbuff = NULL;
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priv->rx_queue[i]->qindex = i;
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priv->rx_queue[i]->dev = priv->ndev;
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spin_lock_init(&(priv->rx_queue[i]->rxlock));
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}
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return 0;
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}
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static void gfar_free_tx_queues(struct gfar_private *priv)
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{
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int i;
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@ -519,7 +555,7 @@ static void free_tx_pointers(struct gfar_private *priv)
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kfree(priv->tx_queue[i]);
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}
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static void free_rx_pointers(struct gfar_private *priv)
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static void gfar_free_rx_queues(struct gfar_private *priv)
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{
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int i;
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@ -608,6 +644,30 @@ static int gfar_parse_group(struct device_node *np,
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grp->rx_bit_map = 0xFF;
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grp->tx_bit_map = 0xFF;
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}
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/* bit_map's MSB is q0 (from q0 to q7) but, for_each_set_bit parses
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* right to left, so we need to revert the 8 bits to get the q index
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*/
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grp->rx_bit_map = bitrev8(grp->rx_bit_map);
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grp->tx_bit_map = bitrev8(grp->tx_bit_map);
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/* Calculate RSTAT, TSTAT, RQUEUE and TQUEUE values,
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* also assign queues to groups
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*/
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for_each_set_bit(i, &grp->rx_bit_map, priv->num_rx_queues) {
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grp->num_rx_queues++;
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grp->rstat |= (RSTAT_CLEAR_RHALT >> i);
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priv->rqueue |= ((RQUEUE_EN0 | RQUEUE_EX0) >> i);
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priv->rx_queue[i]->grp = grp;
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}
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for_each_set_bit(i, &grp->tx_bit_map, priv->num_tx_queues) {
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grp->num_tx_queues++;
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grp->tstat |= (TSTAT_CLEAR_THALT >> i);
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priv->tqueue |= (TQUEUE_EN0 >> i);
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priv->tx_queue[i]->grp = grp;
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}
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priv->num_grps++;
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return 0;
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@ -664,7 +724,14 @@ static int gfar_of_init(struct platform_device *ofdev, struct net_device **pdev)
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priv->num_tx_queues = num_tx_qs;
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netif_set_real_num_rx_queues(dev, num_rx_qs);
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priv->num_rx_queues = num_rx_qs;
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priv->num_grps = 0x0;
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err = gfar_alloc_tx_queues(priv);
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if (err)
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goto tx_alloc_failed;
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err = gfar_alloc_rx_queues(priv);
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if (err)
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goto rx_alloc_failed;
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/* Init Rx queue filer rule set linked list */
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INIT_LIST_HEAD(&priv->rx_list.list);
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@ -691,38 +758,6 @@ static int gfar_of_init(struct platform_device *ofdev, struct net_device **pdev)
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goto err_grp_init;
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}
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for (i = 0; i < priv->num_tx_queues; i++)
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priv->tx_queue[i] = NULL;
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for (i = 0; i < priv->num_rx_queues; i++)
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priv->rx_queue[i] = NULL;
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for (i = 0; i < priv->num_tx_queues; i++) {
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priv->tx_queue[i] = kzalloc(sizeof(struct gfar_priv_tx_q),
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GFP_KERNEL);
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if (!priv->tx_queue[i]) {
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err = -ENOMEM;
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goto tx_alloc_failed;
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}
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priv->tx_queue[i]->tx_skbuff = NULL;
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priv->tx_queue[i]->qindex = i;
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priv->tx_queue[i]->dev = dev;
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spin_lock_init(&(priv->tx_queue[i]->txlock));
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}
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for (i = 0; i < priv->num_rx_queues; i++) {
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priv->rx_queue[i] = kzalloc(sizeof(struct gfar_priv_rx_q),
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GFP_KERNEL);
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if (!priv->rx_queue[i]) {
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err = -ENOMEM;
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goto rx_alloc_failed;
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}
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priv->rx_queue[i]->rx_skbuff = NULL;
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priv->rx_queue[i]->qindex = i;
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priv->rx_queue[i]->dev = dev;
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spin_lock_init(&(priv->rx_queue[i]->rxlock));
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}
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stash = of_get_property(np, "bd-stash", NULL);
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if (stash) {
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@ -784,12 +819,12 @@ static int gfar_of_init(struct platform_device *ofdev, struct net_device **pdev)
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return 0;
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rx_alloc_failed:
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free_rx_pointers(priv);
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tx_alloc_failed:
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free_tx_pointers(priv);
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err_grp_init:
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unmap_group_regs(priv);
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rx_alloc_failed:
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gfar_free_rx_queues(priv);
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tx_alloc_failed:
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gfar_free_tx_queues(priv);
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free_gfar_dev(priv);
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return err;
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}
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@ -875,19 +910,6 @@ static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
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return phy_mii_ioctl(priv->phydev, rq, cmd);
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}
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static unsigned int reverse_bitmap(unsigned int bit_map, unsigned int max_qs)
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{
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unsigned int new_bit_map = 0x0;
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int mask = 0x1 << (max_qs - 1), i;
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for (i = 0; i < max_qs; i++) {
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if (bit_map & mask)
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new_bit_map = new_bit_map + (1 << i);
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mask = mask >> 0x1;
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}
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return new_bit_map;
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}
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static u32 cluster_entry_per_class(struct gfar_private *priv, u32 rqfar,
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u32 class)
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{
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@ -1005,43 +1027,10 @@ static void gfar_detect_errata(struct gfar_private *priv)
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priv->errata);
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}
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/* Set up the ethernet device structure, private data,
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* and anything else we need before we start
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*/
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static int gfar_probe(struct platform_device *ofdev)
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static void gfar_hw_init(struct gfar_private *priv)
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{
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struct gfar __iomem *regs = priv->gfargrp[0].regs;
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u32 tempval;
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struct net_device *dev = NULL;
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struct gfar_private *priv = NULL;
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struct gfar __iomem *regs = NULL;
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int err = 0, i, grp_idx = 0;
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u32 rstat = 0, tstat = 0, rqueue = 0, tqueue = 0;
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u32 isrg = 0;
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u32 __iomem *baddr;
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err = gfar_of_init(ofdev, &dev);
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if (err)
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return err;
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priv = netdev_priv(dev);
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priv->ndev = dev;
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priv->ofdev = ofdev;
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priv->dev = &ofdev->dev;
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SET_NETDEV_DEV(dev, &ofdev->dev);
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spin_lock_init(&priv->bflock);
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INIT_WORK(&priv->reset_task, gfar_reset_task);
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platform_set_drvdata(ofdev, priv);
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regs = priv->gfargrp[0].regs;
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gfar_detect_errata(priv);
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/* Stop the DMA engine now, in case it was running before
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* (The firmware could have used it, and left it running).
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*/
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gfar_halt(dev);
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/* Reset MAC layer */
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gfar_write(®s->maccfg1, MACCFG1_SOFT_RESET);
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@ -1049,15 +1038,10 @@ static int gfar_probe(struct platform_device *ofdev)
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/* We need to delay at least 3 TX clocks */
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udelay(2);
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tempval = 0;
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if (!priv->pause_aneg_en && priv->tx_pause_en)
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tempval |= MACCFG1_TX_FLOW;
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if (!priv->pause_aneg_en && priv->rx_pause_en)
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tempval |= MACCFG1_RX_FLOW;
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/* the soft reset bit is not self-resetting, so we need to
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* clear it before resuming normal operation
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*/
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gfar_write(®s->maccfg1, tempval);
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gfar_write(®s->maccfg1, 0);
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/* Initialize MACCFG2. */
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tempval = MACCFG2_INIT_SETTINGS;
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@ -1068,36 +1052,18 @@ static int gfar_probe(struct platform_device *ofdev)
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/* Initialize ECNTRL */
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gfar_write(®s->ecntrl, ECNTRL_INIT_SETTINGS);
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/* Set the dev->base_addr to the gfar reg region */
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dev->base_addr = (unsigned long) regs;
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/* Program the interrupt steering regs, only for MG devices */
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if (priv->num_grps > 1)
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gfar_write_isrg(priv);
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/* Fill in the dev structure */
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dev->watchdog_timeo = TX_TIMEOUT;
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dev->mtu = 1500;
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dev->netdev_ops = &gfar_netdev_ops;
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dev->ethtool_ops = &gfar_ethtool_ops;
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/* Enable all Rx/Tx queues after MAC reset */
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gfar_write(®s->rqueue, priv->rqueue);
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gfar_write(®s->tqueue, priv->tqueue);
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}
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/* Register for napi ...We are registering NAPI for each grp */
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if (priv->mode == SQ_SG_MODE)
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netif_napi_add(dev, &priv->gfargrp[0].napi, gfar_poll_sq,
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GFAR_DEV_WEIGHT);
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else
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for (i = 0; i < priv->num_grps; i++)
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netif_napi_add(dev, &priv->gfargrp[i].napi, gfar_poll,
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GFAR_DEV_WEIGHT);
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if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
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dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG |
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NETIF_F_RXCSUM;
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dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG |
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NETIF_F_RXCSUM | NETIF_F_HIGHDMA;
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}
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if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN) {
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dev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX |
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NETIF_F_HW_VLAN_CTAG_RX;
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dev->features |= NETIF_F_HW_VLAN_CTAG_RX;
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}
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static void __init gfar_init_addr_hash_table(struct gfar_private *priv)
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{
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struct gfar __iomem *regs = priv->gfargrp[0].regs;
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if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
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priv->extended_hash = 1;
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@ -1133,6 +1099,74 @@ static int gfar_probe(struct platform_device *ofdev)
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priv->hash_regs[6] = ®s->gaddr6;
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priv->hash_regs[7] = ®s->gaddr7;
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}
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}
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/* Set up the ethernet device structure, private data,
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* and anything else we need before we start
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*/
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static int gfar_probe(struct platform_device *ofdev)
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{
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struct net_device *dev = NULL;
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struct gfar_private *priv = NULL;
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int err = 0, i;
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err = gfar_of_init(ofdev, &dev);
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if (err)
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return err;
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priv = netdev_priv(dev);
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priv->ndev = dev;
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priv->ofdev = ofdev;
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priv->dev = &ofdev->dev;
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SET_NETDEV_DEV(dev, &ofdev->dev);
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spin_lock_init(&priv->bflock);
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INIT_WORK(&priv->reset_task, gfar_reset_task);
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platform_set_drvdata(ofdev, priv);
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gfar_detect_errata(priv);
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/* Stop the DMA engine now, in case it was running before
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* (The firmware could have used it, and left it running).
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*/
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gfar_halt(dev);
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gfar_hw_init(priv);
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/* Set the dev->base_addr to the gfar reg region */
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dev->base_addr = (unsigned long) priv->gfargrp[0].regs;
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/* Fill in the dev structure */
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dev->watchdog_timeo = TX_TIMEOUT;
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dev->mtu = 1500;
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dev->netdev_ops = &gfar_netdev_ops;
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dev->ethtool_ops = &gfar_ethtool_ops;
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/* Register for napi ...We are registering NAPI for each grp */
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if (priv->mode == SQ_SG_MODE)
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netif_napi_add(dev, &priv->gfargrp[0].napi, gfar_poll_sq,
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GFAR_DEV_WEIGHT);
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else
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for (i = 0; i < priv->num_grps; i++)
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netif_napi_add(dev, &priv->gfargrp[i].napi, gfar_poll,
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GFAR_DEV_WEIGHT);
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if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
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dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG |
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NETIF_F_RXCSUM;
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dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG |
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NETIF_F_RXCSUM | NETIF_F_HIGHDMA;
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}
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if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN) {
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dev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX |
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NETIF_F_HW_VLAN_CTAG_RX;
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dev->features |= NETIF_F_HW_VLAN_CTAG_RX;
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}
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gfar_init_addr_hash_table(priv);
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if (priv->device_flags & FSL_GIANFAR_DEV_HAS_PADDING)
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priv->padding = DEFAULT_PADDING;
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@ -1143,59 +1177,6 @@ static int gfar_probe(struct platform_device *ofdev)
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priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)
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dev->needed_headroom = GMAC_FCB_LEN;
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/* Program the isrg regs only if number of grps > 1 */
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if (priv->num_grps > 1) {
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baddr = ®s->isrg0;
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for (i = 0; i < priv->num_grps; i++) {
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isrg |= (priv->gfargrp[i].rx_bit_map << ISRG_SHIFT_RX);
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isrg |= (priv->gfargrp[i].tx_bit_map << ISRG_SHIFT_TX);
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gfar_write(baddr, isrg);
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baddr++;
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isrg = 0x0;
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}
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}
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/* Need to reverse the bit maps as bit_map's MSB is q0
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* but, for_each_set_bit parses from right to left, which
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* basically reverses the queue numbers
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*/
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for (i = 0; i< priv->num_grps; i++) {
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priv->gfargrp[i].tx_bit_map =
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reverse_bitmap(priv->gfargrp[i].tx_bit_map, MAX_TX_QS);
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priv->gfargrp[i].rx_bit_map =
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reverse_bitmap(priv->gfargrp[i].rx_bit_map, MAX_RX_QS);
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}
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/* Calculate RSTAT, TSTAT, RQUEUE and TQUEUE values,
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* also assign queues to groups
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*/
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for (grp_idx = 0; grp_idx < priv->num_grps; grp_idx++) {
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priv->gfargrp[grp_idx].num_rx_queues = 0x0;
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for_each_set_bit(i, &priv->gfargrp[grp_idx].rx_bit_map,
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priv->num_rx_queues) {
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priv->gfargrp[grp_idx].num_rx_queues++;
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priv->rx_queue[i]->grp = &priv->gfargrp[grp_idx];
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rstat = rstat | (RSTAT_CLEAR_RHALT >> i);
|
||||
rqueue = rqueue | ((RQUEUE_EN0 | RQUEUE_EX0) >> i);
|
||||
}
|
||||
priv->gfargrp[grp_idx].num_tx_queues = 0x0;
|
||||
|
||||
for_each_set_bit(i, &priv->gfargrp[grp_idx].tx_bit_map,
|
||||
priv->num_tx_queues) {
|
||||
priv->gfargrp[grp_idx].num_tx_queues++;
|
||||
priv->tx_queue[i]->grp = &priv->gfargrp[grp_idx];
|
||||
tstat = tstat | (TSTAT_CLEAR_THALT >> i);
|
||||
tqueue = tqueue | (TQUEUE_EN0 >> i);
|
||||
}
|
||||
priv->gfargrp[grp_idx].rstat = rstat;
|
||||
priv->gfargrp[grp_idx].tstat = tstat;
|
||||
rstat = tstat =0;
|
||||
}
|
||||
|
||||
gfar_write(®s->rqueue, rqueue);
|
||||
gfar_write(®s->tqueue, tqueue);
|
||||
|
||||
priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE;
|
||||
|
||||
/* Initializing some of the rx/tx queue level parameters */
|
||||
|
|
@ -1272,8 +1253,8 @@ static int gfar_probe(struct platform_device *ofdev)
|
|||
|
||||
register_fail:
|
||||
unmap_group_regs(priv);
|
||||
free_tx_pointers(priv);
|
||||
free_rx_pointers(priv);
|
||||
gfar_free_rx_queues(priv);
|
||||
gfar_free_tx_queues(priv);
|
||||
if (priv->phy_node)
|
||||
of_node_put(priv->phy_node);
|
||||
if (priv->tbi_node)
|
||||
|
|
@ -1293,6 +1274,8 @@ static int gfar_remove(struct platform_device *ofdev)
|
|||
|
||||
unregister_netdev(priv->ndev);
|
||||
unmap_group_regs(priv);
|
||||
gfar_free_rx_queues(priv);
|
||||
gfar_free_tx_queues(priv);
|
||||
free_gfar_dev(priv);
|
||||
|
||||
return 0;
|
||||
|
|
|
|||
|
|
@ -9,7 +9,7 @@
|
|||
* Maintainer: Kumar Gala
|
||||
* Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>
|
||||
*
|
||||
* Copyright 2002-2009, 2011 Freescale Semiconductor, Inc.
|
||||
* Copyright 2002-2009, 2011-2013 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
|
|
@ -892,8 +892,8 @@ struct gfar {
|
|||
#define DEFAULT_MAPPING 0xFF
|
||||
#endif
|
||||
|
||||
#define ISRG_SHIFT_TX 0x10
|
||||
#define ISRG_SHIFT_RX 0x18
|
||||
#define ISRG_RR0 0x80000000
|
||||
#define ISRG_TR0 0x00800000
|
||||
|
||||
/* The same driver can operate in two modes */
|
||||
/* SQ_SG_MODE: Single Queue Single Group Mode
|
||||
|
|
@ -1113,6 +1113,9 @@ struct gfar_private {
|
|||
unsigned int total_tx_ring_size;
|
||||
unsigned int total_rx_ring_size;
|
||||
|
||||
u32 rqueue;
|
||||
u32 tqueue;
|
||||
|
||||
/* RX per device parameters */
|
||||
unsigned int rx_stash_size;
|
||||
unsigned int rx_stash_index;
|
||||
|
|
@ -1176,6 +1179,31 @@ static inline void gfar_read_filer(struct gfar_private *priv,
|
|||
*fpr = gfar_read(®s->rqfpr);
|
||||
}
|
||||
|
||||
static inline void gfar_write_isrg(struct gfar_private *priv)
|
||||
{
|
||||
struct gfar __iomem *regs = priv->gfargrp[0].regs;
|
||||
u32 __iomem *baddr = ®s->isrg0;
|
||||
u32 isrg = 0;
|
||||
int grp_idx, i;
|
||||
|
||||
for (grp_idx = 0; grp_idx < priv->num_grps; grp_idx++) {
|
||||
struct gfar_priv_grp *grp = &priv->gfargrp[grp_idx];
|
||||
|
||||
for_each_set_bit(i, &grp->rx_bit_map, priv->num_rx_queues) {
|
||||
isrg |= (ISRG_RR0 >> i);
|
||||
}
|
||||
|
||||
for_each_set_bit(i, &grp->tx_bit_map, priv->num_tx_queues) {
|
||||
isrg |= (ISRG_TR0 >> i);
|
||||
}
|
||||
|
||||
gfar_write(baddr, isrg);
|
||||
|
||||
baddr++;
|
||||
isrg = 0;
|
||||
}
|
||||
}
|
||||
|
||||
void lock_rx_qs(struct gfar_private *priv);
|
||||
void lock_tx_qs(struct gfar_private *priv);
|
||||
void unlock_rx_qs(struct gfar_private *priv);
|
||||
|
|
|
|||
Loading…
Reference in New Issue