drm/radeon/kms: Convert R300 to new init path
Also cleanup register specific to R300. Signed-off-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
Jerome Glisse
Dave Airlie
parent
ca6ffc64cb
commit
207bf9e90c
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@ -34,42 +34,15 @@
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#include "r100_track.h"
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#include "r300d.h"
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#include "rv350d.h"
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#include "r300_reg_safe.h"
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/* r300,r350,rv350,rv370,rv380 depends on : */
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void r100_hdp_reset(struct radeon_device *rdev);
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int r100_cp_reset(struct radeon_device *rdev);
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int r100_rb2d_reset(struct radeon_device *rdev);
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int r100_cp_init(struct radeon_device *rdev, unsigned ring_size);
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int r100_pci_gart_enable(struct radeon_device *rdev);
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void r100_mc_setup(struct radeon_device *rdev);
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void r100_mc_disable_clients(struct radeon_device *rdev);
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int r100_gui_wait_for_idle(struct radeon_device *rdev);
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int r100_cs_packet_parse(struct radeon_cs_parser *p,
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struct radeon_cs_packet *pkt,
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unsigned idx);
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int r100_cs_packet_parse_vline(struct radeon_cs_parser *p);
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int r100_cs_parse_packet0(struct radeon_cs_parser *p,
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struct radeon_cs_packet *pkt,
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const unsigned *auth, unsigned n,
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radeon_packet0_check_t check);
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int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
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struct radeon_cs_packet *pkt,
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struct radeon_object *robj);
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/* This files gather functions specifics to:
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* r300,r350,rv350,rv370,rv380
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*
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* Some of these functions might be used by newer ASICs.
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*/
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void r300_gpu_init(struct radeon_device *rdev);
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int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev);
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/* This files gather functions specifics to: r300,r350,rv350,rv370,rv380 */
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/*
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* rv370,rv380 PCIE GART
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*/
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static int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev);
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void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev)
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{
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uint32_t tmp;
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@ -182,59 +155,6 @@ void rv370_pcie_gart_fini(struct radeon_device *rdev)
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radeon_gart_fini(rdev);
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}
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/*
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* MC
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*/
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int r300_mc_init(struct radeon_device *rdev)
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{
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int r;
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if (r100_debugfs_rbbm_init(rdev)) {
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DRM_ERROR("Failed to register debugfs file for RBBM !\n");
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}
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r300_gpu_init(rdev);
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r100_pci_gart_disable(rdev);
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if (rdev->flags & RADEON_IS_PCIE) {
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rv370_pcie_gart_disable(rdev);
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}
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/* Setup GPU memory space */
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rdev->mc.vram_location = 0xFFFFFFFFUL;
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rdev->mc.gtt_location = 0xFFFFFFFFUL;
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if (rdev->flags & RADEON_IS_AGP) {
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r = radeon_agp_init(rdev);
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if (r) {
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printk(KERN_WARNING "[drm] Disabling AGP\n");
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rdev->flags &= ~RADEON_IS_AGP;
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rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
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} else {
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rdev->mc.gtt_location = rdev->mc.agp_base;
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}
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}
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r = radeon_mc_setup(rdev);
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if (r) {
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return r;
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}
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/* Program GPU memory space */
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r100_mc_disable_clients(rdev);
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if (r300_mc_wait_for_idle(rdev)) {
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printk(KERN_WARNING "Failed to wait MC idle while "
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"programming pipes. Bad things might happen.\n");
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}
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r100_mc_setup(rdev);
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return 0;
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}
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void r300_mc_fini(struct radeon_device *rdev)
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{
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}
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/*
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* Fence emission
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*/
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void r300_fence_ring_emit(struct radeon_device *rdev,
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struct radeon_fence *fence)
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{
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@ -260,10 +180,6 @@ void r300_fence_ring_emit(struct radeon_device *rdev,
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radeon_ring_write(rdev, RADEON_SW_INT_FIRE);
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}
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/*
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* Global GPU functions
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*/
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int r300_copy_dma(struct radeon_device *rdev,
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uint64_t src_offset,
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uint64_t dst_offset,
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@ -582,11 +498,6 @@ void r300_vram_info(struct radeon_device *rdev)
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r100_vram_init_sizes(rdev);
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}
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/*
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* PCIE Lanes
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*/
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void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes)
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{
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uint32_t link_width_cntl, mask;
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@ -646,10 +557,6 @@ void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes)
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}
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/*
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* Debugfs info
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*/
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#if defined(CONFIG_DEBUG_FS)
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static int rv370_debugfs_pcie_gart_info(struct seq_file *m, void *data)
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{
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@ -680,7 +587,7 @@ static struct drm_info_list rv370_pcie_gart_info_list[] = {
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};
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#endif
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int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev)
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static int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev)
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{
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#if defined(CONFIG_DEBUG_FS)
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return radeon_debugfs_add_files(rdev, rv370_pcie_gart_info_list, 1);
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@ -689,10 +596,6 @@ int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev)
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#endif
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}
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/*
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* CS functions
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*/
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static int r300_packet0_check(struct radeon_cs_parser *p,
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struct radeon_cs_packet *pkt,
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unsigned idx, unsigned reg)
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@ -1226,12 +1129,6 @@ void r300_set_reg_safe(struct radeon_device *rdev)
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rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r300_reg_safe_bm);
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}
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int r300_init(struct radeon_device *rdev)
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{
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r300_set_reg_safe(rdev);
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return 0;
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}
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void r300_mc_program(struct radeon_device *rdev)
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{
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struct r100_mc_save save;
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@ -1279,3 +1176,185 @@ void r300_clock_startup(struct radeon_device *rdev)
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tmp |= S_00000D_FORCE_VAP(1);
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WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
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}
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static int r300_startup(struct radeon_device *rdev)
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{
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int r;
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r300_mc_program(rdev);
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/* Resume clock */
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r300_clock_startup(rdev);
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/* Initialize GPU configuration (# pipes, ...) */
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r300_gpu_init(rdev);
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/* Initialize GART (initialize after TTM so we can allocate
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* memory through TTM but finalize after TTM) */
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if (rdev->flags & RADEON_IS_PCIE) {
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r = rv370_pcie_gart_enable(rdev);
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if (r)
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return r;
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}
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if (rdev->flags & RADEON_IS_PCI) {
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r = r100_pci_gart_enable(rdev);
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if (r)
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return r;
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}
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/* Enable IRQ */
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rdev->irq.sw_int = true;
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r100_irq_set(rdev);
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/* 1M ring buffer */
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r = r100_cp_init(rdev, 1024 * 1024);
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if (r) {
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dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
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return r;
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}
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r = r100_wb_init(rdev);
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if (r)
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dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
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r = r100_ib_init(rdev);
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if (r) {
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dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
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return r;
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}
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return 0;
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}
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int r300_resume(struct radeon_device *rdev)
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{
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/* Make sur GART are not working */
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if (rdev->flags & RADEON_IS_PCIE)
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rv370_pcie_gart_disable(rdev);
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if (rdev->flags & RADEON_IS_PCI)
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r100_pci_gart_disable(rdev);
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/* Resume clock before doing reset */
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r300_clock_startup(rdev);
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/* Reset gpu before posting otherwise ATOM will enter infinite loop */
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if (radeon_gpu_reset(rdev)) {
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dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
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RREG32(R_000E40_RBBM_STATUS),
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RREG32(R_0007C0_CP_STAT));
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}
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/* post */
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radeon_combios_asic_init(rdev->ddev);
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/* Resume clock after posting */
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r300_clock_startup(rdev);
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return r300_startup(rdev);
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}
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int r300_suspend(struct radeon_device *rdev)
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{
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r100_cp_disable(rdev);
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r100_wb_disable(rdev);
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r100_irq_disable(rdev);
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if (rdev->flags & RADEON_IS_PCIE)
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rv370_pcie_gart_disable(rdev);
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if (rdev->flags & RADEON_IS_PCI)
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r100_pci_gart_disable(rdev);
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return 0;
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}
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void r300_fini(struct radeon_device *rdev)
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{
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r300_suspend(rdev);
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r100_cp_fini(rdev);
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r100_wb_fini(rdev);
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r100_ib_fini(rdev);
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radeon_gem_fini(rdev);
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if (rdev->flags & RADEON_IS_PCIE)
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rv370_pcie_gart_fini(rdev);
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if (rdev->flags & RADEON_IS_PCI)
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r100_pci_gart_fini(rdev);
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radeon_irq_kms_fini(rdev);
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radeon_fence_driver_fini(rdev);
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radeon_object_fini(rdev);
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radeon_atombios_fini(rdev);
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kfree(rdev->bios);
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rdev->bios = NULL;
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}
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int r300_init(struct radeon_device *rdev)
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{
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int r;
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rdev->new_init_path = true;
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/* Disable VGA */
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r100_vga_render_disable(rdev);
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/* Initialize scratch registers */
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radeon_scratch_init(rdev);
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/* Initialize surface registers */
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radeon_surface_init(rdev);
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/* TODO: disable VGA need to use VGA request */
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/* BIOS*/
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if (!radeon_get_bios(rdev)) {
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if (ASIC_IS_AVIVO(rdev))
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return -EINVAL;
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}
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if (rdev->is_atom_bios) {
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dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
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return -EINVAL;
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} else {
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r = radeon_combios_init(rdev);
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if (r)
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return r;
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}
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/* Reset gpu before posting otherwise ATOM will enter infinite loop */
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if (radeon_gpu_reset(rdev)) {
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dev_warn(rdev->dev,
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"GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
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RREG32(R_000E40_RBBM_STATUS),
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RREG32(R_0007C0_CP_STAT));
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}
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/* check if cards are posted or not */
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if (!radeon_card_posted(rdev) && rdev->bios) {
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DRM_INFO("GPU not posted. posting now...\n");
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radeon_combios_asic_init(rdev->ddev);
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}
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/* Set asic errata */
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r300_errata(rdev);
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/* Initialize clocks */
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radeon_get_clock_info(rdev->ddev);
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/* Get vram informations */
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r300_vram_info(rdev);
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/* Initialize memory controller (also test AGP) */
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r = r420_mc_init(rdev);
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if (r)
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return r;
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/* Fence driver */
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r = radeon_fence_driver_init(rdev);
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if (r)
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return r;
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r = radeon_irq_kms_init(rdev);
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if (r)
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return r;
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/* Memory manager */
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r = radeon_object_init(rdev);
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if (r)
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return r;
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if (rdev->flags & RADEON_IS_PCIE) {
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r = rv370_pcie_gart_init(rdev);
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if (r)
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return r;
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}
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if (rdev->flags & RADEON_IS_PCI) {
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r = r100_pci_gart_init(rdev);
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if (r)
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return r;
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}
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r300_set_reg_safe(rdev);
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rdev->accel_working = true;
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r = r300_startup(rdev);
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if (r) {
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/* Somethings want wront with the accel init stop accel */
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dev_err(rdev->dev, "Disabling GPU acceleration\n");
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r300_suspend(rdev);
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r100_cp_fini(rdev);
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r100_wb_fini(rdev);
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r100_ib_fini(rdev);
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if (rdev->flags & RADEON_IS_PCIE)
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rv370_pcie_gart_fini(rdev);
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if (rdev->flags & RADEON_IS_PCI)
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r100_pci_gart_fini(rdev);
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radeon_irq_kms_fini(rdev);
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rdev->accel_working = false;
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}
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return 0;
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}
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@ -96,6 +96,119 @@
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#define S_000170_AGP_BASE_ADDR(x) (((x) & 0xFFFFFFFF) << 0)
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#define G_000170_AGP_BASE_ADDR(x) (((x) >> 0) & 0xFFFFFFFF)
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#define C_000170_AGP_BASE_ADDR 0x00000000
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#define R_0007C0_CP_STAT 0x0007C0
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#define S_0007C0_MRU_BUSY(x) (((x) & 0x1) << 0)
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#define G_0007C0_MRU_BUSY(x) (((x) >> 0) & 0x1)
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#define C_0007C0_MRU_BUSY 0xFFFFFFFE
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#define S_0007C0_MWU_BUSY(x) (((x) & 0x1) << 1)
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#define G_0007C0_MWU_BUSY(x) (((x) >> 1) & 0x1)
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#define C_0007C0_MWU_BUSY 0xFFFFFFFD
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#define S_0007C0_RSIU_BUSY(x) (((x) & 0x1) << 2)
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#define G_0007C0_RSIU_BUSY(x) (((x) >> 2) & 0x1)
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#define C_0007C0_RSIU_BUSY 0xFFFFFFFB
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#define S_0007C0_RCIU_BUSY(x) (((x) & 0x1) << 3)
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#define G_0007C0_RCIU_BUSY(x) (((x) >> 3) & 0x1)
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#define C_0007C0_RCIU_BUSY 0xFFFFFFF7
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#define S_0007C0_CSF_PRIMARY_BUSY(x) (((x) & 0x1) << 9)
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#define G_0007C0_CSF_PRIMARY_BUSY(x) (((x) >> 9) & 0x1)
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#define C_0007C0_CSF_PRIMARY_BUSY 0xFFFFFDFF
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#define S_0007C0_CSF_INDIRECT_BUSY(x) (((x) & 0x1) << 10)
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#define G_0007C0_CSF_INDIRECT_BUSY(x) (((x) >> 10) & 0x1)
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#define C_0007C0_CSF_INDIRECT_BUSY 0xFFFFFBFF
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#define S_0007C0_CSQ_PRIMARY_BUSY(x) (((x) & 0x1) << 11)
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#define G_0007C0_CSQ_PRIMARY_BUSY(x) (((x) >> 11) & 0x1)
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#define C_0007C0_CSQ_PRIMARY_BUSY 0xFFFFF7FF
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#define S_0007C0_CSQ_INDIRECT_BUSY(x) (((x) & 0x1) << 12)
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#define G_0007C0_CSQ_INDIRECT_BUSY(x) (((x) >> 12) & 0x1)
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#define C_0007C0_CSQ_INDIRECT_BUSY 0xFFFFEFFF
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#define S_0007C0_CSI_BUSY(x) (((x) & 0x1) << 13)
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#define G_0007C0_CSI_BUSY(x) (((x) >> 13) & 0x1)
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#define C_0007C0_CSI_BUSY 0xFFFFDFFF
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#define S_0007C0_CSF_INDIRECT2_BUSY(x) (((x) & 0x1) << 14)
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#define G_0007C0_CSF_INDIRECT2_BUSY(x) (((x) >> 14) & 0x1)
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#define C_0007C0_CSF_INDIRECT2_BUSY 0xFFFFBFFF
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#define S_0007C0_CSQ_INDIRECT2_BUSY(x) (((x) & 0x1) << 15)
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#define G_0007C0_CSQ_INDIRECT2_BUSY(x) (((x) >> 15) & 0x1)
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#define C_0007C0_CSQ_INDIRECT2_BUSY 0xFFFF7FFF
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#define S_0007C0_GUIDMA_BUSY(x) (((x) & 0x1) << 28)
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#define G_0007C0_GUIDMA_BUSY(x) (((x) >> 28) & 0x1)
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#define C_0007C0_GUIDMA_BUSY 0xEFFFFFFF
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#define S_0007C0_VIDDMA_BUSY(x) (((x) & 0x1) << 29)
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#define G_0007C0_VIDDMA_BUSY(x) (((x) >> 29) & 0x1)
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#define C_0007C0_VIDDMA_BUSY 0xDFFFFFFF
|
||||
#define S_0007C0_CMDSTRM_BUSY(x) (((x) & 0x1) << 30)
|
||||
#define G_0007C0_CMDSTRM_BUSY(x) (((x) >> 30) & 0x1)
|
||||
#define C_0007C0_CMDSTRM_BUSY 0xBFFFFFFF
|
||||
#define S_0007C0_CP_BUSY(x) (((x) & 0x1) << 31)
|
||||
#define G_0007C0_CP_BUSY(x) (((x) >> 31) & 0x1)
|
||||
#define C_0007C0_CP_BUSY 0x7FFFFFFF
|
||||
#define R_000E40_RBBM_STATUS 0x000E40
|
||||
#define S_000E40_CMDFIFO_AVAIL(x) (((x) & 0x7F) << 0)
|
||||
#define G_000E40_CMDFIFO_AVAIL(x) (((x) >> 0) & 0x7F)
|
||||
#define C_000E40_CMDFIFO_AVAIL 0xFFFFFF80
|
||||
#define S_000E40_HIRQ_ON_RBB(x) (((x) & 0x1) << 8)
|
||||
#define G_000E40_HIRQ_ON_RBB(x) (((x) >> 8) & 0x1)
|
||||
#define C_000E40_HIRQ_ON_RBB 0xFFFFFEFF
|
||||
#define S_000E40_CPRQ_ON_RBB(x) (((x) & 0x1) << 9)
|
||||
#define G_000E40_CPRQ_ON_RBB(x) (((x) >> 9) & 0x1)
|
||||
#define C_000E40_CPRQ_ON_RBB 0xFFFFFDFF
|
||||
#define S_000E40_CFRQ_ON_RBB(x) (((x) & 0x1) << 10)
|
||||
#define G_000E40_CFRQ_ON_RBB(x) (((x) >> 10) & 0x1)
|
||||
#define C_000E40_CFRQ_ON_RBB 0xFFFFFBFF
|
||||
#define S_000E40_HIRQ_IN_RTBUF(x) (((x) & 0x1) << 11)
|
||||
#define G_000E40_HIRQ_IN_RTBUF(x) (((x) >> 11) & 0x1)
|
||||
#define C_000E40_HIRQ_IN_RTBUF 0xFFFFF7FF
|
||||
#define S_000E40_CPRQ_IN_RTBUF(x) (((x) & 0x1) << 12)
|
||||
#define G_000E40_CPRQ_IN_RTBUF(x) (((x) >> 12) & 0x1)
|
||||
#define C_000E40_CPRQ_IN_RTBUF 0xFFFFEFFF
|
||||
#define S_000E40_CFRQ_IN_RTBUF(x) (((x) & 0x1) << 13)
|
||||
#define G_000E40_CFRQ_IN_RTBUF(x) (((x) >> 13) & 0x1)
|
||||
#define C_000E40_CFRQ_IN_RTBUF 0xFFFFDFFF
|
||||
#define S_000E40_CF_PIPE_BUSY(x) (((x) & 0x1) << 14)
|
||||
#define G_000E40_CF_PIPE_BUSY(x) (((x) >> 14) & 0x1)
|
||||
#define C_000E40_CF_PIPE_BUSY 0xFFFFBFFF
|
||||
#define S_000E40_ENG_EV_BUSY(x) (((x) & 0x1) << 15)
|
||||
#define G_000E40_ENG_EV_BUSY(x) (((x) >> 15) & 0x1)
|
||||
#define C_000E40_ENG_EV_BUSY 0xFFFF7FFF
|
||||
#define S_000E40_CP_CMDSTRM_BUSY(x) (((x) & 0x1) << 16)
|
||||
#define G_000E40_CP_CMDSTRM_BUSY(x) (((x) >> 16) & 0x1)
|
||||
#define C_000E40_CP_CMDSTRM_BUSY 0xFFFEFFFF
|
||||
#define S_000E40_E2_BUSY(x) (((x) & 0x1) << 17)
|
||||
#define G_000E40_E2_BUSY(x) (((x) >> 17) & 0x1)
|
||||
#define C_000E40_E2_BUSY 0xFFFDFFFF
|
||||
#define S_000E40_RB2D_BUSY(x) (((x) & 0x1) << 18)
|
||||
#define G_000E40_RB2D_BUSY(x) (((x) >> 18) & 0x1)
|
||||
#define C_000E40_RB2D_BUSY 0xFFFBFFFF
|
||||
#define S_000E40_RB3D_BUSY(x) (((x) & 0x1) << 19)
|
||||
#define G_000E40_RB3D_BUSY(x) (((x) >> 19) & 0x1)
|
||||
#define C_000E40_RB3D_BUSY 0xFFF7FFFF
|
||||
#define S_000E40_VAP_BUSY(x) (((x) & 0x1) << 20)
|
||||
#define G_000E40_VAP_BUSY(x) (((x) >> 20) & 0x1)
|
||||
#define C_000E40_VAP_BUSY 0xFFEFFFFF
|
||||
#define S_000E40_RE_BUSY(x) (((x) & 0x1) << 21)
|
||||
#define G_000E40_RE_BUSY(x) (((x) >> 21) & 0x1)
|
||||
#define C_000E40_RE_BUSY 0xFFDFFFFF
|
||||
#define S_000E40_TAM_BUSY(x) (((x) & 0x1) << 22)
|
||||
#define G_000E40_TAM_BUSY(x) (((x) >> 22) & 0x1)
|
||||
#define C_000E40_TAM_BUSY 0xFFBFFFFF
|
||||
#define S_000E40_TDM_BUSY(x) (((x) & 0x1) << 23)
|
||||
#define G_000E40_TDM_BUSY(x) (((x) >> 23) & 0x1)
|
||||
#define C_000E40_TDM_BUSY 0xFF7FFFFF
|
||||
#define S_000E40_PB_BUSY(x) (((x) & 0x1) << 24)
|
||||
#define G_000E40_PB_BUSY(x) (((x) >> 24) & 0x1)
|
||||
#define C_000E40_PB_BUSY 0xFEFFFFFF
|
||||
#define S_000E40_TIM_BUSY(x) (((x) & 0x1) << 25)
|
||||
#define G_000E40_TIM_BUSY(x) (((x) >> 25) & 0x1)
|
||||
#define C_000E40_TIM_BUSY 0xFDFFFFFF
|
||||
#define S_000E40_GA_BUSY(x) (((x) & 0x1) << 26)
|
||||
#define G_000E40_GA_BUSY(x) (((x) >> 26) & 0x1)
|
||||
#define C_000E40_GA_BUSY 0xFBFFFFFF
|
||||
#define S_000E40_CBA2D_BUSY(x) (((x) & 0x1) << 27)
|
||||
#define G_000E40_CBA2D_BUSY(x) (((x) >> 27) & 0x1)
|
||||
#define C_000E40_CBA2D_BUSY 0xF7FFFFFF
|
||||
#define S_000E40_GUI_ACTIVE(x) (((x) & 0x1) << 31)
|
||||
#define G_000E40_GUI_ACTIVE(x) (((x) >> 31) & 0x1)
|
||||
#define C_000E40_GUI_ACTIVE 0x7FFFFFFF
|
||||
|
||||
|
||||
#define R_00000D_SCLK_CNTL 0x00000D
|
||||
|
|
|
|||
|
|
@ -1031,6 +1031,16 @@ extern void r100_hdp_reset(struct radeon_device *rdev);
|
|||
extern int r100_rb2d_reset(struct radeon_device *rdev);
|
||||
extern int r100_cp_reset(struct radeon_device *rdev);
|
||||
extern void r100_vga_render_disable(struct radeon_device *rdev);
|
||||
extern int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
|
||||
struct radeon_cs_packet *pkt,
|
||||
struct radeon_object *robj);
|
||||
extern int r100_cs_parse_packet0(struct radeon_cs_parser *p,
|
||||
struct radeon_cs_packet *pkt,
|
||||
const unsigned *auth, unsigned n,
|
||||
radeon_packet0_check_t check);
|
||||
extern int r100_cs_packet_parse(struct radeon_cs_parser *p,
|
||||
struct radeon_cs_packet *pkt,
|
||||
unsigned idx);
|
||||
|
||||
/* r300,r350,rv350,rv370,rv380 */
|
||||
extern void r300_set_reg_safe(struct radeon_device *rdev);
|
||||
|
|
|
|||
|
|
@ -129,54 +129,51 @@ static struct radeon_asic r100_asic = {
|
|||
/*
|
||||
* r300,r350,rv350,rv380
|
||||
*/
|
||||
int r300_init(struct radeon_device *rdev);
|
||||
void r300_errata(struct radeon_device *rdev);
|
||||
void r300_vram_info(struct radeon_device *rdev);
|
||||
int r300_gpu_reset(struct radeon_device *rdev);
|
||||
int r300_mc_init(struct radeon_device *rdev);
|
||||
void r300_mc_fini(struct radeon_device *rdev);
|
||||
void r300_ring_start(struct radeon_device *rdev);
|
||||
void r300_fence_ring_emit(struct radeon_device *rdev,
|
||||
struct radeon_fence *fence);
|
||||
int r300_cs_parse(struct radeon_cs_parser *p);
|
||||
int rv370_pcie_gart_init(struct radeon_device *rdev);
|
||||
void rv370_pcie_gart_fini(struct radeon_device *rdev);
|
||||
int rv370_pcie_gart_enable(struct radeon_device *rdev);
|
||||
void rv370_pcie_gart_disable(struct radeon_device *rdev);
|
||||
void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev);
|
||||
int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
|
||||
uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg);
|
||||
void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
|
||||
void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes);
|
||||
int r300_copy_dma(struct radeon_device *rdev,
|
||||
uint64_t src_offset,
|
||||
uint64_t dst_offset,
|
||||
unsigned num_pages,
|
||||
struct radeon_fence *fence);
|
||||
|
||||
extern int r300_init(struct radeon_device *rdev);
|
||||
extern void r300_fini(struct radeon_device *rdev);
|
||||
extern int r300_suspend(struct radeon_device *rdev);
|
||||
extern int r300_resume(struct radeon_device *rdev);
|
||||
extern int r300_gpu_reset(struct radeon_device *rdev);
|
||||
extern void r300_ring_start(struct radeon_device *rdev);
|
||||
extern void r300_fence_ring_emit(struct radeon_device *rdev,
|
||||
struct radeon_fence *fence);
|
||||
extern int r300_cs_parse(struct radeon_cs_parser *p);
|
||||
extern void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev);
|
||||
extern int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
|
||||
extern uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg);
|
||||
extern void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
|
||||
extern void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes);
|
||||
extern int r300_copy_dma(struct radeon_device *rdev,
|
||||
uint64_t src_offset,
|
||||
uint64_t dst_offset,
|
||||
unsigned num_pages,
|
||||
struct radeon_fence *fence);
|
||||
static struct radeon_asic r300_asic = {
|
||||
.init = &r300_init,
|
||||
.errata = &r300_errata,
|
||||
.vram_info = &r300_vram_info,
|
||||
.fini = &r300_fini,
|
||||
.suspend = &r300_suspend,
|
||||
.resume = &r300_resume,
|
||||
.errata = NULL,
|
||||
.vram_info = NULL,
|
||||
.gpu_reset = &r300_gpu_reset,
|
||||
.mc_init = &r300_mc_init,
|
||||
.mc_fini = &r300_mc_fini,
|
||||
.wb_init = &r100_wb_init,
|
||||
.wb_fini = &r100_wb_fini,
|
||||
.gart_init = &r100_pci_gart_init,
|
||||
.gart_fini = &r100_pci_gart_fini,
|
||||
.gart_enable = &r100_pci_gart_enable,
|
||||
.gart_disable = &r100_pci_gart_disable,
|
||||
.mc_init = NULL,
|
||||
.mc_fini = NULL,
|
||||
.wb_init = NULL,
|
||||
.wb_fini = NULL,
|
||||
.gart_init = NULL,
|
||||
.gart_fini = NULL,
|
||||
.gart_enable = NULL,
|
||||
.gart_disable = NULL,
|
||||
.gart_tlb_flush = &r100_pci_gart_tlb_flush,
|
||||
.gart_set_page = &r100_pci_gart_set_page,
|
||||
.cp_init = &r100_cp_init,
|
||||
.cp_fini = &r100_cp_fini,
|
||||
.cp_disable = &r100_cp_disable,
|
||||
.cp_init = NULL,
|
||||
.cp_fini = NULL,
|
||||
.cp_disable = NULL,
|
||||
.cp_commit = &r100_cp_commit,
|
||||
.ring_start = &r300_ring_start,
|
||||
.ring_test = &r100_ring_test,
|
||||
.ring_ib_execute = &r100_ring_ib_execute,
|
||||
.ib_test = &r100_ib_test,
|
||||
.ib_test = NULL,
|
||||
.irq_set = &r100_irq_set,
|
||||
.irq_process = &r100_irq_process,
|
||||
.get_vblank_counter = &r100_get_vblank_counter,
|
||||
|
|
|
|||
Loading…
Reference in New Issue