drm/i915: fix backlight after resume on 855gm
Some 855gm models (at least ThinkPad X40) regressed because of commitb0cd324fae
Author: Jani Nikula <jani.nikula@intel.com> Date: Wed Nov 12 16:25:43 2014 +0200 drm/i915: don't save/restore backlight hist ctl registers which tried to make our driver more robust by not blindly saving and restoring registers, but it failed to take into account commit0eb96d6ed3
Author: Jesse Barnes <jbarnes@virtuousgeek.org> Date: Wed Oct 14 12:33:41 2009 -0700 drm/i915: save/restore BLC histogram control reg across suspend/resume Fix the regression by enabling hist ctl on gen2. v2: Improved the comment. v3: Improved the comment, again. Reported-and-tested-by: Philipp Gesang <phg@phi-gamma.net> References: http://mid.gmane.org/20150623222648.GD12335@acheron Fixes:b0cd324fae
("drm/i915: don't save/restore backlight hist ctl registers") Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: stable@vger.kernel.org Acked-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
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@ -3491,6 +3491,7 @@ enum skl_disp_power_wells {
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#define BLM_POLARITY_PNV (1 << 0) /* pnv only */
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#define BLC_HIST_CTL (dev_priv->info.display_mmio_offset + 0x61260)
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#define BLM_HISTOGRAM_ENABLE (1 << 31)
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/* New registers for PCH-split platforms. Safe where new bits show up, the
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* register layout machtes with gen4 BLC_PWM_CTL[12]. */
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@ -907,6 +907,14 @@ static void i9xx_enable_backlight(struct intel_connector *connector)
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/* XXX: combine this into above write? */
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intel_panel_actually_set_backlight(connector, panel->backlight.level);
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/*
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* Needed to enable backlight on some 855gm models. BLC_HIST_CTL is
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* 855gm only, but checking for gen2 is safe, as 855gm is the only gen2
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* that has backlight.
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*/
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if (IS_GEN2(dev))
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I915_WRITE(BLC_HIST_CTL, BLM_HISTOGRAM_ENABLE);
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}
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static void i965_enable_backlight(struct intel_connector *connector)
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