sata_inic162x: finally, driver for initio 162x SATA controllers, take #2
Driver for Initio 162x SATA controllers. ATA r/w, ATAPI r, hotplug and suspend/resume work. ATAPI w (recording, that is) broken. Feel free to fix it, but be warned, this controller is weird. Signed-off-by: Tejun Heo <htejun@gmail.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
This commit is contained in:
Tejun Heo
Jeff Garzik
parent
726f0785b6
commit
1fd7a697a3
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@ -147,6 +147,12 @@ config SATA_VITESSE
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If unsure, say N.
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config SATA_INIC162X
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tristate "Initio 162x SATA support (HIGHLY EXPERIMENTAL)"
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depends on PCI && EXPERIMENTAL
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help
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This option enables support for Initio 162x Serial ATA.
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config SATA_INTEL_COMBINED
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bool
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depends on IDE=y && !BLK_DEV_IDE_SATA && (SATA_AHCI || ATA_PIIX)
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@ -15,6 +15,7 @@ obj-$(CONFIG_SATA_SX4) += sata_sx4.o
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obj-$(CONFIG_SATA_NV) += sata_nv.o
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obj-$(CONFIG_SATA_ULI) += sata_uli.o
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obj-$(CONFIG_SATA_MV) += sata_mv.o
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obj-$(CONFIG_SATA_INIC162X) += sata_inic162x.o
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obj-$(CONFIG_PDC_ADMA) += pdc_adma.o
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obj-$(CONFIG_PATA_ALI) += pata_ali.o
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@ -0,0 +1,809 @@
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/*
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* sata_inic162x.c - Driver for Initio 162x SATA controllers
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*
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* Copyright 2006 SUSE Linux Products GmbH
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* Copyright 2006 Tejun Heo <teheo@novell.com>
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*
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* This file is released under GPL v2.
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*
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* This controller is eccentric and easily locks up if something isn't
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* right. Documentation is available at initio's website but it only
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* documents registers (not programming model).
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*
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* - ATA disks work.
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* - Hotplug works.
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* - ATAPI read works but burning doesn't. This thing is really
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* peculiar about ATAPI and I couldn't figure out how ATAPI PIO and
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* ATAPI DMA WRITE should be programmed. If you've got a clue, be
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* my guest.
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* - Both STR and STD work.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <scsi/scsi_host.h>
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#include <linux/libata.h>
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#include <linux/blkdev.h>
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#include <scsi/scsi_device.h>
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#define DRV_NAME "sata_inic162x"
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#define DRV_VERSION "0.1"
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enum {
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MMIO_BAR = 5,
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NR_PORTS = 2,
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HOST_CTL = 0x7c,
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HOST_STAT = 0x7e,
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HOST_IRQ_STAT = 0xbc,
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HOST_IRQ_MASK = 0xbe,
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PORT_SIZE = 0x40,
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/* registers for ATA TF operation */
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PORT_TF = 0x00,
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PORT_ALT_STAT = 0x08,
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PORT_IRQ_STAT = 0x09,
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PORT_IRQ_MASK = 0x0a,
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PORT_PRD_CTL = 0x0b,
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PORT_PRD_ADDR = 0x0c,
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PORT_PRD_XFERLEN = 0x10,
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/* IDMA register */
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PORT_IDMA_CTL = 0x14,
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PORT_SCR = 0x20,
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/* HOST_CTL bits */
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HCTL_IRQOFF = (1 << 8), /* global IRQ off */
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HCTL_PWRDWN = (1 << 13), /* power down PHYs */
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HCTL_SOFTRST = (1 << 13), /* global reset (no phy reset) */
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HCTL_RPGSEL = (1 << 15), /* register page select */
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HCTL_KNOWN_BITS = HCTL_IRQOFF | HCTL_PWRDWN | HCTL_SOFTRST |
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HCTL_RPGSEL,
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/* HOST_IRQ_(STAT|MASK) bits */
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HIRQ_PORT0 = (1 << 0),
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HIRQ_PORT1 = (1 << 1),
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HIRQ_SOFT = (1 << 14),
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HIRQ_GLOBAL = (1 << 15), /* STAT only */
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/* PORT_IRQ_(STAT|MASK) bits */
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PIRQ_OFFLINE = (1 << 0), /* device unplugged */
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PIRQ_ONLINE = (1 << 1), /* device plugged */
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PIRQ_COMPLETE = (1 << 2), /* completion interrupt */
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PIRQ_FATAL = (1 << 3), /* fatal error */
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PIRQ_ATA = (1 << 4), /* ATA interrupt */
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PIRQ_REPLY = (1 << 5), /* reply FIFO not empty */
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PIRQ_PENDING = (1 << 7), /* port IRQ pending (STAT only) */
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PIRQ_ERR = PIRQ_OFFLINE | PIRQ_ONLINE | PIRQ_FATAL,
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PIRQ_MASK_DMA_READ = PIRQ_REPLY | PIRQ_ATA,
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PIRQ_MASK_OTHER = PIRQ_REPLY | PIRQ_COMPLETE,
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PIRQ_MASK_FREEZE = 0xff,
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/* PORT_PRD_CTL bits */
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PRD_CTL_START = (1 << 0),
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PRD_CTL_WR = (1 << 3),
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PRD_CTL_DMAEN = (1 << 7), /* DMA enable */
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/* PORT_IDMA_CTL bits */
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IDMA_CTL_RST_ATA = (1 << 2), /* hardreset ATA bus */
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IDMA_CTL_RST_IDMA = (1 << 5), /* reset IDMA machinary */
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IDMA_CTL_GO = (1 << 7), /* IDMA mode go */
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IDMA_CTL_ATA_NIEN = (1 << 8), /* ATA IRQ disable */
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};
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struct inic_host_priv {
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u16 cached_hctl;
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};
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struct inic_port_priv {
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u8 dfl_prdctl;
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u8 cached_prdctl;
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u8 cached_pirq_mask;
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};
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static int inic_slave_config(struct scsi_device *sdev)
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{
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/* This controller is braindamaged. dma_boundary is 0xffff
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* like others but it will lock up the whole machine HARD if
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* 65536 byte PRD entry is fed. Reduce maximum segment size.
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*/
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blk_queue_max_segment_size(sdev->request_queue, 65536 - 512);
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return ata_scsi_slave_config(sdev);
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}
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static struct scsi_host_template inic_sht = {
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.module = THIS_MODULE,
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.name = DRV_NAME,
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.ioctl = ata_scsi_ioctl,
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.queuecommand = ata_scsi_queuecmd,
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.can_queue = ATA_DEF_QUEUE,
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.this_id = ATA_SHT_THIS_ID,
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.sg_tablesize = LIBATA_MAX_PRD,
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.cmd_per_lun = ATA_SHT_CMD_PER_LUN,
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.emulated = ATA_SHT_EMULATED,
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.use_clustering = ATA_SHT_USE_CLUSTERING,
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.proc_name = DRV_NAME,
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.dma_boundary = ATA_DMA_BOUNDARY,
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.slave_configure = inic_slave_config,
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.slave_destroy = ata_scsi_slave_destroy,
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.bios_param = ata_std_bios_param,
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.suspend = ata_scsi_device_suspend,
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.resume = ata_scsi_device_resume,
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};
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static const int scr_map[] = {
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[SCR_STATUS] = 0,
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[SCR_ERROR] = 1,
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[SCR_CONTROL] = 2,
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};
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static void __iomem * inic_port_base(struct ata_port *ap)
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{
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return ap->host->mmio_base + ap->port_no * PORT_SIZE;
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}
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static void __inic_set_pirq_mask(struct ata_port *ap, u8 mask)
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{
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void __iomem *port_base = inic_port_base(ap);
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struct inic_port_priv *pp = ap->private_data;
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writeb(mask, port_base + PORT_IRQ_MASK);
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pp->cached_pirq_mask = mask;
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}
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static void inic_set_pirq_mask(struct ata_port *ap, u8 mask)
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{
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struct inic_port_priv *pp = ap->private_data;
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if (pp->cached_pirq_mask != mask)
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__inic_set_pirq_mask(ap, mask);
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}
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static void inic_reset_port(void __iomem *port_base)
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{
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void __iomem *idma_ctl = port_base + PORT_IDMA_CTL;
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u16 ctl;
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ctl = readw(idma_ctl);
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ctl &= ~(IDMA_CTL_RST_IDMA | IDMA_CTL_ATA_NIEN | IDMA_CTL_GO);
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/* mask IRQ and assert reset */
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writew(ctl | IDMA_CTL_RST_IDMA | IDMA_CTL_ATA_NIEN, idma_ctl);
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readw(idma_ctl); /* flush */
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/* give it some time */
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msleep(1);
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/* release reset */
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writew(ctl | IDMA_CTL_ATA_NIEN, idma_ctl);
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/* clear irq */
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writeb(0xff, port_base + PORT_IRQ_STAT);
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/* reenable ATA IRQ, turn off IDMA mode */
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writew(ctl, idma_ctl);
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}
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static u32 inic_scr_read(struct ata_port *ap, unsigned sc_reg)
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{
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void __iomem *scr_addr = (void __iomem *)ap->ioaddr.scr_addr;
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void __iomem *addr;
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u32 val;
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if (unlikely(sc_reg >= ARRAY_SIZE(scr_map)))
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return 0xffffffffU;
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addr = scr_addr + scr_map[sc_reg] * 4;
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val = readl(scr_addr + scr_map[sc_reg] * 4);
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/* this controller has stuck DIAG.N, ignore it */
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if (sc_reg == SCR_ERROR)
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val &= ~SERR_PHYRDY_CHG;
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return val;
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}
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static void inic_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val)
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{
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void __iomem *scr_addr = (void __iomem *)ap->ioaddr.scr_addr;
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void __iomem *addr;
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if (unlikely(sc_reg >= ARRAY_SIZE(scr_map)))
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return;
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addr = scr_addr + scr_map[sc_reg] * 4;
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writel(val, scr_addr + scr_map[sc_reg] * 4);
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}
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/*
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* In TF mode, inic162x is very similar to SFF device. TF registers
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* function the same. DMA engine behaves similary using the same PRD
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* format as BMDMA but different command register, interrupt and event
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* notification methods are used. The following inic_bmdma_*()
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* functions do the impedance matching.
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*/
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static void inic_bmdma_setup(struct ata_queued_cmd *qc)
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{
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struct ata_port *ap = qc->ap;
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struct inic_port_priv *pp = ap->private_data;
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void __iomem *port_base = inic_port_base(ap);
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int rw = qc->tf.flags & ATA_TFLAG_WRITE;
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/* make sure device sees PRD table writes */
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wmb();
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/* load transfer length */
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writel(qc->nbytes, port_base + PORT_PRD_XFERLEN);
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/* turn on DMA and specify data direction */
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pp->cached_prdctl = pp->dfl_prdctl | PRD_CTL_DMAEN;
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if (!rw)
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pp->cached_prdctl |= PRD_CTL_WR;
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writeb(pp->cached_prdctl, port_base + PORT_PRD_CTL);
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/* issue r/w command */
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ap->ops->exec_command(ap, &qc->tf);
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}
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static void inic_bmdma_start(struct ata_queued_cmd *qc)
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{
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struct ata_port *ap = qc->ap;
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struct inic_port_priv *pp = ap->private_data;
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void __iomem *port_base = inic_port_base(ap);
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/* start host DMA transaction */
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pp->cached_prdctl |= PRD_CTL_START;
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writeb(pp->cached_prdctl, port_base + PORT_PRD_CTL);
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}
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static void inic_bmdma_stop(struct ata_queued_cmd *qc)
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{
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struct ata_port *ap = qc->ap;
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struct inic_port_priv *pp = ap->private_data;
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void __iomem *port_base = inic_port_base(ap);
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/* stop DMA engine */
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writeb(pp->dfl_prdctl, port_base + PORT_PRD_CTL);
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}
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static u8 inic_bmdma_status(struct ata_port *ap)
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{
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/* event is already verified by the interrupt handler */
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return ATA_DMA_INTR;
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}
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static void inic_irq_clear(struct ata_port *ap)
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{
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/* noop */
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}
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static void inic_host_intr(struct ata_port *ap)
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{
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void __iomem *port_base = inic_port_base(ap);
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struct ata_eh_info *ehi = &ap->eh_info;
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u8 irq_stat;
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/* fetch and clear irq */
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irq_stat = readb(port_base + PORT_IRQ_STAT);
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writeb(irq_stat, port_base + PORT_IRQ_STAT);
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if (likely(!(irq_stat & PIRQ_ERR))) {
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struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->active_tag);
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if (unlikely(!qc || (qc->tf.flags & ATA_TFLAG_POLLING))) {
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ata_chk_status(ap); /* clear ATA interrupt */
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return;
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}
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if (likely(ata_host_intr(ap, qc)))
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return;
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ata_chk_status(ap); /* clear ATA interrupt */
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ata_port_printk(ap, KERN_WARNING, "unhandled "
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"interrupt, irq_stat=%x\n", irq_stat);
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return;
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}
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/* error */
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ata_ehi_push_desc(ehi, "irq_stat=0x%x", irq_stat);
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if (irq_stat & (PIRQ_OFFLINE | PIRQ_ONLINE)) {
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ata_ehi_hotplugged(ehi);
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ata_port_freeze(ap);
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} else
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ata_port_abort(ap);
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}
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static irqreturn_t inic_interrupt(int irq, void *dev_instance)
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{
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struct ata_host *host = dev_instance;
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void __iomem *mmio_base = host->mmio_base;
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u16 host_irq_stat;
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int i, handled = 0;;
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host_irq_stat = readw(mmio_base + HOST_IRQ_STAT);
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if (unlikely(!(host_irq_stat & HIRQ_GLOBAL)))
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goto out;
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spin_lock(&host->lock);
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for (i = 0; i < NR_PORTS; i++) {
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struct ata_port *ap = host->ports[i];
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if (!(host_irq_stat & (HIRQ_PORT0 << i)))
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continue;
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if (likely(ap && !(ap->flags & ATA_FLAG_DISABLED))) {
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inic_host_intr(ap);
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handled++;
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} else {
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if (ata_ratelimit())
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dev_printk(KERN_ERR, host->dev, "interrupt "
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"from disabled port %d (0x%x)\n",
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i, host_irq_stat);
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}
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}
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spin_unlock(&host->lock);
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out:
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return IRQ_RETVAL(handled);
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}
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static unsigned int inic_qc_issue(struct ata_queued_cmd *qc)
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{
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struct ata_port *ap = qc->ap;
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/* ATA IRQ doesn't wait for DMA transfer completion and vice
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* versa. Mask IRQ selectively to detect command completion.
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* Without it, ATA DMA read command can cause data corruption.
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*
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* Something similar might be needed for ATAPI writes. I
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* tried a lot of combinations but couldn't find the solution.
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*/
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if (qc->tf.protocol == ATA_PROT_DMA &&
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!(qc->tf.flags & ATA_TFLAG_WRITE))
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inic_set_pirq_mask(ap, PIRQ_MASK_DMA_READ);
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else
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inic_set_pirq_mask(ap, PIRQ_MASK_OTHER);
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/* Issuing a command to yet uninitialized port locks up the
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* controller. Most of the time, this happens for the first
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* command after reset which are ATA and ATAPI IDENTIFYs.
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* Fast fail if stat is 0x7f or 0xff for those commands.
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*/
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if (unlikely(qc->tf.command == ATA_CMD_ID_ATA ||
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qc->tf.command == ATA_CMD_ID_ATAPI)) {
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u8 stat = ata_chk_status(ap);
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if (stat == 0x7f || stat == 0xff)
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return AC_ERR_HSM;
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}
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return ata_qc_issue_prot(qc);
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}
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static void inic_freeze(struct ata_port *ap)
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{
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void __iomem *port_base = inic_port_base(ap);
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__inic_set_pirq_mask(ap, PIRQ_MASK_FREEZE);
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ata_chk_status(ap);
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writeb(0xff, port_base + PORT_IRQ_STAT);
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readb(port_base + PORT_IRQ_STAT); /* flush */
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}
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static void inic_thaw(struct ata_port *ap)
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{
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void __iomem *port_base = inic_port_base(ap);
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ata_chk_status(ap);
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writeb(0xff, port_base + PORT_IRQ_STAT);
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__inic_set_pirq_mask(ap, PIRQ_MASK_OTHER);
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readb(port_base + PORT_IRQ_STAT); /* flush */
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}
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/*
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* SRST and SControl hardreset don't give valid signature on this
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* controller. Only controller specific hardreset mechanism works.
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*/
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static int inic_hardreset(struct ata_port *ap, unsigned int *class)
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{
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void __iomem *port_base = inic_port_base(ap);
|
||||
void __iomem *idma_ctl = port_base + PORT_IDMA_CTL;
|
||||
const unsigned long *timing = sata_ehc_deb_timing(&ap->eh_context);
|
||||
u16 val;
|
||||
int rc;
|
||||
|
||||
/* hammer it into sane state */
|
||||
inic_reset_port(port_base);
|
||||
|
||||
if (ata_port_offline(ap)) {
|
||||
*class = ATA_DEV_NONE;
|
||||
return 0;
|
||||
}
|
||||
|
||||
val = readw(idma_ctl);
|
||||
writew(val | IDMA_CTL_RST_ATA, idma_ctl);
|
||||
readw(idma_ctl); /* flush */
|
||||
msleep(1);
|
||||
writew(val & ~IDMA_CTL_RST_ATA, idma_ctl);
|
||||
|
||||
rc = sata_phy_resume(ap, timing);
|
||||
if (rc) {
|
||||
ata_port_printk(ap, KERN_WARNING, "failed to resume "
|
||||
"link for reset (errno=%d)\n", rc);
|
||||
return rc;
|
||||
}
|
||||
|
||||
msleep(150);
|
||||
|
||||
*class = ATA_DEV_NONE;
|
||||
if (ata_port_online(ap)) {
|
||||
struct ata_taskfile tf;
|
||||
|
||||
if (ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT)) {
|
||||
ata_port_printk(ap, KERN_WARNING,
|
||||
"device busy after hardreset\n");
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
ata_tf_read(ap, &tf);
|
||||
*class = ata_dev_classify(&tf);
|
||||
if (*class == ATA_DEV_UNKNOWN)
|
||||
*class = ATA_DEV_NONE;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void inic_error_handler(struct ata_port *ap)
|
||||
{
|
||||
void __iomem *port_base = inic_port_base(ap);
|
||||
struct inic_port_priv *pp = ap->private_data;
|
||||
unsigned long flags;
|
||||
|
||||
/* reset PIO HSM and stop DMA engine */
|
||||
inic_reset_port(port_base);
|
||||
|
||||
spin_lock_irqsave(ap->lock, flags);
|
||||
ap->hsm_task_state = HSM_ST_IDLE;
|
||||
writeb(pp->dfl_prdctl, port_base + PORT_PRD_CTL);
|
||||
spin_unlock_irqrestore(ap->lock, flags);
|
||||
|
||||
/* PIO and DMA engines have been stopped, perform recovery */
|
||||
ata_do_eh(ap, ata_std_prereset, NULL, inic_hardreset,
|
||||
ata_std_postreset);
|
||||
}
|
||||
|
||||
static void inic_post_internal_cmd(struct ata_queued_cmd *qc)
|
||||
{
|
||||
/* make DMA engine forget about the failed command */
|
||||
if (qc->err_mask)
|
||||
inic_reset_port(inic_port_base(qc->ap));
|
||||
}
|
||||
|
||||
static void inic_dev_config(struct ata_port *ap, struct ata_device *dev)
|
||||
{
|
||||
/* inic can only handle upto LBA28 max sectors */
|
||||
if (dev->max_sectors > ATA_MAX_SECTORS)
|
||||
dev->max_sectors = ATA_MAX_SECTORS;
|
||||
}
|
||||
|
||||
static void init_port(struct ata_port *ap)
|
||||
{
|
||||
void __iomem *port_base = inic_port_base(ap);
|
||||
|
||||
/* Setup PRD address */
|
||||
writel(ap->prd_dma, port_base + PORT_PRD_ADDR);
|
||||
}
|
||||
|
||||
static int inic_port_resume(struct ata_port *ap)
|
||||
{
|
||||
init_port(ap);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int inic_port_start(struct ata_port *ap)
|
||||
{
|
||||
void __iomem *port_base = inic_port_base(ap);
|
||||
struct inic_port_priv *pp;
|
||||
u8 tmp;
|
||||
int rc;
|
||||
|
||||
/* alloc and initialize private data */
|
||||
pp = kzalloc(sizeof(*pp), GFP_KERNEL);
|
||||
if (!pp)
|
||||
return -ENOMEM;
|
||||
ap->private_data = pp;
|
||||
|
||||
/* default PRD_CTL value, DMAEN, WR and START off */
|
||||
tmp = readb(port_base + PORT_PRD_CTL);
|
||||
tmp &= ~(PRD_CTL_DMAEN | PRD_CTL_WR | PRD_CTL_START);
|
||||
pp->dfl_prdctl = tmp;
|
||||
|
||||
/* Alloc resources */
|
||||
rc = ata_port_start(ap);
|
||||
if (rc) {
|
||||
kfree(pp);
|
||||
return rc;
|
||||
}
|
||||
|
||||
init_port(ap);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void inic_port_stop(struct ata_port *ap)
|
||||
{
|
||||
ata_port_stop(ap);
|
||||
kfree(ap->private_data);
|
||||
}
|
||||
|
||||
static struct ata_port_operations inic_port_ops = {
|
||||
.port_disable = ata_port_disable,
|
||||
.tf_load = ata_tf_load,
|
||||
.tf_read = ata_tf_read,
|
||||
.check_status = ata_check_status,
|
||||
.exec_command = ata_exec_command,
|
||||
.dev_select = ata_std_dev_select,
|
||||
|
||||
.scr_read = inic_scr_read,
|
||||
.scr_write = inic_scr_write,
|
||||
|
||||
.bmdma_setup = inic_bmdma_setup,
|
||||
.bmdma_start = inic_bmdma_start,
|
||||
.bmdma_stop = inic_bmdma_stop,
|
||||
.bmdma_status = inic_bmdma_status,
|
||||
|
||||
.irq_handler = inic_interrupt,
|
||||
.irq_clear = inic_irq_clear,
|
||||
|
||||
.qc_prep = ata_qc_prep,
|
||||
.qc_issue = inic_qc_issue,
|
||||
.data_xfer = ata_pio_data_xfer,
|
||||
|
||||
.freeze = inic_freeze,
|
||||
.thaw = inic_thaw,
|
||||
.error_handler = inic_error_handler,
|
||||
.post_internal_cmd = inic_post_internal_cmd,
|
||||
.dev_config = inic_dev_config,
|
||||
|
||||
.port_resume = inic_port_resume,
|
||||
|
||||
.port_start = inic_port_start,
|
||||
.port_stop = inic_port_stop,
|
||||
.host_stop = ata_pci_host_stop
|
||||
};
|
||||
|
||||
static struct ata_port_info inic_port_info = {
|
||||
.sht = &inic_sht,
|
||||
/* For some reason, ATA_PROT_ATAPI is broken on this
|
||||
* controller, and no, PIO_POLLING does't fix it. It somehow
|
||||
* manages to report the wrong ireason and ignoring ireason
|
||||
* results in machine lock up. Tell libata to always prefer
|
||||
* DMA.
|
||||
*/
|
||||
.flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
|
||||
.pio_mask = 0x1f, /* pio0-4 */
|
||||
.mwdma_mask = 0x07, /* mwdma0-2 */
|
||||
.udma_mask = 0x7f, /* udma0-6 */
|
||||
.port_ops = &inic_port_ops
|
||||
};
|
||||
|
||||
static int init_controller(void __iomem *mmio_base, u16 hctl)
|
||||
{
|
||||
int i;
|
||||
u16 val;
|
||||
|
||||
hctl &= ~HCTL_KNOWN_BITS;
|
||||
|
||||
/* Soft reset whole controller. Spec says reset duration is 3
|
||||
* PCI clocks, be generous and give it 10ms.
|
||||
*/
|
||||
writew(hctl | HCTL_SOFTRST, mmio_base + HOST_CTL);
|
||||
readw(mmio_base + HOST_CTL); /* flush */
|
||||
|
||||
for (i = 0; i < 10; i++) {
|
||||
msleep(1);
|
||||
val = readw(mmio_base + HOST_CTL);
|
||||
if (!(val & HCTL_SOFTRST))
|
||||
break;
|
||||
}
|
||||
|
||||
if (val & HCTL_SOFTRST)
|
||||
return -EIO;
|
||||
|
||||
/* mask all interrupts and reset ports */
|
||||
for (i = 0; i < NR_PORTS; i++) {
|
||||
void __iomem *port_base = mmio_base + i * PORT_SIZE;
|
||||
|
||||
writeb(0xff, port_base + PORT_IRQ_MASK);
|
||||
inic_reset_port(port_base);
|
||||
}
|
||||
|
||||
/* port IRQ is masked now, unmask global IRQ */
|
||||
writew(hctl & ~HCTL_IRQOFF, mmio_base + HOST_CTL);
|
||||
val = readw(mmio_base + HOST_IRQ_MASK);
|
||||
val &= ~(HIRQ_PORT0 | HIRQ_PORT1);
|
||||
writew(val, mmio_base + HOST_IRQ_MASK);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int inic_pci_device_resume(struct pci_dev *pdev)
|
||||
{
|
||||
struct ata_host *host = dev_get_drvdata(&pdev->dev);
|
||||
struct inic_host_priv *hpriv = host->private_data;
|
||||
void __iomem *mmio_base = host->mmio_base;
|
||||
int rc;
|
||||
|
||||
ata_pci_device_do_resume(pdev);
|
||||
|
||||
if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
|
||||
printk("XXX\n");
|
||||
rc = init_controller(mmio_base, hpriv->cached_hctl);
|
||||
if (rc)
|
||||
return rc;
|
||||
}
|
||||
|
||||
ata_host_resume(host);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int inic_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
|
||||
{
|
||||
static int printed_version;
|
||||
struct ata_port_info *pinfo = &inic_port_info;
|
||||
struct ata_probe_ent *probe_ent;
|
||||
struct inic_host_priv *hpriv;
|
||||
void __iomem *mmio_base;
|
||||
int i, rc;
|
||||
|
||||
if (!printed_version++)
|
||||
dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
|
||||
|
||||
rc = pci_enable_device(pdev);
|
||||
if (rc)
|
||||
return rc;
|
||||
|
||||
rc = pci_request_regions(pdev, DRV_NAME);
|
||||
if (rc)
|
||||
goto err_out;
|
||||
|
||||
rc = -ENOMEM;
|
||||
mmio_base = pci_iomap(pdev, MMIO_BAR, 0);
|
||||
if (!mmio_base)
|
||||
goto err_out_regions;
|
||||
|
||||
/* Set dma_mask. This devices doesn't support 64bit addressing. */
|
||||
rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
|
||||
if (rc) {
|
||||
dev_printk(KERN_ERR, &pdev->dev,
|
||||
"32-bit DMA enable failed\n");
|
||||
goto err_out_map;
|
||||
}
|
||||
|
||||
rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
|
||||
if (rc) {
|
||||
dev_printk(KERN_ERR, &pdev->dev,
|
||||
"32-bit consistent DMA enable failed\n");
|
||||
goto err_out_map;
|
||||
}
|
||||
|
||||
rc = -ENOMEM;
|
||||
probe_ent = kzalloc(sizeof(*probe_ent), GFP_KERNEL);
|
||||
if (!probe_ent)
|
||||
goto err_out_map;
|
||||
|
||||
hpriv = kzalloc(sizeof(*hpriv), GFP_KERNEL);
|
||||
if (!hpriv)
|
||||
goto err_out_ent;
|
||||
|
||||
probe_ent->dev = &pdev->dev;
|
||||
INIT_LIST_HEAD(&probe_ent->node);
|
||||
|
||||
probe_ent->sht = pinfo->sht;
|
||||
probe_ent->port_flags = pinfo->flags;
|
||||
probe_ent->pio_mask = pinfo->pio_mask;
|
||||
probe_ent->mwdma_mask = pinfo->mwdma_mask;
|
||||
probe_ent->udma_mask = pinfo->udma_mask;
|
||||
probe_ent->port_ops = pinfo->port_ops;
|
||||
probe_ent->n_ports = NR_PORTS;
|
||||
|
||||
probe_ent->irq = pdev->irq;
|
||||
probe_ent->irq_flags = SA_SHIRQ;
|
||||
|
||||
probe_ent->mmio_base = mmio_base;
|
||||
|
||||
for (i = 0; i < NR_PORTS; i++) {
|
||||
struct ata_ioports *port = &probe_ent->port[i];
|
||||
unsigned long port_base =
|
||||
(unsigned long)mmio_base + i * PORT_SIZE;
|
||||
|
||||
port->cmd_addr = pci_resource_start(pdev, 2 * i);
|
||||
port->altstatus_addr =
|
||||
port->ctl_addr =
|
||||
pci_resource_start(pdev, 2 * i + 1) | ATA_PCI_CTL_OFS;
|
||||
port->scr_addr = port_base + PORT_SCR;
|
||||
|
||||
ata_std_ports(port);
|
||||
}
|
||||
|
||||
probe_ent->private_data = hpriv;
|
||||
hpriv->cached_hctl = readw(mmio_base + HOST_CTL);
|
||||
|
||||
rc = init_controller(mmio_base, hpriv->cached_hctl);
|
||||
if (rc) {
|
||||
dev_printk(KERN_ERR, &pdev->dev,
|
||||
"failed to initialize controller\n");
|
||||
goto err_out_hpriv;
|
||||
}
|
||||
|
||||
pci_set_master(pdev);
|
||||
|
||||
rc = -ENODEV;
|
||||
if (!ata_device_add(probe_ent))
|
||||
goto err_out_hpriv;
|
||||
|
||||
kfree(probe_ent);
|
||||
|
||||
return 0;
|
||||
|
||||
err_out_hpriv:
|
||||
kfree(hpriv);
|
||||
err_out_ent:
|
||||
kfree(probe_ent);
|
||||
err_out_map:
|
||||
pci_iounmap(pdev, mmio_base);
|
||||
err_out_regions:
|
||||
pci_release_regions(pdev);
|
||||
err_out:
|
||||
pci_disable_device(pdev);
|
||||
return rc;
|
||||
}
|
||||
|
||||
static const struct pci_device_id inic_pci_tbl[] = {
|
||||
{ PCI_VDEVICE(INIT, 0x1622), },
|
||||
{ },
|
||||
};
|
||||
|
||||
static struct pci_driver inic_pci_driver = {
|
||||
.name = DRV_NAME,
|
||||
.id_table = inic_pci_tbl,
|
||||
.suspend = ata_pci_device_suspend,
|
||||
.resume = inic_pci_device_resume,
|
||||
.probe = inic_init_one,
|
||||
.remove = ata_pci_remove_one,
|
||||
};
|
||||
|
||||
static int __init inic_init(void)
|
||||
{
|
||||
return pci_register_driver(&inic_pci_driver);
|
||||
}
|
||||
|
||||
static void __exit inic_exit(void)
|
||||
{
|
||||
pci_unregister_driver(&inic_pci_driver);
|
||||
}
|
||||
|
||||
MODULE_AUTHOR("Tejun Heo");
|
||||
MODULE_DESCRIPTION("low-level driver for Initio 162x SATA");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
MODULE_DEVICE_TABLE(pci, inic_pci_tbl);
|
||||
MODULE_VERSION(DRV_VERSION);
|
||||
|
||||
module_init(inic_init);
|
||||
module_exit(inic_exit);
|
||||
Loading…
Reference in New Issue