PCI: iproc: Add Broadcom iProc PCIe support
Add support for the Broadcom iProc PCIe controller. pcie-iproc.c is the common core driver, and a front-end bus interface needs to be added to support different bus interfaces. pcie-iproc-platform.c contains the support for the platform bus interface. Signed-off-by: Ray Jui <rjui@broadcom.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Scott Branden <sbranden@broadcom.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Ray Jui
Bjorn Helgaas
parent
1b55d62259
commit
1fb37a8178
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@ -106,4 +106,23 @@ config PCI_VERSATILE
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bool "ARM Versatile PB PCI controller"
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depends on ARCH_VERSATILE
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config PCIE_IPROC
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tristate "Broadcom iProc PCIe controller"
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depends on OF && ARM
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default n
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help
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This enables the iProc PCIe core controller support for Broadcom's
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iProc family of SoCs. An appropriate bus interface driver also needs
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to be enabled
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config PCIE_IPROC_PLATFORM
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tristate "Broadcom iProc PCIe platform bus driver"
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depends on ARCH_BCM_IPROC || (ARM && COMPILE_TEST)
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depends on OF
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select PCIE_IPROC
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default ARCH_BCM_IPROC
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help
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Say Y here if you want to use the Broadcom iProc PCIe controller
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through the generic platform bus interface
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endmenu
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@ -13,3 +13,5 @@ obj-$(CONFIG_PCIE_XILINX) += pcie-xilinx.o
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obj-$(CONFIG_PCI_XGENE) += pci-xgene.o
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obj-$(CONFIG_PCI_LAYERSCAPE) += pci-layerscape.o
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obj-$(CONFIG_PCI_VERSATILE) += pci-versatile.o
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obj-$(CONFIG_PCIE_IPROC) += pcie-iproc.o
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obj-$(CONFIG_PCIE_IPROC_PLATFORM) += pcie-iproc-platform.o
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@ -0,0 +1,108 @@
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/*
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* Copyright (C) 2015 Broadcom Corporation
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation version 2.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/clk.h>
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#include <linux/module.h>
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#include <linux/slab.h>
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#include <linux/interrupt.h>
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#include <linux/platform_device.h>
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#include <linux/of_address.h>
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#include <linux/of_pci.h>
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#include <linux/of_irq.h>
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#include <linux/of_platform.h>
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#include <linux/phy/phy.h>
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#include "pcie-iproc.h"
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static int iproc_pcie_pltfm_probe(struct platform_device *pdev)
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{
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struct iproc_pcie *pcie;
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struct device_node *np = pdev->dev.of_node;
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struct resource reg;
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resource_size_t iobase = 0;
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LIST_HEAD(res);
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int ret;
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pcie = devm_kzalloc(&pdev->dev, sizeof(struct iproc_pcie), GFP_KERNEL);
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if (!pcie)
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return -ENOMEM;
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pcie->dev = &pdev->dev;
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platform_set_drvdata(pdev, pcie);
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ret = of_address_to_resource(np, 0, ®);
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if (ret < 0) {
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dev_err(pcie->dev, "unable to obtain controller resources\n");
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return ret;
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}
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pcie->base = devm_ioremap(pcie->dev, reg.start, resource_size(®));
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if (!pcie->base) {
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dev_err(pcie->dev, "unable to map controller registers\n");
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return -ENOMEM;
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}
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/* PHY use is optional */
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pcie->phy = devm_phy_get(&pdev->dev, "pcie-phy");
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if (IS_ERR(pcie->phy)) {
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if (PTR_ERR(pcie->phy) == -EPROBE_DEFER)
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return -EPROBE_DEFER;
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pcie->phy = NULL;
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}
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ret = of_pci_get_host_bridge_resources(np, 0, 0xff, &res, &iobase);
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if (ret) {
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dev_err(pcie->dev,
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"unable to get PCI host bridge resources\n");
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return ret;
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}
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pcie->resources = &res;
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ret = iproc_pcie_setup(pcie);
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if (ret) {
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dev_err(pcie->dev, "PCIe controller setup failed\n");
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return ret;
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}
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return 0;
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}
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static int iproc_pcie_pltfm_remove(struct platform_device *pdev)
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{
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struct iproc_pcie *pcie = platform_get_drvdata(pdev);
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return iproc_pcie_remove(pcie);
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}
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static const struct of_device_id iproc_pcie_of_match_table[] = {
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{ .compatible = "brcm,iproc-pcie", },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, iproc_pcie_of_match_table);
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static struct platform_driver iproc_pcie_pltfm_driver = {
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.driver = {
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.name = "iproc-pcie",
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.of_match_table = of_match_ptr(iproc_pcie_of_match_table),
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},
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.probe = iproc_pcie_pltfm_probe,
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.remove = iproc_pcie_pltfm_remove,
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};
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module_platform_driver(iproc_pcie_pltfm_driver);
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MODULE_AUTHOR("Ray Jui <rjui@broadcom.com>");
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MODULE_DESCRIPTION("Broadcom iPROC PCIe platform driver");
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MODULE_LICENSE("GPL v2");
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@ -0,0 +1,268 @@
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/*
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* Copyright (C) 2014 Hauke Mehrtens <hauke@hauke-m.de>
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* Copyright (C) 2015 Broadcom Corporatcommon ion
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation version 2.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/msi.h>
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#include <linux/clk.h>
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#include <linux/module.h>
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#include <linux/mbus.h>
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#include <linux/slab.h>
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <linux/platform_device.h>
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#include <linux/of_address.h>
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#include <linux/of_pci.h>
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#include <linux/of_irq.h>
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#include <linux/of_platform.h>
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#include <linux/phy/phy.h>
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#include "pcie-iproc.h"
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#define CLK_CONTROL_OFFSET 0x000
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#define EP_MODE_SURVIVE_PERST_SHIFT 1
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#define EP_MODE_SURVIVE_PERST BIT(EP_MODE_SURVIVE_PERST_SHIFT)
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#define RC_PCIE_RST_OUTPUT_SHIFT 0
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#define RC_PCIE_RST_OUTPUT BIT(RC_PCIE_RST_OUTPUT_SHIFT)
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#define CFG_IND_ADDR_OFFSET 0x120
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#define CFG_IND_ADDR_MASK 0x00001ffc
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#define CFG_IND_DATA_OFFSET 0x124
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#define CFG_ADDR_OFFSET 0x1f8
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#define CFG_ADDR_BUS_NUM_SHIFT 20
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#define CFG_ADDR_BUS_NUM_MASK 0x0ff00000
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#define CFG_ADDR_DEV_NUM_SHIFT 15
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#define CFG_ADDR_DEV_NUM_MASK 0x000f8000
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#define CFG_ADDR_FUNC_NUM_SHIFT 12
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#define CFG_ADDR_FUNC_NUM_MASK 0x00007000
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#define CFG_ADDR_REG_NUM_SHIFT 2
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#define CFG_ADDR_REG_NUM_MASK 0x00000ffc
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#define CFG_ADDR_CFG_TYPE_SHIFT 0
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#define CFG_ADDR_CFG_TYPE_MASK 0x00000003
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#define CFG_DATA_OFFSET 0x1fc
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#define SYS_RC_INTX_EN 0x330
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#define SYS_RC_INTX_MASK 0xf
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static inline struct iproc_pcie *sys_to_pcie(struct pci_sys_data *sys)
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{
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return sys->private_data;
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}
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/**
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* Note access to the configuration registers are protected at the higher layer
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* by 'pci_lock' in drivers/pci/access.c
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*/
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static void __iomem *iproc_pcie_map_cfg_bus(struct pci_bus *bus,
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unsigned int devfn,
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int where)
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{
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struct pci_sys_data *sys = bus->sysdata;
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struct iproc_pcie *pcie = sys_to_pcie(sys);
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unsigned slot = PCI_SLOT(devfn);
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unsigned fn = PCI_FUNC(devfn);
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unsigned busno = bus->number;
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u32 val;
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/* root complex access */
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if (busno == 0) {
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if (slot >= 1)
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return NULL;
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writel(where & CFG_IND_ADDR_MASK,
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pcie->base + CFG_IND_ADDR_OFFSET);
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return (pcie->base + CFG_IND_DATA_OFFSET);
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}
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if (fn > 1)
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return NULL;
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/* EP device access */
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val = (busno << CFG_ADDR_BUS_NUM_SHIFT) |
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(slot << CFG_ADDR_DEV_NUM_SHIFT) |
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(fn << CFG_ADDR_FUNC_NUM_SHIFT) |
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(where & CFG_ADDR_REG_NUM_MASK) |
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(1 & CFG_ADDR_CFG_TYPE_MASK);
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writel(val, pcie->base + CFG_ADDR_OFFSET);
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return (pcie->base + CFG_DATA_OFFSET);
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}
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static struct pci_ops iproc_pcie_ops = {
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.map_bus = iproc_pcie_map_cfg_bus,
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.read = pci_generic_config_read32,
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.write = pci_generic_config_write32,
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};
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static void iproc_pcie_reset(struct iproc_pcie *pcie)
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{
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u32 val;
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/*
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* Configure the PCIe controller as root complex and send a downstream
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* reset
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*/
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val = EP_MODE_SURVIVE_PERST | RC_PCIE_RST_OUTPUT;
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writel(val, pcie->base + CLK_CONTROL_OFFSET);
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udelay(250);
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val &= ~EP_MODE_SURVIVE_PERST;
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writel(val, pcie->base + CLK_CONTROL_OFFSET);
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msleep(250);
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}
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static int iproc_pcie_check_link(struct iproc_pcie *pcie, struct pci_bus *bus)
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{
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u8 hdr_type;
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u32 link_ctrl;
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u16 pos, link_status;
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int link_is_active = 0;
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/* make sure we are not in EP mode */
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pci_bus_read_config_byte(bus, 0, PCI_HEADER_TYPE, &hdr_type);
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if ((hdr_type & 0x7f) != PCI_HEADER_TYPE_BRIDGE) {
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dev_err(pcie->dev, "in EP mode, hdr=%#02x\n", hdr_type);
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return -EFAULT;
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}
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/* force class to PCI_CLASS_BRIDGE_PCI (0x0604) */
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pci_bus_write_config_word(bus, 0, PCI_CLASS_DEVICE,
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PCI_CLASS_BRIDGE_PCI);
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/* check link status to see if link is active */
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pos = pci_bus_find_capability(bus, 0, PCI_CAP_ID_EXP);
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pci_bus_read_config_word(bus, 0, pos + PCI_EXP_LNKSTA, &link_status);
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if (link_status & PCI_EXP_LNKSTA_NLW)
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link_is_active = 1;
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if (!link_is_active) {
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/* try GEN 1 link speed */
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#define PCI_LINK_STATUS_CTRL_2_OFFSET 0x0dc
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#define PCI_TARGET_LINK_SPEED_MASK 0xf
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#define PCI_TARGET_LINK_SPEED_GEN2 0x2
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#define PCI_TARGET_LINK_SPEED_GEN1 0x1
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pci_bus_read_config_dword(bus, 0,
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PCI_LINK_STATUS_CTRL_2_OFFSET,
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&link_ctrl);
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if ((link_ctrl & PCI_TARGET_LINK_SPEED_MASK) ==
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PCI_TARGET_LINK_SPEED_GEN2) {
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link_ctrl &= ~PCI_TARGET_LINK_SPEED_MASK;
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link_ctrl |= PCI_TARGET_LINK_SPEED_GEN1;
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pci_bus_write_config_dword(bus, 0,
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PCI_LINK_STATUS_CTRL_2_OFFSET,
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link_ctrl);
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msleep(100);
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pos = pci_bus_find_capability(bus, 0, PCI_CAP_ID_EXP);
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pci_bus_read_config_word(bus, 0, pos + PCI_EXP_LNKSTA,
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&link_status);
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if (link_status & PCI_EXP_LNKSTA_NLW)
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link_is_active = 1;
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}
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}
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dev_info(pcie->dev, "link: %s\n", link_is_active ? "UP" : "DOWN");
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return link_is_active ? 0 : -ENODEV;
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}
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static void iproc_pcie_enable(struct iproc_pcie *pcie)
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{
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writel(SYS_RC_INTX_MASK, pcie->base + SYS_RC_INTX_EN);
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}
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int iproc_pcie_setup(struct iproc_pcie *pcie)
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{
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int ret;
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struct pci_bus *bus;
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if (!pcie || !pcie->dev || !pcie->base)
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return -EINVAL;
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if (pcie->phy) {
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ret = phy_init(pcie->phy);
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if (ret) {
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dev_err(pcie->dev, "unable to initialize PCIe PHY\n");
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return ret;
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}
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ret = phy_power_on(pcie->phy);
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if (ret) {
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dev_err(pcie->dev, "unable to power on PCIe PHY\n");
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goto err_exit_phy;
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}
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}
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iproc_pcie_reset(pcie);
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pcie->sysdata.private_data = pcie;
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bus = pci_create_root_bus(pcie->dev, 0, &iproc_pcie_ops,
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&pcie->sysdata, pcie->resources);
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if (!bus) {
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dev_err(pcie->dev, "unable to create PCI root bus\n");
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ret = -ENOMEM;
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goto err_power_off_phy;
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}
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pcie->root_bus = bus;
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ret = iproc_pcie_check_link(pcie, bus);
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if (ret) {
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dev_err(pcie->dev, "no PCIe EP device detected\n");
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goto err_rm_root_bus;
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}
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iproc_pcie_enable(pcie);
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pci_scan_child_bus(bus);
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pci_assign_unassigned_bus_resources(bus);
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pci_fixup_irqs(pci_common_swizzle, of_irq_parse_and_map_pci);
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pci_bus_add_devices(bus);
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return 0;
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err_rm_root_bus:
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pci_stop_root_bus(bus);
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pci_remove_root_bus(bus);
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err_power_off_phy:
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if (pcie->phy)
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phy_power_off(pcie->phy);
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err_exit_phy:
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if (pcie->phy)
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phy_exit(pcie->phy);
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return ret;
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}
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EXPORT_SYMBOL(iproc_pcie_setup);
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int iproc_pcie_remove(struct iproc_pcie *pcie)
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{
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pci_stop_root_bus(pcie->root_bus);
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pci_remove_root_bus(pcie->root_bus);
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if (pcie->phy) {
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phy_power_off(pcie->phy);
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phy_exit(pcie->phy);
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}
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return 0;
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}
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EXPORT_SYMBOL(iproc_pcie_remove);
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MODULE_AUTHOR("Ray Jui <rjui@broadcom.com>");
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MODULE_DESCRIPTION("Broadcom iPROC PCIe common driver");
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MODULE_LICENSE("GPL v2");
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@ -0,0 +1,42 @@
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/*
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* Copyright (C) 2014-2015 Broadcom Corporation
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*
|
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation version 2.
|
||||
*
|
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
|
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* kind, whether express or implied; without even the implied warranty
|
||||
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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* GNU General Public License for more details.
|
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*/
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#ifndef _PCIE_IPROC_H
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#define _PCIE_IPROC_H
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#define IPROC_PCIE_MAX_NUM_IRQS 6
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/**
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* iProc PCIe device
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* @dev: pointer to device data structure
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* @base: PCIe host controller I/O register base
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* @resources: linked list of all PCI resources
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* @sysdata: Per PCI controller data
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* @root_bus: pointer to root bus
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* @phy: optional PHY device that controls the Serdes
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* @irqs: interrupt IDs
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*/
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struct iproc_pcie {
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struct device *dev;
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void __iomem *base;
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struct list_head *resources;
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struct pci_sys_data sysdata;
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struct pci_bus *root_bus;
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struct phy *phy;
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int irqs[IPROC_PCIE_MAX_NUM_IRQS];
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};
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int iproc_pcie_setup(struct iproc_pcie *pcie);
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||||
int iproc_pcie_remove(struct iproc_pcie *pcie);
|
||||
|
||||
#endif /* _PCIE_IPROC_H */
|
||||
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Reference in New Issue