netxen: remove sub 64-bit mem accesses
Sub 64-bit / unaligned access to oncard memory was only used
by old diagnostic tools, causes some intermittent issues when
memory controller agent is used. The new access method was
added by commit ea6828b8aa
("netxen: improve pci memory access"). Firmware init anyway
uses 8-byte strides.
This also fixes address/offset calculation for NX2031 context
memory (SIU). For NX3031, SIU uses same register offsets
as packet memory (MIU).
Signed-off-by: Amit Kumar Salecha <amit@netxen.com>
Signed-off-by: Dhananjay Phadke <dhananjay@netxen.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Amit Kumar Salecha
David S. Miller
parent
89d71a66c4
commit
1f5e055db3
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@ -1180,8 +1180,8 @@ struct netxen_adapter {
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u32 (*crb_read)(struct netxen_adapter *, ulong);
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int (*crb_write)(struct netxen_adapter *, ulong, u32);
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int (*pci_mem_read)(struct netxen_adapter *, u64, void *, int);
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int (*pci_mem_write)(struct netxen_adapter *, u64, void *, int);
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int (*pci_mem_read)(struct netxen_adapter *, u64, u64 *);
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int (*pci_mem_write)(struct netxen_adapter *, u64, u64);
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unsigned long (*pci_set_window)(struct netxen_adapter *,
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unsigned long long);
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@ -661,40 +661,47 @@ enum {
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#define NETXEN_NIU_AP_STATION_ADDR_0(I) (NETXEN_CRB_NIU+0xa0040+(I)*0x10000)
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#define NETXEN_NIU_AP_STATION_ADDR_1(I) (NETXEN_CRB_NIU+0xa0044+(I)*0x10000)
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#define TEST_AGT_CTRL (0x00)
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#define TA_CTL_START 1
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#define TA_CTL_ENABLE 2
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#define TA_CTL_WRITE 4
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#define TA_CTL_BUSY 8
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/*
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* Register offsets for MN
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*/
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#define MIU_CONTROL (0x000)
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#define MIU_TEST_AGT_CTRL (0x090)
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#define MIU_TEST_AGT_ADDR_LO (0x094)
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#define MIU_TEST_AGT_ADDR_HI (0x098)
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#define MIU_TEST_AGT_WRDATA_LO (0x0a0)
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#define MIU_TEST_AGT_WRDATA_HI (0x0a4)
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#define MIU_TEST_AGT_WRDATA(i) (0x0a0+(4*(i)))
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#define MIU_TEST_AGT_RDDATA_LO (0x0a8)
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#define MIU_TEST_AGT_RDDATA_HI (0x0ac)
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#define MIU_TEST_AGT_RDDATA(i) (0x0a8+(4*(i)))
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#define MIU_TEST_AGT_ADDR_MASK 0xfffffff8
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#define MIU_TEST_AGT_UPPER_ADDR(off) (0)
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#define MIU_TEST_AGT_BASE (0x90)
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/* MIU_TEST_AGT_CTRL flags. work for SIU as well */
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#define MIU_TA_CTL_START 1
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#define MIU_TA_CTL_ENABLE 2
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#define MIU_TA_CTL_WRITE 4
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#define MIU_TA_CTL_BUSY 8
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#define MIU_TEST_AGT_ADDR_LO (0x04)
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#define MIU_TEST_AGT_ADDR_HI (0x08)
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#define MIU_TEST_AGT_WRDATA_LO (0x10)
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#define MIU_TEST_AGT_WRDATA_HI (0x14)
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#define MIU_TEST_AGT_WRDATA(i) (0x10+(4*(i)))
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#define MIU_TEST_AGT_RDDATA_LO (0x18)
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#define MIU_TEST_AGT_RDDATA_HI (0x1c)
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#define MIU_TEST_AGT_RDDATA(i) (0x18+(4*(i)))
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#define SIU_TEST_AGT_CTRL (0x060)
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#define SIU_TEST_AGT_ADDR_LO (0x064)
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#define SIU_TEST_AGT_ADDR_HI (0x078)
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#define SIU_TEST_AGT_WRDATA_LO (0x068)
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#define SIU_TEST_AGT_WRDATA_HI (0x06c)
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#define SIU_TEST_AGT_WRDATA(i) (0x068+(4*(i)))
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#define SIU_TEST_AGT_RDDATA_LO (0x070)
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#define SIU_TEST_AGT_RDDATA_HI (0x074)
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#define SIU_TEST_AGT_RDDATA(i) (0x070+(4*(i)))
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#define MIU_TEST_AGT_ADDR_MASK 0xfffffff8
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#define MIU_TEST_AGT_UPPER_ADDR(off) (0)
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#define SIU_TEST_AGT_ADDR_MASK 0x3ffff8
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#define SIU_TEST_AGT_UPPER_ADDR(off) ((off)>>22)
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/*
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* Register offsets for MS
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*/
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#define SIU_TEST_AGT_BASE (0x60)
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#define SIU_TEST_AGT_ADDR_LO (0x04)
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#define SIU_TEST_AGT_ADDR_HI (0x18)
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#define SIU_TEST_AGT_WRDATA_LO (0x08)
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#define SIU_TEST_AGT_WRDATA_HI (0x0c)
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#define SIU_TEST_AGT_WRDATA(i) (0x08+(4*(i)))
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#define SIU_TEST_AGT_RDDATA_LO (0x10)
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#define SIU_TEST_AGT_RDDATA_HI (0x14)
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#define SIU_TEST_AGT_RDDATA(i) (0x10+(4*(i)))
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#define SIU_TEST_AGT_ADDR_MASK 0x3ffff8
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#define SIU_TEST_AGT_UPPER_ADDR(off) ((off)>>22)
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/* XG Link status */
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#define XG_LINK_UP 0x10
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@ -1458,101 +1458,69 @@ netxen_nic_pci_set_window_2M(struct netxen_adapter *adapter,
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static int
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netxen_nic_pci_mem_write_128M(struct netxen_adapter *adapter,
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u64 off, void *data, int size)
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u64 off, u64 data)
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{
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unsigned long flags;
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int i, j, ret = 0, loop, sz[2], off0;
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uint32_t temp;
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uint64_t off8, tmpw, word[2] = {0, 0};
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int j, ret;
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u32 temp, off_lo, off_hi, addr_hi, data_hi, data_lo;
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void __iomem *mem_crb;
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if (size != 8)
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/* Only 64-bit aligned access */
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if (off & 7)
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return -EIO;
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/* P2 has different SIU and MIU test agent base addr */
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if (ADDR_IN_RANGE(off, NETXEN_ADDR_QDR_NET,
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NETXEN_ADDR_QDR_NET_MAX_P2)) {
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mem_crb = pci_base_offset(adapter, NETXEN_CRB_QDR_NET);
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mem_crb = pci_base_offset(adapter,
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NETXEN_CRB_QDR_NET+SIU_TEST_AGT_BASE);
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addr_hi = SIU_TEST_AGT_ADDR_HI;
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data_lo = SIU_TEST_AGT_WRDATA_LO;
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data_hi = SIU_TEST_AGT_WRDATA_HI;
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off_lo = off & SIU_TEST_AGT_ADDR_MASK;
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off_hi = SIU_TEST_AGT_UPPER_ADDR(off);
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goto correct;
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}
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if (ADDR_IN_RANGE(off, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
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mem_crb = pci_base_offset(adapter, NETXEN_CRB_DDR_NET);
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mem_crb = pci_base_offset(adapter,
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NETXEN_CRB_DDR_NET+MIU_TEST_AGT_BASE);
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addr_hi = MIU_TEST_AGT_ADDR_HI;
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data_lo = MIU_TEST_AGT_WRDATA_LO;
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data_hi = MIU_TEST_AGT_WRDATA_HI;
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off_lo = off & MIU_TEST_AGT_ADDR_MASK;
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off_hi = 0;
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goto correct;
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}
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return -EIO;
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correct:
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off8 = off & 0xfffffff8;
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off0 = off & 0x7;
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sz[0] = (size < (8 - off0)) ? size : (8 - off0);
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sz[1] = size - sz[0];
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loop = ((off0 + size - 1) >> 3) + 1;
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if ((size != 8) || (off0 != 0)) {
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for (i = 0; i < loop; i++) {
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if (adapter->pci_mem_read(adapter,
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off8 + (i << 3), &word[i], 8))
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return -1;
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}
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}
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switch (size) {
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case 1:
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tmpw = *((uint8_t *)data);
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break;
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case 2:
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tmpw = *((uint16_t *)data);
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break;
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case 4:
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tmpw = *((uint32_t *)data);
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break;
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case 8:
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default:
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tmpw = *((uint64_t *)data);
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break;
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}
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word[0] &= ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8));
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word[0] |= tmpw << (off0 * 8);
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if (loop == 2) {
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word[1] &= ~(~0ULL << (sz[1] * 8));
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word[1] |= tmpw >> (sz[0] * 8);
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}
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write_lock_irqsave(&adapter->adapter_lock, flags);
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netxen_nic_pci_change_crbwindow_128M(adapter, 0);
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for (i = 0; i < loop; i++) {
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writel((uint32_t)(off8 + (i << 3)),
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(mem_crb+MIU_TEST_AGT_ADDR_LO));
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writel(0,
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(mem_crb+MIU_TEST_AGT_ADDR_HI));
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writel(word[i] & 0xffffffff,
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(mem_crb+MIU_TEST_AGT_WRDATA_LO));
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writel((word[i] >> 32) & 0xffffffff,
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(mem_crb+MIU_TEST_AGT_WRDATA_HI));
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writel(MIU_TA_CTL_ENABLE|MIU_TA_CTL_WRITE,
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(mem_crb+MIU_TEST_AGT_CTRL));
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writel(MIU_TA_CTL_START|MIU_TA_CTL_ENABLE|MIU_TA_CTL_WRITE,
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(mem_crb+MIU_TEST_AGT_CTRL));
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writel(off_lo, (mem_crb + MIU_TEST_AGT_ADDR_LO));
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writel(off_hi, (mem_crb + addr_hi));
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writel(data & 0xffffffff, (mem_crb + data_lo));
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writel((data >> 32) & 0xffffffff, (mem_crb + data_hi));
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writel((TA_CTL_ENABLE | TA_CTL_WRITE), (mem_crb + TEST_AGT_CTRL));
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writel((TA_CTL_START | TA_CTL_ENABLE | TA_CTL_WRITE),
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(mem_crb + TEST_AGT_CTRL));
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for (j = 0; j < MAX_CTL_CHECK; j++) {
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temp = readl(
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(mem_crb+MIU_TEST_AGT_CTRL));
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if ((temp & MIU_TA_CTL_BUSY) == 0)
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break;
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}
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if (j >= MAX_CTL_CHECK) {
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if (printk_ratelimit())
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dev_err(&adapter->pdev->dev,
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"failed to write through agent\n");
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ret = -1;
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for (j = 0; j < MAX_CTL_CHECK; j++) {
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temp = readl((mem_crb + TEST_AGT_CTRL));
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if ((temp & TA_CTL_BUSY) == 0)
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break;
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}
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}
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if (j >= MAX_CTL_CHECK) {
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if (printk_ratelimit())
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dev_err(&adapter->pdev->dev,
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"failed to write through agent\n");
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ret = -EIO;
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} else
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ret = 0;
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netxen_nic_pci_change_crbwindow_128M(adapter, 1);
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write_unlock_irqrestore(&adapter->adapter_lock, flags);
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return ret;
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@ -1560,304 +1528,202 @@ correct:
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static int
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netxen_nic_pci_mem_read_128M(struct netxen_adapter *adapter,
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u64 off, void *data, int size)
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u64 off, u64 *data)
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{
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unsigned long flags;
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int i, j = 0, k, start, end, loop, sz[2], off0[2];
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uint32_t temp;
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uint64_t off8, val, word[2] = {0, 0};
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int j, ret;
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u32 temp, off_lo, off_hi, addr_hi, data_hi, data_lo;
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u64 val;
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void __iomem *mem_crb;
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if (size != 8)
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/* Only 64-bit aligned access */
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if (off & 7)
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return -EIO;
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/* P2 has different SIU and MIU test agent base addr */
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if (ADDR_IN_RANGE(off, NETXEN_ADDR_QDR_NET,
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NETXEN_ADDR_QDR_NET_MAX_P2)) {
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mem_crb = pci_base_offset(adapter, NETXEN_CRB_QDR_NET);
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mem_crb = pci_base_offset(adapter,
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NETXEN_CRB_QDR_NET+SIU_TEST_AGT_BASE);
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addr_hi = SIU_TEST_AGT_ADDR_HI;
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data_lo = SIU_TEST_AGT_RDDATA_LO;
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data_hi = SIU_TEST_AGT_RDDATA_HI;
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off_lo = off & SIU_TEST_AGT_ADDR_MASK;
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off_hi = SIU_TEST_AGT_UPPER_ADDR(off);
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goto correct;
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}
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if (ADDR_IN_RANGE(off, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
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mem_crb = pci_base_offset(adapter, NETXEN_CRB_DDR_NET);
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mem_crb = pci_base_offset(adapter,
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NETXEN_CRB_DDR_NET+MIU_TEST_AGT_BASE);
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addr_hi = MIU_TEST_AGT_ADDR_HI;
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data_lo = MIU_TEST_AGT_RDDATA_LO;
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data_hi = MIU_TEST_AGT_RDDATA_HI;
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off_lo = off & MIU_TEST_AGT_ADDR_MASK;
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off_hi = 0;
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goto correct;
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}
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return -EIO;
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correct:
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off8 = off & 0xfffffff8;
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off0[0] = off & 0x7;
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off0[1] = 0;
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sz[0] = (size < (8 - off0[0])) ? size : (8 - off0[0]);
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sz[1] = size - sz[0];
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loop = ((off0[0] + size - 1) >> 3) + 1;
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write_lock_irqsave(&adapter->adapter_lock, flags);
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netxen_nic_pci_change_crbwindow_128M(adapter, 0);
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for (i = 0; i < loop; i++) {
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writel((uint32_t)(off8 + (i << 3)),
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(mem_crb+MIU_TEST_AGT_ADDR_LO));
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writel(0,
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(mem_crb+MIU_TEST_AGT_ADDR_HI));
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writel(MIU_TA_CTL_ENABLE,
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(mem_crb+MIU_TEST_AGT_CTRL));
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writel(MIU_TA_CTL_START|MIU_TA_CTL_ENABLE,
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(mem_crb+MIU_TEST_AGT_CTRL));
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writel(off_lo, (mem_crb + MIU_TEST_AGT_ADDR_LO));
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writel(off_hi, (mem_crb + addr_hi));
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writel(TA_CTL_ENABLE, (mem_crb + TEST_AGT_CTRL));
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writel((TA_CTL_START|TA_CTL_ENABLE), (mem_crb + TEST_AGT_CTRL));
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for (j = 0; j < MAX_CTL_CHECK; j++) {
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temp = readl(
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(mem_crb+MIU_TEST_AGT_CTRL));
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if ((temp & MIU_TA_CTL_BUSY) == 0)
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break;
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}
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if (j >= MAX_CTL_CHECK) {
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if (printk_ratelimit())
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dev_err(&adapter->pdev->dev,
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"failed to read through agent\n");
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for (j = 0; j < MAX_CTL_CHECK; j++) {
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temp = readl(mem_crb + TEST_AGT_CTRL);
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if ((temp & TA_CTL_BUSY) == 0)
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break;
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}
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}
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start = off0[i] >> 2;
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end = (off0[i] + sz[i] - 1) >> 2;
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for (k = start; k <= end; k++) {
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word[i] |= ((uint64_t) readl(
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(mem_crb +
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MIU_TEST_AGT_RDDATA(k))) << (32*k));
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}
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if (j >= MAX_CTL_CHECK) {
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if (printk_ratelimit())
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dev_err(&adapter->pdev->dev,
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"failed to read through agent\n");
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ret = -EIO;
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} else {
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temp = readl(mem_crb + data_hi);
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val = ((u64)temp << 32);
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val |= readl(mem_crb + data_lo);
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*data = val;
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ret = 0;
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}
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netxen_nic_pci_change_crbwindow_128M(adapter, 1);
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write_unlock_irqrestore(&adapter->adapter_lock, flags);
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if (j >= MAX_CTL_CHECK)
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return -1;
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if (sz[0] == 8) {
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val = word[0];
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} else {
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val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) |
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((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8));
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}
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switch (size) {
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case 1:
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*(uint8_t *)data = val;
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break;
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case 2:
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*(uint16_t *)data = val;
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break;
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case 4:
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*(uint32_t *)data = val;
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break;
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case 8:
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*(uint64_t *)data = val;
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break;
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}
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return 0;
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return ret;
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}
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static int
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netxen_nic_pci_mem_write_2M(struct netxen_adapter *adapter,
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u64 off, void *data, int size)
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u64 off, u64 data)
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{
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int i, j, ret = 0, loop, sz[2], off0;
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uint32_t temp;
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uint64_t off8, tmpw, word[2] = {0, 0};
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unsigned long flags;
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int j, ret;
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u32 temp, off8;
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void __iomem *mem_crb;
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if (size != 8)
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/* Only 64-bit aligned access */
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if (off & 7)
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return -EIO;
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/* P3 onward, test agent base for MIU and SIU is same */
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if (ADDR_IN_RANGE(off, NETXEN_ADDR_QDR_NET,
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NETXEN_ADDR_QDR_NET_MAX_P3)) {
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mem_crb = netxen_get_ioaddr(adapter, NETXEN_CRB_QDR_NET);
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mem_crb = netxen_get_ioaddr(adapter,
|
||||
NETXEN_CRB_QDR_NET+MIU_TEST_AGT_BASE);
|
||||
goto correct;
|
||||
}
|
||||
|
||||
if (ADDR_IN_RANGE(off, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
|
||||
mem_crb = netxen_get_ioaddr(adapter, NETXEN_CRB_DDR_NET);
|
||||
mem_crb = netxen_get_ioaddr(adapter,
|
||||
NETXEN_CRB_DDR_NET+MIU_TEST_AGT_BASE);
|
||||
goto correct;
|
||||
}
|
||||
|
||||
return -EIO;
|
||||
|
||||
correct:
|
||||
off8 = off & 0xfffffff8;
|
||||
off0 = off & 0x7;
|
||||
sz[0] = (size < (8 - off0)) ? size : (8 - off0);
|
||||
sz[1] = size - sz[0];
|
||||
loop = ((off0 + size - 1) >> 3) + 1;
|
||||
off8 = off & MIU_TEST_AGT_ADDR_MASK;
|
||||
|
||||
if ((size != 8) || (off0 != 0)) {
|
||||
for (i = 0; i < loop; i++) {
|
||||
if (adapter->pci_mem_read(adapter,
|
||||
off8 + (i << 3), &word[i], 8))
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
write_lock_irqsave(&adapter->adapter_lock, flags);
|
||||
|
||||
switch (size) {
|
||||
case 1:
|
||||
tmpw = *((uint8_t *)data);
|
||||
break;
|
||||
case 2:
|
||||
tmpw = *((uint16_t *)data);
|
||||
break;
|
||||
case 4:
|
||||
tmpw = *((uint32_t *)data);
|
||||
break;
|
||||
case 8:
|
||||
default:
|
||||
tmpw = *((uint64_t *)data);
|
||||
break;
|
||||
}
|
||||
writel(off8, (mem_crb + MIU_TEST_AGT_ADDR_LO));
|
||||
writel(0, (mem_crb + MIU_TEST_AGT_ADDR_HI));
|
||||
writel(data & 0xffffffff, mem_crb + MIU_TEST_AGT_WRDATA_LO);
|
||||
writel((data >> 32) & 0xffffffff, mem_crb + MIU_TEST_AGT_WRDATA_HI);
|
||||
writel((TA_CTL_ENABLE | TA_CTL_WRITE), (mem_crb + TEST_AGT_CTRL));
|
||||
writel((TA_CTL_START | TA_CTL_ENABLE | TA_CTL_WRITE),
|
||||
(mem_crb + TEST_AGT_CTRL));
|
||||
|
||||
word[0] &= ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8));
|
||||
word[0] |= tmpw << (off0 * 8);
|
||||
|
||||
if (loop == 2) {
|
||||
word[1] &= ~(~0ULL << (sz[1] * 8));
|
||||
word[1] |= tmpw >> (sz[0] * 8);
|
||||
}
|
||||
|
||||
/*
|
||||
* don't lock here - write_wx gets the lock if each time
|
||||
* write_lock_irqsave(&adapter->adapter_lock, flags);
|
||||
* netxen_nic_pci_change_crbwindow_128M(adapter, 0);
|
||||
*/
|
||||
|
||||
for (i = 0; i < loop; i++) {
|
||||
writel(off8 + (i << 3), mem_crb+MIU_TEST_AGT_ADDR_LO);
|
||||
writel(0, mem_crb+MIU_TEST_AGT_ADDR_HI);
|
||||
writel(word[i] & 0xffffffff, mem_crb+MIU_TEST_AGT_WRDATA_LO);
|
||||
writel((word[i] >> 32) & 0xffffffff,
|
||||
mem_crb+MIU_TEST_AGT_WRDATA_HI);
|
||||
writel((MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE),
|
||||
mem_crb+MIU_TEST_AGT_CTRL);
|
||||
writel(MIU_TA_CTL_START | MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE,
|
||||
mem_crb+MIU_TEST_AGT_CTRL);
|
||||
|
||||
for (j = 0; j < MAX_CTL_CHECK; j++) {
|
||||
temp = readl(mem_crb + MIU_TEST_AGT_CTRL);
|
||||
if ((temp & MIU_TA_CTL_BUSY) == 0)
|
||||
break;
|
||||
}
|
||||
|
||||
if (j >= MAX_CTL_CHECK) {
|
||||
if (printk_ratelimit())
|
||||
dev_err(&adapter->pdev->dev,
|
||||
"failed to write through agent\n");
|
||||
ret = -1;
|
||||
for (j = 0; j < MAX_CTL_CHECK; j++) {
|
||||
temp = readl(mem_crb + TEST_AGT_CTRL);
|
||||
if ((temp & TA_CTL_BUSY) == 0)
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* netxen_nic_pci_change_crbwindow_128M(adapter, 1);
|
||||
* write_unlock_irqrestore(&adapter->adapter_lock, flags);
|
||||
*/
|
||||
if (j >= MAX_CTL_CHECK) {
|
||||
if (printk_ratelimit())
|
||||
dev_err(&adapter->pdev->dev,
|
||||
"failed to write through agent\n");
|
||||
ret = -EIO;
|
||||
} else
|
||||
ret = 0;
|
||||
|
||||
write_unlock_irqrestore(&adapter->adapter_lock, flags);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int
|
||||
netxen_nic_pci_mem_read_2M(struct netxen_adapter *adapter,
|
||||
u64 off, void *data, int size)
|
||||
u64 off, u64 *data)
|
||||
{
|
||||
int i, j = 0, k, start, end, loop, sz[2], off0[2];
|
||||
uint32_t temp;
|
||||
uint64_t off8, val, word[2] = {0, 0};
|
||||
unsigned long flags;
|
||||
int j, ret;
|
||||
u32 temp, off8;
|
||||
u64 val;
|
||||
void __iomem *mem_crb;
|
||||
|
||||
if (size != 8)
|
||||
/* Only 64-bit aligned access */
|
||||
if (off & 7)
|
||||
return -EIO;
|
||||
|
||||
/* P3 onward, test agent base for MIU and SIU is same */
|
||||
if (ADDR_IN_RANGE(off, NETXEN_ADDR_QDR_NET,
|
||||
NETXEN_ADDR_QDR_NET_MAX_P3)) {
|
||||
mem_crb = netxen_get_ioaddr(adapter, NETXEN_CRB_QDR_NET);
|
||||
mem_crb = netxen_get_ioaddr(adapter,
|
||||
NETXEN_CRB_QDR_NET+MIU_TEST_AGT_BASE);
|
||||
goto correct;
|
||||
}
|
||||
|
||||
if (ADDR_IN_RANGE(off, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
|
||||
mem_crb = netxen_get_ioaddr(adapter, NETXEN_CRB_DDR_NET);
|
||||
mem_crb = netxen_get_ioaddr(adapter,
|
||||
NETXEN_CRB_DDR_NET+MIU_TEST_AGT_BASE);
|
||||
goto correct;
|
||||
}
|
||||
|
||||
return -EIO;
|
||||
|
||||
correct:
|
||||
off8 = off & 0xfffffff8;
|
||||
off0[0] = off & 0x7;
|
||||
off0[1] = 0;
|
||||
sz[0] = (size < (8 - off0[0])) ? size : (8 - off0[0]);
|
||||
sz[1] = size - sz[0];
|
||||
loop = ((off0[0] + size - 1) >> 3) + 1;
|
||||
off8 = off & MIU_TEST_AGT_ADDR_MASK;
|
||||
|
||||
/*
|
||||
* don't lock here - write_wx gets the lock if each time
|
||||
* write_lock_irqsave(&adapter->adapter_lock, flags);
|
||||
* netxen_nic_pci_change_crbwindow_128M(adapter, 0);
|
||||
*/
|
||||
write_lock_irqsave(&adapter->adapter_lock, flags);
|
||||
|
||||
for (i = 0; i < loop; i++) {
|
||||
writel(off8 + (i << 3), mem_crb + MIU_TEST_AGT_ADDR_LO);
|
||||
writel(0, mem_crb + MIU_TEST_AGT_ADDR_HI);
|
||||
writel(MIU_TA_CTL_ENABLE, mem_crb + MIU_TEST_AGT_CTRL);
|
||||
writel(MIU_TA_CTL_START | MIU_TA_CTL_ENABLE,
|
||||
mem_crb + MIU_TEST_AGT_CTRL);
|
||||
writel(off8, (mem_crb + MIU_TEST_AGT_ADDR_LO));
|
||||
writel(0, (mem_crb + MIU_TEST_AGT_ADDR_HI));
|
||||
writel(TA_CTL_ENABLE, (mem_crb + TEST_AGT_CTRL));
|
||||
writel((TA_CTL_START | TA_CTL_ENABLE), (mem_crb + TEST_AGT_CTRL));
|
||||
|
||||
for (j = 0; j < MAX_CTL_CHECK; j++) {
|
||||
temp = readl(mem_crb + MIU_TEST_AGT_CTRL);
|
||||
if ((temp & MIU_TA_CTL_BUSY) == 0)
|
||||
break;
|
||||
}
|
||||
|
||||
if (j >= MAX_CTL_CHECK) {
|
||||
if (printk_ratelimit())
|
||||
dev_err(&adapter->pdev->dev,
|
||||
"failed to read through agent\n");
|
||||
for (j = 0; j < MAX_CTL_CHECK; j++) {
|
||||
temp = readl(mem_crb + TEST_AGT_CTRL);
|
||||
if ((temp & TA_CTL_BUSY) == 0)
|
||||
break;
|
||||
}
|
||||
|
||||
start = off0[i] >> 2;
|
||||
end = (off0[i] + sz[i] - 1) >> 2;
|
||||
for (k = start; k <= end; k++) {
|
||||
temp = readl(mem_crb + MIU_TEST_AGT_RDDATA(k));
|
||||
word[i] |= ((uint64_t)temp << (32 * k));
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* netxen_nic_pci_change_crbwindow_128M(adapter, 1);
|
||||
* write_unlock_irqrestore(&adapter->adapter_lock, flags);
|
||||
*/
|
||||
|
||||
if (j >= MAX_CTL_CHECK)
|
||||
return -1;
|
||||
|
||||
if (sz[0] == 8) {
|
||||
val = word[0];
|
||||
if (j >= MAX_CTL_CHECK) {
|
||||
if (printk_ratelimit())
|
||||
dev_err(&adapter->pdev->dev,
|
||||
"failed to read through agent\n");
|
||||
ret = -EIO;
|
||||
} else {
|
||||
val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) |
|
||||
((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8));
|
||||
temp = readl(mem_crb + MIU_TEST_AGT_RDDATA_HI);
|
||||
val = (u64)temp << 32;
|
||||
val |= readl(mem_crb + MIU_TEST_AGT_RDDATA_LO);
|
||||
*data = val;
|
||||
ret = 0;
|
||||
}
|
||||
|
||||
switch (size) {
|
||||
case 1:
|
||||
*(uint8_t *)data = val;
|
||||
break;
|
||||
case 2:
|
||||
*(uint16_t *)data = val;
|
||||
break;
|
||||
case 4:
|
||||
*(uint32_t *)data = val;
|
||||
break;
|
||||
case 8:
|
||||
*(uint64_t *)data = val;
|
||||
break;
|
||||
}
|
||||
return 0;
|
||||
write_unlock_irqrestore(&adapter->adapter_lock, flags);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
void
|
||||
|
|
|
|||
|
|
@ -702,7 +702,10 @@ netxen_load_firmware(struct netxen_adapter *adapter)
|
|||
|
||||
for (i = 0; i < size; i++) {
|
||||
data = cpu_to_le64(ptr64[i]);
|
||||
adapter->pci_mem_write(adapter, flashaddr, &data, 8);
|
||||
if (adapter->pci_mem_write(adapter,
|
||||
flashaddr, data))
|
||||
return -EIO;
|
||||
|
||||
flashaddr += 8;
|
||||
}
|
||||
|
||||
|
|
@ -716,7 +719,7 @@ netxen_load_firmware(struct netxen_adapter *adapter)
|
|||
data = cpu_to_le64(ptr64[i]);
|
||||
|
||||
if (adapter->pci_mem_write(adapter,
|
||||
flashaddr, &data, 8))
|
||||
flashaddr, data))
|
||||
return -EIO;
|
||||
|
||||
flashaddr += 8;
|
||||
|
|
@ -730,17 +733,17 @@ netxen_load_firmware(struct netxen_adapter *adapter)
|
|||
|
||||
for (i = 0; i < size; i++) {
|
||||
if (netxen_rom_fast_read(adapter,
|
||||
flashaddr, &lo) != 0)
|
||||
flashaddr, (int *)&lo) != 0)
|
||||
return -EIO;
|
||||
if (netxen_rom_fast_read(adapter,
|
||||
flashaddr + 4, &hi) != 0)
|
||||
flashaddr + 4, (int *)&hi) != 0)
|
||||
return -EIO;
|
||||
|
||||
/* hi, lo are already in host endian byteorder */
|
||||
data = (((u64)hi << 32) | lo);
|
||||
|
||||
if (adapter->pci_mem_write(adapter,
|
||||
flashaddr, &data, 8))
|
||||
flashaddr, data))
|
||||
return -EIO;
|
||||
|
||||
flashaddr += 8;
|
||||
|
|
|
|||
Loading…
Reference in New Issue