clk: uniphier: Add SCSSI clock gate for each channel
SCSSI has clock gates for each channel in the SoCs newer than Pro4,
so this adds missing clock gates for channel 1, 2 and 3. And more, this
moves MCSSI clock ID after SCSSI.
Fixes: ff388ee365
("clk: uniphier: add clock frequency support for SPI")
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Link: https://lkml.kernel.org/r/1577410925-22021-1-git-send-email-hayashi.kunihiko@socionext.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
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@ -18,8 +18,8 @@
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#define UNIPHIER_PERI_CLK_FI2C(idx, ch) \
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UNIPHIER_CLK_GATE("i2c" #ch, (idx), "i2c", 0x24, 24 + (ch))
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#define UNIPHIER_PERI_CLK_SCSSI(idx) \
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UNIPHIER_CLK_GATE("scssi", (idx), "spi", 0x20, 17)
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#define UNIPHIER_PERI_CLK_SCSSI(idx, ch) \
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UNIPHIER_CLK_GATE("scssi" #ch, (idx), "spi", 0x20, 17 + (ch))
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#define UNIPHIER_PERI_CLK_MCSSI(idx) \
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UNIPHIER_CLK_GATE("mcssi", (idx), "spi", 0x24, 14)
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@ -35,7 +35,7 @@ const struct uniphier_clk_data uniphier_ld4_peri_clk_data[] = {
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UNIPHIER_PERI_CLK_I2C(6, 2),
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UNIPHIER_PERI_CLK_I2C(7, 3),
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UNIPHIER_PERI_CLK_I2C(8, 4),
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UNIPHIER_PERI_CLK_SCSSI(11),
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UNIPHIER_PERI_CLK_SCSSI(11, 0),
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{ /* sentinel */ }
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};
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@ -51,7 +51,10 @@ const struct uniphier_clk_data uniphier_pro4_peri_clk_data[] = {
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UNIPHIER_PERI_CLK_FI2C(8, 4),
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UNIPHIER_PERI_CLK_FI2C(9, 5),
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UNIPHIER_PERI_CLK_FI2C(10, 6),
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UNIPHIER_PERI_CLK_SCSSI(11),
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UNIPHIER_PERI_CLK_MCSSI(12),
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UNIPHIER_PERI_CLK_SCSSI(11, 0),
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UNIPHIER_PERI_CLK_SCSSI(12, 1),
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UNIPHIER_PERI_CLK_SCSSI(13, 2),
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UNIPHIER_PERI_CLK_SCSSI(14, 3),
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UNIPHIER_PERI_CLK_MCSSI(15),
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{ /* sentinel */ }
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};
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