Merge branch 'for-john' of git://git.kernel.org/pub/scm/linux/kernel/git/iwlwifi/iwlwifi-next
Conflicts: drivers/net/wireless/iwlwifi/pcie/trans.c
This commit is contained in:
John W. Linville
commit
1e60896fe0
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@ -168,8 +168,13 @@ int iwlagn_mac_setup_register(struct iwl_priv *priv,
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hw->flags |= IEEE80211_HW_SUPPORTS_DYNAMIC_SMPS |
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IEEE80211_HW_SUPPORTS_STATIC_SMPS;
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/* enable 11w if the uCode advertise */
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if (capa->flags & IWL_UCODE_TLV_FLAGS_MFP)
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/*
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* Enable 11w if advertised by firmware and software crypto
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* is not enabled (as the firmware will interpret some mgmt
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* packets, so enabling it with software crypto isn't safe)
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*/
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if (priv->fw->ucode_capa.flags & IWL_UCODE_TLV_FLAGS_MFP &&
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!iwlwifi_mod_params.sw_crypto)
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hw->flags |= IEEE80211_HW_MFP_CAPABLE;
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hw->sta_data_size = sizeof(struct iwl_station_priv);
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@ -1191,8 +1191,6 @@ static void iwl_option_config(struct iwl_priv *priv)
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static int iwl_eeprom_init_hw_params(struct iwl_priv *priv)
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{
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priv->eeprom_data->sku = priv->eeprom_data->sku;
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if (priv->eeprom_data->sku & EEPROM_SKU_CAP_11N_ENABLE &&
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!priv->cfg->ht_params) {
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IWL_ERR(priv, "Invalid 11n configuration\n");
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@ -150,7 +150,7 @@ enum iwl_led_mode {
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struct iwl_base_params {
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int eeprom_size;
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int num_of_queues; /* def: HW dependent */
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/* for iwl_apm_init() */
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/* for iwl_pcie_apm_init() */
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u32 pll_cfg_val;
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const u16 max_ll_items;
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@ -267,7 +267,7 @@ static inline unsigned int FH_MEM_CBBC_QUEUE(unsigned int chnl)
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#define FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS (20)
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#define FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS (4)
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#define RX_RB_TIMEOUT (0x10)
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#define RX_RB_TIMEOUT (0x11)
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#define FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_VAL (0x00000000)
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#define FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_EOF_VAL (0x40000000)
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@ -69,7 +69,6 @@
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#include "iwl-trans.h"
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#include "iwl-drv.h"
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#include "iwl-trans.h"
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#include "cfg.h"
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#include "internal.h"
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@ -73,7 +73,7 @@ struct isr_statistics {
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};
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/**
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* struct iwl_rx_queue - Rx queue
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* struct iwl_rxq - Rx queue
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* @bd: driver's pointer to buffer of receive buffer descriptors (rbd)
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* @bd_dma: bus address of buffer of receive buffer descriptors (rbd)
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* @pool:
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@ -91,7 +91,7 @@ struct isr_statistics {
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*
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* NOTE: rx_free and rx_used are used as a FIFO for iwl_rx_mem_buffers
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*/
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struct iwl_rx_queue {
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struct iwl_rxq {
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__le32 *bd;
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dma_addr_t bd_dma;
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struct iwl_rx_mem_buffer pool[RX_QUEUE_SIZE + RX_FREE_BUFFERS];
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@ -157,8 +157,8 @@ struct iwl_cmd_meta {
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* 32 since we don't need so many commands pending. Since the HW
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* still uses 256 BDs for DMA though, n_bd stays 256. As a result,
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* the software buffers (in the variables @meta, @txb in struct
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* iwl_tx_queue) only have 32 entries, while the HW buffers (@tfds
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* in the same struct) have 256.
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* iwl_txq) only have 32 entries, while the HW buffers (@tfds in
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* the same struct) have 256.
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* This means that we end up with the following:
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* HW entries: | 0 | ... | N * 32 | ... | N * 32 + 31 | ... | 255 |
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* SW entries: | 0 | ... | 31 |
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@ -182,7 +182,7 @@ struct iwl_queue {
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#define TFD_TX_CMD_SLOTS 256
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#define TFD_CMD_SLOTS 32
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struct iwl_pcie_tx_queue_entry {
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struct iwl_pcie_txq_entry {
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struct iwl_device_cmd *cmd;
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struct iwl_device_cmd *copy_cmd;
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struct sk_buff *skb;
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@ -192,7 +192,7 @@ struct iwl_pcie_tx_queue_entry {
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};
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/**
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* struct iwl_tx_queue - Tx Queue for DMA
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* struct iwl_txq - Tx Queue for DMA
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* @q: generic Rx/Tx queue descriptor
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* @tfds: transmit frame descriptors (DMA memory)
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* @entries: transmit entries (driver state)
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@ -205,10 +205,10 @@ struct iwl_pcie_tx_queue_entry {
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* A Tx queue consists of circular buffer of BDs (a.k.a. TFDs, transmit frame
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* descriptors) and required locking structures.
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*/
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struct iwl_tx_queue {
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struct iwl_txq {
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struct iwl_queue q;
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struct iwl_tfd *tfds;
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struct iwl_pcie_tx_queue_entry *entries;
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struct iwl_pcie_txq_entry *entries;
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spinlock_t lock;
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struct timer_list stuck_timer;
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struct iwl_trans_pcie *trans_pcie;
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@ -238,7 +238,7 @@ struct iwl_tx_queue {
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* @wd_timeout: queue watchdog timeout (jiffies)
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*/
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struct iwl_trans_pcie {
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struct iwl_rx_queue rxq;
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struct iwl_rxq rxq;
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struct work_struct rx_replenish;
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struct iwl_trans *trans;
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struct iwl_drv *drv;
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@ -260,7 +260,7 @@ struct iwl_trans_pcie {
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struct iwl_dma_ptr scd_bc_tbls;
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struct iwl_dma_ptr kw;
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struct iwl_tx_queue *txq;
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struct iwl_txq *txq;
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unsigned long queue_used[BITS_TO_LONGS(IWL_MAX_HW_QUEUES)];
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unsigned long queue_stopped[BITS_TO_LONGS(IWL_MAX_HW_QUEUES)];
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@ -287,10 +287,16 @@ struct iwl_trans_pcie {
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unsigned long wd_timeout;
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};
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/*****************************************************
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* DRIVER STATUS FUNCTIONS
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******************************************************/
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enum {
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/**
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* enum iwl_pcie_status: status of the PCIe transport
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* @STATUS_HCMD_ACTIVE: a SYNC command is being processed
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* @STATUS_DEVICE_ENABLED: APM is enabled
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* @STATUS_TPOWER_PMI: the device might be asleep (need to wake it up)
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* @STATUS_INT_ENABLED: interrupts are enabled
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* @STATUS_RFKILL: the HW RFkill switch is in KILL position
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* @STATUS_FW_ERROR: the fw is in error state
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*/
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enum iwl_pcie_status {
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STATUS_HCMD_ACTIVE,
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STATUS_DEVICE_ENABLED,
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STATUS_TPOWER_PMI,
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@ -309,6 +315,10 @@ iwl_trans_pcie_get_trans(struct iwl_trans_pcie *trans_pcie)
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trans_specific);
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}
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/*
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* Convention: trans API functions: iwl_trans_pcie_XXX
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* Other functions: iwl_pcie_XXX
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*/
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struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
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const struct pci_device_id *ent,
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const struct iwl_cfg *cfg);
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@ -317,51 +327,43 @@ void iwl_trans_pcie_free(struct iwl_trans *trans);
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/*****************************************************
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* RX
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******************************************************/
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void iwl_bg_rx_replenish(struct work_struct *data);
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void iwl_irq_tasklet(struct iwl_trans *trans);
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void iwl_rx_replenish(struct iwl_trans *trans);
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void iwl_rx_queue_update_write_ptr(struct iwl_trans *trans,
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struct iwl_rx_queue *q);
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int iwl_pcie_rx_init(struct iwl_trans *trans);
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void iwl_pcie_tasklet(struct iwl_trans *trans);
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int iwl_pcie_rx_stop(struct iwl_trans *trans);
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void iwl_pcie_rx_free(struct iwl_trans *trans);
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/*****************************************************
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* ICT
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* ICT - interrupt handling
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******************************************************/
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void iwl_reset_ict(struct iwl_trans *trans);
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void iwl_disable_ict(struct iwl_trans *trans);
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int iwl_alloc_isr_ict(struct iwl_trans *trans);
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void iwl_free_isr_ict(struct iwl_trans *trans);
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irqreturn_t iwl_isr_ict(int irq, void *data);
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irqreturn_t iwl_pcie_isr_ict(int irq, void *data);
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int iwl_pcie_alloc_ict(struct iwl_trans *trans);
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void iwl_pcie_free_ict(struct iwl_trans *trans);
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void iwl_pcie_reset_ict(struct iwl_trans *trans);
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void iwl_pcie_disable_ict(struct iwl_trans *trans);
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/*****************************************************
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* TX / HCMD
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******************************************************/
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void iwl_txq_update_write_ptr(struct iwl_trans *trans,
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struct iwl_tx_queue *txq);
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int iwlagn_txq_attach_buf_to_tfd(struct iwl_trans *trans,
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struct iwl_tx_queue *txq,
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dma_addr_t addr, u16 len, u8 reset);
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int iwl_queue_init(struct iwl_queue *q, int count, int slots_num, u32 id);
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int iwl_trans_pcie_send_cmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd);
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void iwl_tx_cmd_complete(struct iwl_trans *trans,
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struct iwl_rx_cmd_buffer *rxb, int handler_status);
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void iwl_trans_txq_update_byte_cnt_tbl(struct iwl_trans *trans,
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struct iwl_tx_queue *txq,
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u16 byte_cnt);
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int iwl_pcie_tx_init(struct iwl_trans *trans);
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void iwl_pcie_tx_start(struct iwl_trans *trans, u32 scd_base_addr);
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int iwl_pcie_tx_stop(struct iwl_trans *trans);
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void iwl_pcie_tx_free(struct iwl_trans *trans);
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void iwl_trans_pcie_txq_enable(struct iwl_trans *trans, int txq_id, int fifo,
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int sta_id, int tid, int frame_limit, u16 ssn);
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void iwl_trans_pcie_txq_disable(struct iwl_trans *trans, int queue);
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void iwl_txq_free_tfd(struct iwl_trans *trans, struct iwl_tx_queue *txq,
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enum dma_data_direction dma_dir);
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int iwl_tx_queue_reclaim(struct iwl_trans *trans, int txq_id, int index,
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struct sk_buff_head *skbs);
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void iwl_tx_queue_unmap(struct iwl_trans *trans, int txq_id);
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int iwl_queue_space(const struct iwl_queue *q);
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int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb,
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struct iwl_device_cmd *dev_cmd, int txq_id);
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void iwl_pcie_txq_inc_wr_ptr(struct iwl_trans *trans, struct iwl_txq *txq);
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int iwl_trans_pcie_send_hcmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd);
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void iwl_pcie_hcmd_complete(struct iwl_trans *trans,
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struct iwl_rx_cmd_buffer *rxb, int handler_status);
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void iwl_trans_pcie_reclaim(struct iwl_trans *trans, int txq_id, int ssn,
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struct sk_buff_head *skbs);
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/*****************************************************
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* Error handling
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******************************************************/
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int iwl_dump_fh(struct iwl_trans *trans, char **buf);
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void iwl_dump_csr(struct iwl_trans *trans);
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int iwl_pcie_dump_fh(struct iwl_trans *trans, char **buf);
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void iwl_pcie_dump_csr(struct iwl_trans *trans);
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/*****************************************************
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* Helpers
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@ -397,7 +399,7 @@ static inline void iwl_enable_rfkill_int(struct iwl_trans *trans)
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}
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static inline void iwl_wake_queue(struct iwl_trans *trans,
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struct iwl_tx_queue *txq)
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struct iwl_txq *txq)
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{
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struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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@ -408,7 +410,7 @@ static inline void iwl_wake_queue(struct iwl_trans *trans,
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}
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static inline void iwl_stop_queue(struct iwl_trans *trans,
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struct iwl_tx_queue *txq)
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struct iwl_txq *txq)
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{
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struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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@ -420,7 +422,7 @@ static inline void iwl_stop_queue(struct iwl_trans *trans,
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txq->q.id);
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}
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static inline int iwl_queue_used(const struct iwl_queue *q, int i)
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static inline bool iwl_queue_used(const struct iwl_queue *q, int i)
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{
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return q->write_ptr >= q->read_ptr ?
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(i >= q->read_ptr && i < q->write_ptr) :
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@ -432,8 +434,8 @@ static inline u8 get_cmd_index(struct iwl_queue *q, u32 index)
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return index & (q->n_window - 1);
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}
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static inline const char *
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trans_pcie_get_cmd_string(struct iwl_trans_pcie *trans_pcie, u8 cmd)
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static inline const char *get_cmd_string(struct iwl_trans_pcie *trans_pcie,
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u8 cmd)
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{
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if (!trans_pcie->command_names || !trans_pcie->command_names[cmd])
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return "UNKNOWN";
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|
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@ -76,7 +76,7 @@
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* + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When
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* iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
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* to replenish the iwl->rxq->rx_free.
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* + In iwl_rx_replenish (scheduled) if 'processed' != 'read' then the
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* + In iwl_pcie_rx_replenish (scheduled) if 'processed' != 'read' then the
|
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* iwl->rxq is replenished and the READ INDEX is updated (updating the
|
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* 'processed' and 'read' driver indexes as well)
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* + A received packet is processed and handed to the kernel network stack,
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@ -89,28 +89,28 @@
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*
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* Driver sequence:
|
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*
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* iwl_rx_queue_alloc() Allocates rx_free
|
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* iwl_rx_replenish() Replenishes rx_free list from rx_used, and calls
|
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* iwl_rx_queue_restock
|
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* iwl_rx_queue_restock() Moves available buffers from rx_free into Rx
|
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* iwl_rxq_alloc() Allocates rx_free
|
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* iwl_pcie_rx_replenish() Replenishes rx_free list from rx_used, and calls
|
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* iwl_pcie_rxq_restock
|
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* iwl_pcie_rxq_restock() Moves available buffers from rx_free into Rx
|
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* queue, updates firmware pointers, and updates
|
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* the WRITE index. If insufficient rx_free buffers
|
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* are available, schedules iwl_rx_replenish
|
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* are available, schedules iwl_pcie_rx_replenish
|
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*
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* -- enable interrupts --
|
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* ISR - iwl_rx() Detach iwl_rx_mem_buffers from pool up to the
|
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* ISR - iwl_rx() Detach iwl_rx_mem_buffers from pool up to the
|
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* READ INDEX, detaching the SKB from the pool.
|
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* Moves the packet buffer from queue to rx_used.
|
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* Calls iwl_rx_queue_restock to refill any empty
|
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* Calls iwl_pcie_rxq_restock to refill any empty
|
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* slots.
|
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* ...
|
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*
|
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*/
|
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|
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/**
|
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* iwl_rx_queue_space - Return number of free slots available in queue.
|
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/*
|
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* iwl_rxq_space - Return number of free slots available in queue.
|
||||
*/
|
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static int iwl_rx_queue_space(const struct iwl_rx_queue *q)
|
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static int iwl_rxq_space(const struct iwl_rxq *q)
|
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{
|
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int s = q->read - q->write;
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if (s <= 0)
|
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|
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@ -122,11 +122,28 @@ static int iwl_rx_queue_space(const struct iwl_rx_queue *q)
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return s;
|
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}
|
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|
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/**
|
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* iwl_rx_queue_update_write_ptr - Update the write pointer for the RX queue
|
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/*
|
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* iwl_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
|
||||
*/
|
||||
void iwl_rx_queue_update_write_ptr(struct iwl_trans *trans,
|
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struct iwl_rx_queue *q)
|
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static inline __le32 iwl_pcie_dma_addr2rbd_ptr(dma_addr_t dma_addr)
|
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{
|
||||
return cpu_to_le32((u32)(dma_addr >> 8));
|
||||
}
|
||||
|
||||
/*
|
||||
* iwl_pcie_rx_stop - stops the Rx DMA
|
||||
*/
|
||||
int iwl_pcie_rx_stop(struct iwl_trans *trans)
|
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{
|
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iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
|
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return iwl_poll_direct_bit(trans, FH_MEM_RSSR_RX_STATUS_REG,
|
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FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
|
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}
|
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|
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/*
|
||||
* iwl_pcie_rxq_inc_wr_ptr - Update the write pointer for the RX queue
|
||||
*/
|
||||
static void iwl_pcie_rxq_inc_wr_ptr(struct iwl_trans *trans, struct iwl_rxq *q)
|
||||
{
|
||||
unsigned long flags;
|
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u32 reg;
|
||||
|
|
@ -176,16 +193,8 @@ void iwl_rx_queue_update_write_ptr(struct iwl_trans *trans,
|
|||
spin_unlock_irqrestore(&q->lock, flags);
|
||||
}
|
||||
|
||||
/**
|
||||
* iwl_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
|
||||
*/
|
||||
static inline __le32 iwl_dma_addr2rbd_ptr(dma_addr_t dma_addr)
|
||||
{
|
||||
return cpu_to_le32((u32)(dma_addr >> 8));
|
||||
}
|
||||
|
||||
/**
|
||||
* iwl_rx_queue_restock - refill RX queue from pre-allocated pool
|
||||
/*
|
||||
* iwl_pcie_rxq_restock - refill RX queue from pre-allocated pool
|
||||
*
|
||||
* If there are slots in the RX queue that need to be restocked,
|
||||
* and we have free pre-allocated buffers, fill the ranks as much
|
||||
|
|
@ -195,10 +204,10 @@ static inline __le32 iwl_dma_addr2rbd_ptr(dma_addr_t dma_addr)
|
|||
* also updates the memory address in the firmware to reference the new
|
||||
* target buffer.
|
||||
*/
|
||||
static void iwl_rx_queue_restock(struct iwl_trans *trans)
|
||||
static void iwl_pcie_rxq_restock(struct iwl_trans *trans)
|
||||
{
|
||||
struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
|
||||
struct iwl_rx_queue *rxq = &trans_pcie->rxq;
|
||||
struct iwl_rxq *rxq = &trans_pcie->rxq;
|
||||
struct iwl_rx_mem_buffer *rxb;
|
||||
unsigned long flags;
|
||||
|
||||
|
|
@ -214,7 +223,7 @@ static void iwl_rx_queue_restock(struct iwl_trans *trans)
|
|||
return;
|
||||
|
||||
spin_lock_irqsave(&rxq->lock, flags);
|
||||
while ((iwl_rx_queue_space(rxq) > 0) && (rxq->free_count)) {
|
||||
while ((iwl_rxq_space(rxq) > 0) && (rxq->free_count)) {
|
||||
/* The overwritten rxb must be a used one */
|
||||
rxb = rxq->queue[rxq->write];
|
||||
BUG_ON(rxb && rxb->page);
|
||||
|
|
@ -225,7 +234,7 @@ static void iwl_rx_queue_restock(struct iwl_trans *trans)
|
|||
list_del(&rxb->list);
|
||||
|
||||
/* Point to Rx buffer via next RBD in circular buffer */
|
||||
rxq->bd[rxq->write] = iwl_dma_addr2rbd_ptr(rxb->page_dma);
|
||||
rxq->bd[rxq->write] = iwl_pcie_dma_addr2rbd_ptr(rxb->page_dma);
|
||||
rxq->queue[rxq->write] = rxb;
|
||||
rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
|
||||
rxq->free_count--;
|
||||
|
|
@ -242,23 +251,23 @@ static void iwl_rx_queue_restock(struct iwl_trans *trans)
|
|||
spin_lock_irqsave(&rxq->lock, flags);
|
||||
rxq->need_update = 1;
|
||||
spin_unlock_irqrestore(&rxq->lock, flags);
|
||||
iwl_rx_queue_update_write_ptr(trans, rxq);
|
||||
iwl_pcie_rxq_inc_wr_ptr(trans, rxq);
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* iwl_rx_allocate - allocate a page for each used RBD
|
||||
* iwl_pcie_rxq_alloc_rbs - allocate a page for each used RBD
|
||||
*
|
||||
* A used RBD is an Rx buffer that has been given to the stack. To use it again
|
||||
* a page must be allocated and the RBD must point to the page. This function
|
||||
* doesn't change the HW pointer but handles the list of pages that is used by
|
||||
* iwl_rx_queue_restock. The latter function will update the HW to use the newly
|
||||
* iwl_pcie_rxq_restock. The latter function will update the HW to use the newly
|
||||
* allocated buffers.
|
||||
*/
|
||||
static void iwl_rx_allocate(struct iwl_trans *trans, gfp_t priority)
|
||||
static void iwl_pcie_rxq_alloc_rbs(struct iwl_trans *trans, gfp_t priority)
|
||||
{
|
||||
struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
|
||||
struct iwl_rx_queue *rxq = &trans_pcie->rxq;
|
||||
struct iwl_rxq *rxq = &trans_pcie->rxq;
|
||||
struct iwl_rx_mem_buffer *rxb;
|
||||
struct page *page;
|
||||
unsigned long flags;
|
||||
|
|
@ -340,47 +349,227 @@ static void iwl_rx_allocate(struct iwl_trans *trans, gfp_t priority)
|
|||
}
|
||||
}
|
||||
|
||||
static void iwl_pcie_rxq_free_rbs(struct iwl_trans *trans)
|
||||
{
|
||||
struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
|
||||
struct iwl_rxq *rxq = &trans_pcie->rxq;
|
||||
int i;
|
||||
|
||||
/* Fill the rx_used queue with _all_ of the Rx buffers */
|
||||
for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
|
||||
/* In the reset function, these buffers may have been allocated
|
||||
* to an SKB, so we need to unmap and free potential storage */
|
||||
if (rxq->pool[i].page != NULL) {
|
||||
dma_unmap_page(trans->dev, rxq->pool[i].page_dma,
|
||||
PAGE_SIZE << trans_pcie->rx_page_order,
|
||||
DMA_FROM_DEVICE);
|
||||
__free_pages(rxq->pool[i].page,
|
||||
trans_pcie->rx_page_order);
|
||||
rxq->pool[i].page = NULL;
|
||||
}
|
||||
list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* iwl_rx_replenish - Move all used buffers from rx_used to rx_free
|
||||
* iwl_pcie_rx_replenish - Move all used buffers from rx_used to rx_free
|
||||
*
|
||||
* When moving to rx_free an page is allocated for the slot.
|
||||
*
|
||||
* Also restock the Rx queue via iwl_rx_queue_restock.
|
||||
* Also restock the Rx queue via iwl_pcie_rxq_restock.
|
||||
* This is called as a scheduled work item (except for during initialization)
|
||||
*/
|
||||
void iwl_rx_replenish(struct iwl_trans *trans)
|
||||
static void iwl_pcie_rx_replenish(struct iwl_trans *trans)
|
||||
{
|
||||
struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
|
||||
unsigned long flags;
|
||||
|
||||
iwl_rx_allocate(trans, GFP_KERNEL);
|
||||
iwl_pcie_rxq_alloc_rbs(trans, GFP_KERNEL);
|
||||
|
||||
spin_lock_irqsave(&trans_pcie->irq_lock, flags);
|
||||
iwl_rx_queue_restock(trans);
|
||||
iwl_pcie_rxq_restock(trans);
|
||||
spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
|
||||
}
|
||||
|
||||
static void iwl_rx_replenish_now(struct iwl_trans *trans)
|
||||
static void iwl_pcie_rx_replenish_now(struct iwl_trans *trans)
|
||||
{
|
||||
iwl_rx_allocate(trans, GFP_ATOMIC);
|
||||
iwl_pcie_rxq_alloc_rbs(trans, GFP_ATOMIC);
|
||||
|
||||
iwl_rx_queue_restock(trans);
|
||||
iwl_pcie_rxq_restock(trans);
|
||||
}
|
||||
|
||||
void iwl_bg_rx_replenish(struct work_struct *data)
|
||||
static void iwl_pcie_rx_replenish_work(struct work_struct *data)
|
||||
{
|
||||
struct iwl_trans_pcie *trans_pcie =
|
||||
container_of(data, struct iwl_trans_pcie, rx_replenish);
|
||||
|
||||
iwl_rx_replenish(trans_pcie->trans);
|
||||
iwl_pcie_rx_replenish(trans_pcie->trans);
|
||||
}
|
||||
|
||||
static void iwl_rx_handle_rxbuf(struct iwl_trans *trans,
|
||||
static int iwl_pcie_rx_alloc(struct iwl_trans *trans)
|
||||
{
|
||||
struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
|
||||
struct iwl_rxq *rxq = &trans_pcie->rxq;
|
||||
struct device *dev = trans->dev;
|
||||
|
||||
memset(&trans_pcie->rxq, 0, sizeof(trans_pcie->rxq));
|
||||
|
||||
spin_lock_init(&rxq->lock);
|
||||
|
||||
if (WARN_ON(rxq->bd || rxq->rb_stts))
|
||||
return -EINVAL;
|
||||
|
||||
/* Allocate the circular buffer of Read Buffer Descriptors (RBDs) */
|
||||
rxq->bd = dma_zalloc_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE,
|
||||
&rxq->bd_dma, GFP_KERNEL);
|
||||
if (!rxq->bd)
|
||||
goto err_bd;
|
||||
|
||||
/*Allocate the driver's pointer to receive buffer status */
|
||||
rxq->rb_stts = dma_zalloc_coherent(dev, sizeof(*rxq->rb_stts),
|
||||
&rxq->rb_stts_dma, GFP_KERNEL);
|
||||
if (!rxq->rb_stts)
|
||||
goto err_rb_stts;
|
||||
|
||||
return 0;
|
||||
|
||||
err_rb_stts:
|
||||
dma_free_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE,
|
||||
rxq->bd, rxq->bd_dma);
|
||||
memset(&rxq->bd_dma, 0, sizeof(rxq->bd_dma));
|
||||
rxq->bd = NULL;
|
||||
err_bd:
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
static void iwl_pcie_rx_hw_init(struct iwl_trans *trans, struct iwl_rxq *rxq)
|
||||
{
|
||||
struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
|
||||
u32 rb_size;
|
||||
const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */
|
||||
|
||||
if (trans_pcie->rx_buf_size_8k)
|
||||
rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
|
||||
else
|
||||
rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
|
||||
|
||||
/* Stop Rx DMA */
|
||||
iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
|
||||
|
||||
/* Reset driver's Rx queue write index */
|
||||
iwl_write_direct32(trans, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
|
||||
|
||||
/* Tell device where to find RBD circular buffer in DRAM */
|
||||
iwl_write_direct32(trans, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
|
||||
(u32)(rxq->bd_dma >> 8));
|
||||
|
||||
/* Tell device where in DRAM to update its Rx status */
|
||||
iwl_write_direct32(trans, FH_RSCSR_CHNL0_STTS_WPTR_REG,
|
||||
rxq->rb_stts_dma >> 4);
|
||||
|
||||
/* Enable Rx DMA
|
||||
* FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in
|
||||
* the credit mechanism in 5000 HW RX FIFO
|
||||
* Direct rx interrupts to hosts
|
||||
* Rx buffer size 4 or 8k
|
||||
* RB timeout 0x10
|
||||
* 256 RBDs
|
||||
*/
|
||||
iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG,
|
||||
FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
|
||||
FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY |
|
||||
FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
|
||||
rb_size|
|
||||
(RX_RB_TIMEOUT << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS)|
|
||||
(rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS));
|
||||
|
||||
/* Set interrupt coalescing timer to default (2048 usecs) */
|
||||
iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);
|
||||
}
|
||||
|
||||
int iwl_pcie_rx_init(struct iwl_trans *trans)
|
||||
{
|
||||
struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
|
||||
struct iwl_rxq *rxq = &trans_pcie->rxq;
|
||||
|
||||
int i, err;
|
||||
unsigned long flags;
|
||||
|
||||
if (!rxq->bd) {
|
||||
err = iwl_pcie_rx_alloc(trans);
|
||||
if (err)
|
||||
return err;
|
||||
}
|
||||
|
||||
spin_lock_irqsave(&rxq->lock, flags);
|
||||
INIT_LIST_HEAD(&rxq->rx_free);
|
||||
INIT_LIST_HEAD(&rxq->rx_used);
|
||||
|
||||
INIT_WORK(&trans_pcie->rx_replenish,
|
||||
iwl_pcie_rx_replenish_work);
|
||||
|
||||
iwl_pcie_rxq_free_rbs(trans);
|
||||
|
||||
for (i = 0; i < RX_QUEUE_SIZE; i++)
|
||||
rxq->queue[i] = NULL;
|
||||
|
||||
/* Set us so that we have processed and used all buffers, but have
|
||||
* not restocked the Rx queue with fresh buffers */
|
||||
rxq->read = rxq->write = 0;
|
||||
rxq->write_actual = 0;
|
||||
rxq->free_count = 0;
|
||||
spin_unlock_irqrestore(&rxq->lock, flags);
|
||||
|
||||
iwl_pcie_rx_replenish(trans);
|
||||
|
||||
iwl_pcie_rx_hw_init(trans, rxq);
|
||||
|
||||
spin_lock_irqsave(&trans_pcie->irq_lock, flags);
|
||||
rxq->need_update = 1;
|
||||
iwl_pcie_rxq_inc_wr_ptr(trans, rxq);
|
||||
spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void iwl_pcie_rx_free(struct iwl_trans *trans)
|
||||
{
|
||||
struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
|
||||
struct iwl_rxq *rxq = &trans_pcie->rxq;
|
||||
unsigned long flags;
|
||||
|
||||
/*if rxq->bd is NULL, it means that nothing has been allocated,
|
||||
* exit now */
|
||||
if (!rxq->bd) {
|
||||
IWL_DEBUG_INFO(trans, "Free NULL rx context\n");
|
||||
return;
|
||||
}
|
||||
|
||||
spin_lock_irqsave(&rxq->lock, flags);
|
||||
iwl_pcie_rxq_free_rbs(trans);
|
||||
spin_unlock_irqrestore(&rxq->lock, flags);
|
||||
|
||||
dma_free_coherent(trans->dev, sizeof(__le32) * RX_QUEUE_SIZE,
|
||||
rxq->bd, rxq->bd_dma);
|
||||
memset(&rxq->bd_dma, 0, sizeof(rxq->bd_dma));
|
||||
rxq->bd = NULL;
|
||||
|
||||
if (rxq->rb_stts)
|
||||
dma_free_coherent(trans->dev,
|
||||
sizeof(struct iwl_rb_status),
|
||||
rxq->rb_stts, rxq->rb_stts_dma);
|
||||
else
|
||||
IWL_DEBUG_INFO(trans, "Free rxq->rb_stts which is NULL\n");
|
||||
memset(&rxq->rb_stts_dma, 0, sizeof(rxq->rb_stts_dma));
|
||||
rxq->rb_stts = NULL;
|
||||
}
|
||||
|
||||
static void iwl_pcie_rx_handle_rb(struct iwl_trans *trans,
|
||||
struct iwl_rx_mem_buffer *rxb)
|
||||
{
|
||||
struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
|
||||
struct iwl_rx_queue *rxq = &trans_pcie->rxq;
|
||||
struct iwl_tx_queue *txq = &trans_pcie->txq[trans_pcie->cmd_queue];
|
||||
struct iwl_rxq *rxq = &trans_pcie->rxq;
|
||||
struct iwl_txq *txq = &trans_pcie->txq[trans_pcie->cmd_queue];
|
||||
unsigned long flags;
|
||||
bool page_stolen = false;
|
||||
int max_len = PAGE_SIZE << trans_pcie->rx_page_order;
|
||||
|
|
@ -410,8 +599,7 @@ static void iwl_rx_handle_rxbuf(struct iwl_trans *trans,
|
|||
break;
|
||||
|
||||
IWL_DEBUG_RX(trans, "cmd at offset %d: %s (0x%.2x)\n",
|
||||
rxcb._offset,
|
||||
trans_pcie_get_cmd_string(trans_pcie, pkt->hdr.cmd),
|
||||
rxcb._offset, get_cmd_string(trans_pcie, pkt->hdr.cmd),
|
||||
pkt->hdr.cmd);
|
||||
|
||||
len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
|
||||
|
|
@ -443,7 +631,7 @@ static void iwl_rx_handle_rxbuf(struct iwl_trans *trans,
|
|||
cmd_index = get_cmd_index(&txq->q, index);
|
||||
|
||||
if (reclaim) {
|
||||
struct iwl_pcie_tx_queue_entry *ent;
|
||||
struct iwl_pcie_txq_entry *ent;
|
||||
ent = &txq->entries[cmd_index];
|
||||
cmd = ent->copy_cmd;
|
||||
WARN_ON_ONCE(!cmd && ent->meta.flags & CMD_WANT_HCMD);
|
||||
|
|
@ -473,7 +661,7 @@ static void iwl_rx_handle_rxbuf(struct iwl_trans *trans,
|
|||
* iwl_trans_send_cmd()
|
||||
* as we reclaim the driver command queue */
|
||||
if (!rxcb._page_stolen)
|
||||
iwl_tx_cmd_complete(trans, &rxcb, err);
|
||||
iwl_pcie_hcmd_complete(trans, &rxcb, err);
|
||||
else
|
||||
IWL_WARN(trans, "Claim null rxb?\n");
|
||||
}
|
||||
|
|
@ -515,17 +703,13 @@ static void iwl_rx_handle_rxbuf(struct iwl_trans *trans,
|
|||
spin_unlock_irqrestore(&rxq->lock, flags);
|
||||
}
|
||||
|
||||
/**
|
||||
* iwl_rx_handle - Main entry function for receiving responses from uCode
|
||||
*
|
||||
* Uses the priv->rx_handlers callback function array to invoke
|
||||
* the appropriate handlers, including command responses,
|
||||
* frame-received notifications, and other notifications.
|
||||
/*
|
||||
* iwl_pcie_rx_handle - Main entry function for receiving responses from fw
|
||||
*/
|
||||
static void iwl_rx_handle(struct iwl_trans *trans)
|
||||
static void iwl_pcie_rx_handle(struct iwl_trans *trans)
|
||||
{
|
||||
struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
|
||||
struct iwl_rx_queue *rxq = &trans_pcie->rxq;
|
||||
struct iwl_rxq *rxq = &trans_pcie->rxq;
|
||||
u32 r, i;
|
||||
u8 fill_rx = 0;
|
||||
u32 count = 8;
|
||||
|
|
@ -556,7 +740,7 @@ static void iwl_rx_handle(struct iwl_trans *trans)
|
|||
|
||||
IWL_DEBUG_RX(trans, "rxbuf: HW = %d, SW = %d (%p)\n",
|
||||
r, i, rxb);
|
||||
iwl_rx_handle_rxbuf(trans, rxb);
|
||||
iwl_pcie_rx_handle_rb(trans, rxb);
|
||||
|
||||
i = (i + 1) & RX_QUEUE_MASK;
|
||||
/* If there are a lot of unused frames,
|
||||
|
|
@ -565,7 +749,7 @@ static void iwl_rx_handle(struct iwl_trans *trans)
|
|||
count++;
|
||||
if (count >= 8) {
|
||||
rxq->read = i;
|
||||
iwl_rx_replenish_now(trans);
|
||||
iwl_pcie_rx_replenish_now(trans);
|
||||
count = 0;
|
||||
}
|
||||
}
|
||||
|
|
@ -574,15 +758,15 @@ static void iwl_rx_handle(struct iwl_trans *trans)
|
|||
/* Backtrack one entry */
|
||||
rxq->read = i;
|
||||
if (fill_rx)
|
||||
iwl_rx_replenish_now(trans);
|
||||
iwl_pcie_rx_replenish_now(trans);
|
||||
else
|
||||
iwl_rx_queue_restock(trans);
|
||||
iwl_pcie_rxq_restock(trans);
|
||||
}
|
||||
|
||||
/**
|
||||
* iwl_irq_handle_error - called for HW or SW error interrupt from card
|
||||
/*
|
||||
* iwl_pcie_irq_handle_error - called for HW or SW error interrupt from card
|
||||
*/
|
||||
static void iwl_irq_handle_error(struct iwl_trans *trans)
|
||||
static void iwl_pcie_irq_handle_error(struct iwl_trans *trans)
|
||||
{
|
||||
struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
|
||||
|
||||
|
|
@ -598,8 +782,8 @@ static void iwl_irq_handle_error(struct iwl_trans *trans)
|
|||
return;
|
||||
}
|
||||
|
||||
iwl_dump_csr(trans);
|
||||
iwl_dump_fh(trans, NULL);
|
||||
iwl_pcie_dump_csr(trans);
|
||||
iwl_pcie_dump_fh(trans, NULL);
|
||||
|
||||
set_bit(STATUS_FW_ERROR, &trans_pcie->status);
|
||||
clear_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status);
|
||||
|
|
@ -608,8 +792,7 @@ static void iwl_irq_handle_error(struct iwl_trans *trans)
|
|||
iwl_op_mode_nic_error(trans->op_mode);
|
||||
}
|
||||
|
||||
/* tasklet for iwlagn interrupt */
|
||||
void iwl_irq_tasklet(struct iwl_trans *trans)
|
||||
void iwl_pcie_tasklet(struct iwl_trans *trans)
|
||||
{
|
||||
struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
|
||||
struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
|
||||
|
|
@ -661,7 +844,7 @@ void iwl_irq_tasklet(struct iwl_trans *trans)
|
|||
iwl_disable_interrupts(trans);
|
||||
|
||||
isr_stats->hw++;
|
||||
iwl_irq_handle_error(trans);
|
||||
iwl_pcie_irq_handle_error(trans);
|
||||
|
||||
handled |= CSR_INT_BIT_HW_ERR;
|
||||
|
||||
|
|
@ -724,17 +907,16 @@ void iwl_irq_tasklet(struct iwl_trans *trans)
|
|||
IWL_ERR(trans, "Microcode SW error detected. "
|
||||
" Restarting 0x%X.\n", inta);
|
||||
isr_stats->sw++;
|
||||
iwl_irq_handle_error(trans);
|
||||
iwl_pcie_irq_handle_error(trans);
|
||||
handled |= CSR_INT_BIT_SW_ERR;
|
||||
}
|
||||
|
||||
/* uCode wakes up after power-down sleep */
|
||||
if (inta & CSR_INT_BIT_WAKEUP) {
|
||||
IWL_DEBUG_ISR(trans, "Wakeup interrupt\n");
|
||||
iwl_rx_queue_update_write_ptr(trans, &trans_pcie->rxq);
|
||||
iwl_pcie_rxq_inc_wr_ptr(trans, &trans_pcie->rxq);
|
||||
for (i = 0; i < trans->cfg->base_params->num_of_queues; i++)
|
||||
iwl_txq_update_write_ptr(trans,
|
||||
&trans_pcie->txq[i]);
|
||||
iwl_pcie_txq_inc_wr_ptr(trans, &trans_pcie->txq[i]);
|
||||
|
||||
isr_stats->wakeup++;
|
||||
|
||||
|
|
@ -772,7 +954,7 @@ void iwl_irq_tasklet(struct iwl_trans *trans)
|
|||
iwl_write8(trans, CSR_INT_PERIODIC_REG,
|
||||
CSR_INT_PERIODIC_DIS);
|
||||
|
||||
iwl_rx_handle(trans);
|
||||
iwl_pcie_rx_handle(trans);
|
||||
|
||||
/*
|
||||
* Enable periodic interrupt in 8 msec only if we received
|
||||
|
|
@ -830,7 +1012,7 @@ void iwl_irq_tasklet(struct iwl_trans *trans)
|
|||
#define ICT_COUNT (ICT_SIZE / sizeof(u32))
|
||||
|
||||
/* Free dram table */
|
||||
void iwl_free_isr_ict(struct iwl_trans *trans)
|
||||
void iwl_pcie_free_ict(struct iwl_trans *trans)
|
||||
{
|
||||
struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
|
||||
|
||||
|
|
@ -843,13 +1025,12 @@ void iwl_free_isr_ict(struct iwl_trans *trans)
|
|||
}
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* allocate dram shared table, it is an aligned memory
|
||||
* block of ICT_SIZE.
|
||||
* also reset all data related to ICT table interrupt.
|
||||
*/
|
||||
int iwl_alloc_isr_ict(struct iwl_trans *trans)
|
||||
int iwl_pcie_alloc_ict(struct iwl_trans *trans)
|
||||
{
|
||||
struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
|
||||
|
||||
|
|
@ -862,7 +1043,7 @@ int iwl_alloc_isr_ict(struct iwl_trans *trans)
|
|||
|
||||
/* just an API sanity check ... it is guaranteed to be aligned */
|
||||
if (WARN_ON(trans_pcie->ict_tbl_dma & (ICT_SIZE - 1))) {
|
||||
iwl_free_isr_ict(trans);
|
||||
iwl_pcie_free_ict(trans);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
|
|
@ -883,7 +1064,7 @@ int iwl_alloc_isr_ict(struct iwl_trans *trans)
|
|||
/* Device is going up inform it about using ICT interrupt table,
|
||||
* also we need to tell the driver to start using ICT interrupt.
|
||||
*/
|
||||
void iwl_reset_ict(struct iwl_trans *trans)
|
||||
void iwl_pcie_reset_ict(struct iwl_trans *trans)
|
||||
{
|
||||
struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
|
||||
u32 val;
|
||||
|
|
@ -913,7 +1094,7 @@ void iwl_reset_ict(struct iwl_trans *trans)
|
|||
}
|
||||
|
||||
/* Device is going down disable ict interrupt usage */
|
||||
void iwl_disable_ict(struct iwl_trans *trans)
|
||||
void iwl_pcie_disable_ict(struct iwl_trans *trans)
|
||||
{
|
||||
struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
|
||||
unsigned long flags;
|
||||
|
|
@ -924,7 +1105,7 @@ void iwl_disable_ict(struct iwl_trans *trans)
|
|||
}
|
||||
|
||||
/* legacy (non-ICT) ISR. Assumes that trans_pcie->irq_lock is held */
|
||||
static irqreturn_t iwl_isr(int irq, void *data)
|
||||
static irqreturn_t iwl_pcie_isr(int irq, void *data)
|
||||
{
|
||||
struct iwl_trans *trans = data;
|
||||
struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
|
||||
|
|
@ -971,7 +1152,7 @@ static irqreturn_t iwl_isr(int irq, void *data)
|
|||
#endif
|
||||
|
||||
trans_pcie->inta |= inta;
|
||||
/* iwl_irq_tasklet() will service interrupts and re-enable them */
|
||||
/* iwl_pcie_tasklet() will service interrupts and re-enable them */
|
||||
if (likely(inta))
|
||||
tasklet_schedule(&trans_pcie->irq_tasklet);
|
||||
else if (test_bit(STATUS_INT_ENABLED, &trans_pcie->status) &&
|
||||
|
|
@ -996,7 +1177,7 @@ none:
|
|||
* the interrupt we need to service, driver will set the entries back to 0 and
|
||||
* set index.
|
||||
*/
|
||||
irqreturn_t iwl_isr_ict(int irq, void *data)
|
||||
irqreturn_t iwl_pcie_isr_ict(int irq, void *data)
|
||||
{
|
||||
struct iwl_trans *trans = data;
|
||||
struct iwl_trans_pcie *trans_pcie;
|
||||
|
|
@ -1016,14 +1197,13 @@ irqreturn_t iwl_isr_ict(int irq, void *data)
|
|||
* use legacy interrupt.
|
||||
*/
|
||||
if (unlikely(!trans_pcie->use_ict)) {
|
||||
irqreturn_t ret = iwl_isr(irq, data);
|
||||
irqreturn_t ret = iwl_pcie_isr(irq, data);
|
||||
spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
|
||||
return ret;
|
||||
}
|
||||
|
||||
trace_iwlwifi_dev_irq(trans->dev);
|
||||
|
||||
|
||||
/* Disable (but don't clear!) interrupts here to avoid
|
||||
* back-to-back ISRs and sporadic interrupts from our NIC.
|
||||
* If we have something to service, the tasklet will re-enable ints.
|
||||
|
|
@ -1032,7 +1212,6 @@ irqreturn_t iwl_isr_ict(int irq, void *data)
|
|||
inta_mask = iwl_read32(trans, CSR_INT_MASK); /* just for debug */
|
||||
iwl_write32(trans, CSR_INT_MASK, 0x00000000);
|
||||
|
||||
|
||||
/* Ignore interrupt if there's nothing in NIC to service.
|
||||
* This may be due to IRQ shared with another device,
|
||||
* or due to sporadic interrupts thrown from our NIC. */
|
||||
|
|
@ -1081,7 +1260,7 @@ irqreturn_t iwl_isr_ict(int irq, void *data)
|
|||
inta &= trans_pcie->inta_mask;
|
||||
trans_pcie->inta |= inta;
|
||||
|
||||
/* iwl_irq_tasklet() will service interrupts and re-enable them */
|
||||
/* iwl_pcie_tasklet() will service interrupts and re-enable them */
|
||||
if (likely(inta))
|
||||
tasklet_schedule(&trans_pcie->irq_tasklet);
|
||||
else if (test_bit(STATUS_INT_ENABLED, &trans_pcie->status) &&
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue