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dt-bindings: Misc fix for the ATH79 DDR controllers 

Fix a few typos and reword the description of the
'#qca,ddr-wb-channel-cells' property.

Signed-off-by: Alban Bedel <albeu@free.fr>
CC: trivial@kernel.org
Signed-off-by: Rob Herring <robh@kernel.org>
This commit is contained in:
Alban Bedel 2015-11-29 13:40:12 +01:00 committed by Rob Herring
parent ef8322427e
commit 1da2f213cf
1 changed files with 4 additions and 4 deletions
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8
Documentation/devicetree/bindings/memory-controllers/ath79-ddr-controller.txt
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@ -1,6 +1,6 @@
Binding for Qualcomm Atheros AR7xxx/AR9xxx DDR controller Binding for Qualcomm Atheros AR7xxx/AR9xxx DDR controller
The DDR controller of the ARxxx and AR9xxx families provides an interface The DDR controller of the AR7xxx and AR9xxx families provides an interface
to flush the FIFO between various devices and the DDR. This is mainly used to flush the FIFO between various devices and the DDR. This is mainly used
by the IRQ controller to flush the FIFO before running the interrupt handler by the IRQ controller to flush the FIFO before running the interrupt handler
of such devices. of such devices.
@ -11,9 +11,9 @@ Required properties:
"qca,[ar7100|ar7240]-ddr-controller" as fallback. "qca,[ar7100|ar7240]-ddr-controller" as fallback.
On SoC with PCI support "qca,ar7100-ddr-controller" should be used as On SoC with PCI support "qca,ar7100-ddr-controller" should be used as
fallback, otherwise "qca,ar7240-ddr-controller" should be used. fallback, otherwise "qca,ar7240-ddr-controller" should be used.
- reg: Base address and size of the controllers memory area - reg: Base address and size of the controller's memory area
- #qca,ddr-wb-channel-cells: has to be 1, the index of the write buffer - #qca,ddr-wb-channel-cells: Specifies the number of cells needed to encode
channel the write buffer channel index, should be 1.
Example: Example: