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[MIPS] Kill duplicated setup_irq() for cp0 timer 

Also many plat_timer_setup() can be killed too.

Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Atsushi Nemoto 2007-10-20 01:26:25 +09:00 committed by Ralf Baechle
parent d527eef5b7
commit 1d9ef3ecd7
11 changed files with 0 additions and 82 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
arch/mips/bcm47xx/time.c
View File

@ -46,10 +46,3 @@ void __init plat_time_init(void)
/* Set MIPS counter frequency for fixed_rate_gettimeoffset() */
mips_hpt_frequency = hz;
}
void __init
plat_timer_setup(struct irqaction *irq)
{
/* Enable the timer interrupt */
setup_irq(7, irq);
}

6
arch/mips/emma2rh/markeins/setup.c
View File

@ -104,12 +104,6 @@ void __init plat_time_init(void)
mips_hpt_frequency = (bus_frequency * (4 + reg)) / 4 / 2;
}
void __init plat_timer_setup(struct irqaction *irq)
{
/* we are using the cpu counter for timer interrupts */
setup_irq(CPU_IRQ_BASE + 7, irq);
}
static void markeins_board_init(void);
extern void markeins_irq_setup(void);

5
arch/mips/lemote/lm2e/setup.c
View File

@ -53,11 +53,6 @@ unsigned long bus_clock;
unsigned int memsize;
unsigned int highmemsize = 0;
void __init plat_timer_setup(struct irqaction *irq)
{
setup_irq(MIPS_CPU_IRQ_BASE + 7, irq);
}
void __init plat_time_init(void)
{
/* setup mips r4k timer */

3
arch/mips/pmc-sierra/msp71xx/msp_time.c
View File

@ -86,8 +86,5 @@ void __init plat_timer_setup(struct irqaction *irq)
#ifdef CONFIG_IRQ_MSP_CIC
/* we are using the vpe0 counter for timer interrupts */
setup_irq(MSP_INT_VPE0_TIMER, irq);
#else
/* we are using the mips counter for timer interrupts */
setup_irq(MSP_INT_TIMER, irq);
#endif
}

5
arch/mips/pmc-sierra/yosemite/setup.c
View File

@ -137,11 +137,6 @@ int rtc_mips_set_time(unsigned long tim)
return 0;
}
void __init plat_timer_setup(struct irqaction *irq)
{
setup_irq(7, irq);
}
void __init plat_time_init(void)
{
mips_hpt_frequency = cpu_clock_freq / 2;

18
arch/mips/sni/time.c
View File

@ -121,15 +121,6 @@ void __init plat_time_init(void)
setup_pit_timer();
}
/*
* R4k counter based timer interrupt. Works on RM200-225 and possibly
* others but not on RM400
*/
static void __init sni_cpu_timer_setup(struct irqaction *irq)
{
setup_irq(SNI_MIPS_IRQ_CPU_TIMER, irq);
}
void __init plat_timer_setup(struct irqaction *irq)
{
switch (sni_brd_type) {
@ -139,15 +130,6 @@ void __init plat_timer_setup(struct irqaction *irq)
case SNI_BRD_MINITOWER:
sni_a20r_timer_setup(irq);
break;
case SNI_BRD_PCI_TOWER:
case SNI_BRD_RM200:
case SNI_BRD_PCI_MTOWER:
case SNI_BRD_PCI_DESKTOP:
case SNI_BRD_PCI_TOWER_CPLUS:
case SNI_BRD_PCI_MTOWER_CPLUS:
sni_cpu_timer_setup(irq);
break;
}
}

16
arch/mips/tx4927/common/tx4927_setup.c
View File

@ -72,22 +72,6 @@ void __init plat_time_init(void)
#endif
}
void __init plat_timer_setup(struct irqaction *irq)
{
setup_irq(TX4927_IRQ_CPU_TIMER, irq);
#ifdef CONFIG_TOSHIBA_RBTX4927
{
extern void toshiba_rbtx4927_timer_setup(struct irqaction
*irq);
toshiba_rbtx4927_timer_setup(irq);
}
#endif
return;
}
#ifdef DEBUG
void print_cp0(char *key, int num, char *name, u32 val)
{

10
arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c
View File

@ -94,7 +94,6 @@
#define TOSHIBA_RBTX4927_SETUP_EFWFU ( 1 << 3 )
#define TOSHIBA_RBTX4927_SETUP_SETUP ( 1 << 4 )
#define TOSHIBA_RBTX4927_SETUP_TIME_INIT ( 1 << 5 )
#define TOSHIBA_RBTX4927_SETUP_TIMER_SETUP ( 1 << 6 )
#define TOSHIBA_RBTX4927_SETUP_PCIBIOS ( 1 << 7 )
#define TOSHIBA_RBTX4927_SETUP_PCI1 ( 1 << 8 )
#define TOSHIBA_RBTX4927_SETUP_PCI2 ( 1 << 9 )
@ -108,7 +107,6 @@ static const u32 toshiba_rbtx4927_setup_debug_flag =
(TOSHIBA_RBTX4927_SETUP_NONE | TOSHIBA_RBTX4927_SETUP_INFO |
TOSHIBA_RBTX4927_SETUP_WARN | TOSHIBA_RBTX4927_SETUP_EROR |
TOSHIBA_RBTX4927_SETUP_EFWFU | TOSHIBA_RBTX4927_SETUP_SETUP |
TOSHIBA_RBTX4927_SETUP_TIME_INIT | TOSHIBA_RBTX4927_SETUP_TIMER_SETUP
| TOSHIBA_RBTX4927_SETUP_PCIBIOS | TOSHIBA_RBTX4927_SETUP_PCI1 |
TOSHIBA_RBTX4927_SETUP_PCI2 | TOSHIBA_RBTX4927_SETUP_PCI66);
#endif
@ -947,14 +945,6 @@ toshiba_rbtx4927_time_init(void)
}
void __init toshiba_rbtx4927_timer_setup(struct irqaction *irq)
{
TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIMER_SETUP,
"-\n");
TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIMER_SETUP,
"+\n");
}
static int __init toshiba_rbtx4927_rtc_init(void)
{
static struct resource __initdata res = {

5
arch/mips/tx4938/common/setup.c
View File

@ -43,8 +43,3 @@ plat_mem_setup(void)
{
toshiba_rbtx4938_setup();
}
void __init plat_timer_setup(struct irqaction *irq)
{
setup_irq(TX4938_IRQ_CPU_TIMER, irq);
}

5
arch/mips/vr41xx/common/init.c
View File

@ -48,11 +48,6 @@ void __init plat_time_init(void)
mips_hpt_frequency = tclock / 4;
}
void __init plat_timer_setup(struct irqaction *irq)
{
setup_irq(TIMER_IRQ, irq);
}
void __init plat_mem_setup(void)
{
vr41xx_calculate_clock_frequency();

2
include/asm-mips/sni.h
View File

@ -141,8 +141,6 @@ extern unsigned int sni_brd_type;
#define A20R_PT_TIM0_ACK 0xbc050000
#define A20R_PT_TIM1_ACK 0xbc060000
#define SNI_MIPS_IRQ_CPU_TIMER (MIPS_CPU_IRQ_BASE+7)
#define SNI_A20R_IRQ_BASE MIPS_CPU_IRQ_BASE
#define SNI_A20R_IRQ_TIMER (SNI_A20R_IRQ_BASE+5)