clk: rockchip: remove deprecated gate-clk code and dt-binding
Initially we tried modeling clocks via the devicetree before switching to clocks declared in the clock drivers and only exporting specific ids to the devicetree. As the old code was in the kernel for 1-2 releases when the new mode of operation was added we kept it for backwards compatibility. That deprecation notice is in the binding since july 2014, so nearly 4 years now and I think it's time to drop the old cruft. Especially as at the time using the mainline kernel on Rockchip devices was not really possible, except for experiments on the really old socs of the rk3066 + rk3188 line, so there shouldn't be any devicetrees still around that rely on that code. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Stephen Boyd <sboyd@kernel.org> Reviewed-by: Rob Herring <robh@kernel.org>
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Heiko Stuebner
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a425702f68
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1d646229f2
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@ -1,77 +0,0 @@
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Device Tree Clock bindings for arch-rockchip
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This binding uses the common clock binding[1].
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[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
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== Gate clocks ==
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These bindings are deprecated!
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Please use the soc specific CRU bindings instead.
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The gate registers form a continuos block which makes the dt node
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structure a matter of taste, as either all gates can be put into
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one gate clock spanning all registers or they can be divided into
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the 10 individual gates containing 16 clocks each.
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The code supports both approaches.
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Required properties:
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- compatible : "rockchip,rk2928-gate-clk"
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- reg : shall be the control register address(es) for the clock.
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- #clock-cells : from common clock binding; shall be set to 1
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- clock-output-names : the corresponding gate names that the clock controls
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- clocks : should contain the parent clock for each individual gate,
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therefore the number of clocks elements should match the number of
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clock-output-names
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Example using multiple gate clocks:
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clk_gates0: gate-clk@200000d0 {
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compatible = "rockchip,rk2928-gate-clk";
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reg = <0x200000d0 0x4>;
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clocks = <&dummy>, <&dummy>,
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<&dummy>, <&dummy>,
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<&dummy>, <&dummy>,
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<&dummy>, <&dummy>,
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<&dummy>, <&dummy>,
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<&dummy>, <&dummy>,
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<&dummy>, <&dummy>,
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<&dummy>, <&dummy>;
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clock-output-names =
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"gate_core_periph", "gate_cpu_gpll",
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"gate_ddrphy", "gate_aclk_cpu",
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"gate_hclk_cpu", "gate_pclk_cpu",
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"gate_atclk_cpu", "gate_i2s0",
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"gate_i2s0_frac", "gate_i2s1",
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"gate_i2s1_frac", "gate_i2s2",
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"gate_i2s2_frac", "gate_spdif",
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"gate_spdif_frac", "gate_testclk";
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#clock-cells = <1>;
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};
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clk_gates1: gate-clk@200000d4 {
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compatible = "rockchip,rk2928-gate-clk";
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reg = <0x200000d4 0x4>;
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clocks = <&xin24m>, <&xin24m>,
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<&xin24m>, <&dummy>,
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<&dummy>, <&xin24m>,
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<&xin24m>, <&dummy>,
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<&xin24m>, <&dummy>,
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<&xin24m>, <&dummy>,
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<&xin24m>, <&dummy>,
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<&xin24m>, <&dummy>;
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clock-output-names =
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"gate_timer0", "gate_timer1",
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"gate_timer2", "gate_jtag",
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"gate_aclk_lcdc1_src", "gate_otgphy0",
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"gate_otgphy1", "gate_ddr_gpll",
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"gate_uart0", "gate_frac_uart0",
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"gate_uart1", "gate_frac_uart1",
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"gate_uart2", "gate_frac_uart2",
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"gate_uart3", "gate_frac_uart3";
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#clock-cells = <1>;
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};
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@ -3,7 +3,6 @@
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# Rockchip Clock specific Makefile
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#
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obj-y += clk-rockchip.o
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obj-y += clk.o
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obj-y += clk-pll.o
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obj-y += clk-cpu.o
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@ -1,98 +0,0 @@
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/*
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* Copyright (c) 2013 MundoReader S.L.
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* Author: Heiko Stuebner <heiko@sntech.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/clk-provider.h>
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#include <linux/clkdev.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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static DEFINE_SPINLOCK(clk_lock);
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/*
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* Gate clocks
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*/
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static void __init rk2928_gate_clk_init(struct device_node *node)
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{
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struct clk_onecell_data *clk_data;
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const char *clk_parent;
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const char *clk_name;
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void __iomem *reg;
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void __iomem *reg_idx;
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int flags;
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int qty;
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int reg_bit;
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int clkflags = CLK_SET_RATE_PARENT;
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int i;
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qty = of_property_count_strings(node, "clock-output-names");
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if (qty < 0) {
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pr_err("%s: error in clock-output-names %d\n", __func__, qty);
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return;
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}
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if (qty == 0) {
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pr_info("%s: nothing to do\n", __func__);
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return;
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}
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reg = of_iomap(node, 0);
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if (!reg)
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return;
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clk_data = kzalloc(sizeof(struct clk_onecell_data), GFP_KERNEL);
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if (!clk_data) {
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iounmap(reg);
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return;
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}
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clk_data->clks = kzalloc(qty * sizeof(struct clk *), GFP_KERNEL);
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if (!clk_data->clks) {
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kfree(clk_data);
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iounmap(reg);
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return;
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}
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flags = CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE;
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for (i = 0; i < qty; i++) {
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of_property_read_string_index(node, "clock-output-names",
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i, &clk_name);
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/* ignore empty slots */
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if (!strcmp("reserved", clk_name))
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continue;
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clk_parent = of_clk_get_parent_name(node, i);
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/* keep all gates untouched for now */
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clkflags |= CLK_IGNORE_UNUSED;
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reg_idx = reg + (4 * (i / 16));
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reg_bit = (i % 16);
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clk_data->clks[i] = clk_register_gate(NULL, clk_name,
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clk_parent, clkflags,
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reg_idx, reg_bit,
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flags,
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&clk_lock);
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WARN_ON(IS_ERR(clk_data->clks[i]));
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}
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clk_data->clk_num = qty;
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of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
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}
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CLK_OF_DECLARE(rk2928_gate, "rockchip,rk2928-gate-clk", rk2928_gate_clk_init);
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