ASoC: Add TI tlv320aic32x4 codec support.
This patch adds support for tlv320aic3205 and tlv320aic3254 codecs. It doesn't include miniDSP support for aic3254. Signed-off-by: Javier Martin <javier.martin@vista-silicon.com> Acked-by: Liam Girdwood <lrg@slimlogic.co.uk> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
This commit is contained in:
Javier Martin
Mark Brown
parent
28e9ad921d
commit
1d471cd126
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@ -0,0 +1,31 @@
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/*
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* tlv320aic32x4.h -- TLV320AIC32X4 Soc Audio driver platform data
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*
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* Copyright 2011 Vista Silicon S.L.
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*
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* Author: Javier Martin <javier.martin@vista-silicon.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef _AIC32X4_PDATA_H
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#define _AIC32X4_PDATA_H
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#define AIC32X4_PWR_MICBIAS_2075_LDOIN 0x00000001
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#define AIC32X4_PWR_AVDD_DVDD_WEAK_DISABLE 0x00000002
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#define AIC32X4_PWR_AIC32X4_LDO_ENABLE 0x00000004
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#define AIC32X4_PWR_CMMODE_LDOIN_RANGE_18_36 0x00000008
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#define AIC32X4_PWR_CMMODE_HP_LDOIN_POWERED 0x00000010
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#define AIC32X4_MICPGA_ROUTE_LMIC_IN2R_10K 0x00000001
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#define AIC32X4_MICPGA_ROUTE_RMIC_IN1L_10K 0x00000002
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struct aic32x4_pdata {
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u32 power_cfg;
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u32 micpga_routing;
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bool swapdacs;
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};
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#endif
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@ -40,6 +40,7 @@ config SND_SOC_ALL_CODECS
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select SND_SOC_STAC9766 if SND_SOC_AC97_BUS
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select SND_SOC_TLV320AIC23 if I2C
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select SND_SOC_TLV320AIC26 if SPI_MASTER
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select SND_SOC_TVL320AIC32X4 if I2C
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select SND_SOC_TLV320AIC3X if I2C
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select SND_SOC_TPA6130A2 if I2C
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select SND_SOC_TLV320DAC33 if I2C
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@ -206,6 +207,9 @@ config SND_SOC_TLV320AIC26
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tristate "TI TLV320AIC26 Codec support" if SND_SOC_OF_SIMPLE
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depends on SPI
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config SND_SOC_TVL320AIC32X4
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tristate
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config SND_SOC_TLV320AIC3X
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tristate
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@ -28,6 +28,7 @@ snd-soc-stac9766-objs := stac9766.o
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snd-soc-tlv320aic23-objs := tlv320aic23.o
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snd-soc-tlv320aic26-objs := tlv320aic26.o
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snd-soc-tlv320aic3x-objs := tlv320aic3x.o
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snd-soc-tlv320aic32x4-objs := tlv320aic32x4.o
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snd-soc-tlv320dac33-objs := tlv320dac33.o
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snd-soc-twl4030-objs := twl4030.o
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snd-soc-twl6040-objs := twl6040.o
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@ -112,6 +113,7 @@ obj-$(CONFIG_SND_SOC_STAC9766) += snd-soc-stac9766.o
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obj-$(CONFIG_SND_SOC_TLV320AIC23) += snd-soc-tlv320aic23.o
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obj-$(CONFIG_SND_SOC_TLV320AIC26) += snd-soc-tlv320aic26.o
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obj-$(CONFIG_SND_SOC_TLV320AIC3X) += snd-soc-tlv320aic3x.o
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obj-$(CONFIG_SND_SOC_TVL320AIC32X4) += snd-soc-tlv320aic32x4.o
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obj-$(CONFIG_SND_SOC_TLV320DAC33) += snd-soc-tlv320dac33.o
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obj-$(CONFIG_SND_SOC_TWL4030) += snd-soc-twl4030.o
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obj-$(CONFIG_SND_SOC_TWL6040) += snd-soc-twl6040.o
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@ -0,0 +1,794 @@
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/*
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* linux/sound/soc/codecs/tlv320aic32x4.c
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*
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* Copyright 2011 Vista Silicon S.L.
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*
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* Author: Javier Martin <javier.martin@vista-silicon.com>
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*
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* Based on sound/soc/codecs/wm8974 and TI driver for kernel 2.6.27.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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* MA 02110-1301, USA.
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*/
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#include <linux/module.h>
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#include <linux/moduleparam.h>
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#include <linux/init.h>
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#include <linux/delay.h>
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#include <linux/pm.h>
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#include <linux/i2c.h>
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#include <linux/platform_device.h>
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#include <linux/cdev.h>
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#include <linux/slab.h>
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#include <sound/tlv320aic32x4.h>
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#include <sound/core.h>
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#include <sound/pcm.h>
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#include <sound/pcm_params.h>
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#include <sound/soc.h>
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#include <sound/soc-dapm.h>
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#include <sound/initval.h>
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#include <sound/tlv.h>
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#include "tlv320aic32x4.h"
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struct aic32x4_rate_divs {
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u32 mclk;
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u32 rate;
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u8 p_val;
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u8 pll_j;
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u16 pll_d;
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u16 dosr;
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u8 ndac;
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u8 mdac;
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u8 aosr;
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u8 nadc;
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u8 madc;
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u8 blck_N;
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};
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struct aic32x4_priv {
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u32 sysclk;
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s32 master;
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u8 page_no;
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void *control_data;
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u32 power_cfg;
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u32 micpga_routing;
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bool swapdacs;
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};
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/* 0dB min, 1dB steps */
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static DECLARE_TLV_DB_SCALE(tlv_step_1, 0, 100, 0);
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/* 0dB min, 0.5dB steps */
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static DECLARE_TLV_DB_SCALE(tlv_step_0_5, 0, 50, 0);
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static const struct snd_kcontrol_new aic32x4_snd_controls[] = {
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SOC_DOUBLE_R_TLV("PCM Playback Volume", AIC32X4_LDACVOL,
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AIC32X4_RDACVOL, 0, 0x30, 0, tlv_step_0_5),
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SOC_DOUBLE_R_TLV("HP Driver Gain Volume", AIC32X4_HPLGAIN,
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AIC32X4_HPRGAIN, 0, 0x1D, 0, tlv_step_1),
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SOC_DOUBLE_R_TLV("LO Driver Gain Volume", AIC32X4_LOLGAIN,
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AIC32X4_LORGAIN, 0, 0x1D, 0, tlv_step_1),
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SOC_DOUBLE_R("HP DAC Playback Switch", AIC32X4_HPLGAIN,
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AIC32X4_HPRGAIN, 6, 0x01, 1),
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SOC_DOUBLE_R("LO DAC Playback Switch", AIC32X4_LOLGAIN,
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AIC32X4_LORGAIN, 6, 0x01, 1),
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SOC_DOUBLE_R("Mic PGA Switch", AIC32X4_LMICPGAVOL,
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AIC32X4_RMICPGAVOL, 7, 0x01, 1),
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SOC_SINGLE("ADCFGA Left Mute Switch", AIC32X4_ADCFGA, 7, 1, 0),
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SOC_SINGLE("ADCFGA Right Mute Switch", AIC32X4_ADCFGA, 3, 1, 0),
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SOC_DOUBLE_R_TLV("ADC Level Volume", AIC32X4_LADCVOL,
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AIC32X4_RADCVOL, 0, 0x28, 0, tlv_step_0_5),
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SOC_DOUBLE_R_TLV("PGA Level Volume", AIC32X4_LMICPGAVOL,
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AIC32X4_RMICPGAVOL, 0, 0x5f, 0, tlv_step_0_5),
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SOC_SINGLE("Auto-mute Switch", AIC32X4_DACMUTE, 4, 7, 0),
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SOC_SINGLE("AGC Left Switch", AIC32X4_LAGC1, 7, 1, 0),
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SOC_SINGLE("AGC Right Switch", AIC32X4_RAGC1, 7, 1, 0),
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SOC_DOUBLE_R("AGC Target Level", AIC32X4_LAGC1, AIC32X4_RAGC1,
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4, 0x07, 0),
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SOC_DOUBLE_R("AGC Gain Hysteresis", AIC32X4_LAGC1, AIC32X4_RAGC1,
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0, 0x03, 0),
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SOC_DOUBLE_R("AGC Hysteresis", AIC32X4_LAGC2, AIC32X4_RAGC2,
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6, 0x03, 0),
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SOC_DOUBLE_R("AGC Noise Threshold", AIC32X4_LAGC2, AIC32X4_RAGC2,
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1, 0x1F, 0),
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SOC_DOUBLE_R("AGC Max PGA", AIC32X4_LAGC3, AIC32X4_RAGC3,
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0, 0x7F, 0),
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SOC_DOUBLE_R("AGC Attack Time", AIC32X4_LAGC4, AIC32X4_RAGC4,
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3, 0x1F, 0),
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SOC_DOUBLE_R("AGC Decay Time", AIC32X4_LAGC5, AIC32X4_RAGC5,
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3, 0x1F, 0),
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SOC_DOUBLE_R("AGC Noise Debounce", AIC32X4_LAGC6, AIC32X4_RAGC6,
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0, 0x1F, 0),
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SOC_DOUBLE_R("AGC Signal Debounce", AIC32X4_LAGC7, AIC32X4_RAGC7,
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0, 0x0F, 0),
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};
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static const struct aic32x4_rate_divs aic32x4_divs[] = {
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/* 8k rate */
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{AIC32X4_FREQ_12000000, 8000, 1, 7, 6800, 768, 5, 3, 128, 5, 18, 24},
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{AIC32X4_FREQ_24000000, 8000, 2, 7, 6800, 768, 15, 1, 64, 45, 4, 24},
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{AIC32X4_FREQ_25000000, 8000, 2, 7, 3728, 768, 15, 1, 64, 45, 4, 24},
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/* 11.025k rate */
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{AIC32X4_FREQ_12000000, 11025, 1, 7, 5264, 512, 8, 2, 128, 8, 8, 16},
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{AIC32X4_FREQ_24000000, 11025, 2, 7, 5264, 512, 16, 1, 64, 32, 4, 16},
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/* 16k rate */
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{AIC32X4_FREQ_12000000, 16000, 1, 7, 6800, 384, 5, 3, 128, 5, 9, 12},
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{AIC32X4_FREQ_24000000, 16000, 2, 7, 6800, 384, 15, 1, 64, 18, 5, 12},
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{AIC32X4_FREQ_25000000, 16000, 2, 7, 3728, 384, 15, 1, 64, 18, 5, 12},
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/* 22.05k rate */
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{AIC32X4_FREQ_12000000, 22050, 1, 7, 5264, 256, 4, 4, 128, 4, 8, 8},
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{AIC32X4_FREQ_24000000, 22050, 2, 7, 5264, 256, 16, 1, 64, 16, 4, 8},
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{AIC32X4_FREQ_25000000, 22050, 2, 7, 2253, 256, 16, 1, 64, 16, 4, 8},
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/* 32k rate */
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{AIC32X4_FREQ_12000000, 32000, 1, 7, 1680, 192, 2, 7, 64, 2, 21, 6},
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{AIC32X4_FREQ_24000000, 32000, 2, 7, 1680, 192, 7, 2, 64, 7, 6, 6},
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/* 44.1k rate */
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{AIC32X4_FREQ_12000000, 44100, 1, 7, 5264, 128, 2, 8, 128, 2, 8, 4},
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{AIC32X4_FREQ_24000000, 44100, 2, 7, 5264, 128, 8, 2, 64, 8, 4, 4},
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{AIC32X4_FREQ_25000000, 44100, 2, 7, 2253, 128, 8, 2, 64, 8, 4, 4},
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/* 48k rate */
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{AIC32X4_FREQ_12000000, 48000, 1, 8, 1920, 128, 2, 8, 128, 2, 8, 4},
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{AIC32X4_FREQ_24000000, 48000, 2, 8, 1920, 128, 8, 2, 64, 8, 4, 4},
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{AIC32X4_FREQ_25000000, 48000, 2, 7, 8643, 128, 8, 2, 64, 8, 4, 4}
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};
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static const struct snd_kcontrol_new hpl_output_mixer_controls[] = {
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SOC_DAPM_SINGLE("L_DAC Switch", AIC32X4_HPLROUTE, 3, 1, 0),
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SOC_DAPM_SINGLE("IN1_L Switch", AIC32X4_HPLROUTE, 2, 1, 0),
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};
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static const struct snd_kcontrol_new hpr_output_mixer_controls[] = {
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SOC_DAPM_SINGLE("R_DAC Switch", AIC32X4_HPRROUTE, 3, 1, 0),
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SOC_DAPM_SINGLE("IN1_R Switch", AIC32X4_HPRROUTE, 2, 1, 0),
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};
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static const struct snd_kcontrol_new lol_output_mixer_controls[] = {
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SOC_DAPM_SINGLE("L_DAC Switch", AIC32X4_LOLROUTE, 3, 1, 0),
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};
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static const struct snd_kcontrol_new lor_output_mixer_controls[] = {
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SOC_DAPM_SINGLE("R_DAC Switch", AIC32X4_LORROUTE, 3, 1, 0),
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};
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static const struct snd_kcontrol_new left_input_mixer_controls[] = {
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SOC_DAPM_SINGLE("IN1_L P Switch", AIC32X4_LMICPGAPIN, 6, 1, 0),
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SOC_DAPM_SINGLE("IN2_L P Switch", AIC32X4_LMICPGAPIN, 4, 1, 0),
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SOC_DAPM_SINGLE("IN3_L P Switch", AIC32X4_LMICPGAPIN, 2, 1, 0),
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};
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static const struct snd_kcontrol_new right_input_mixer_controls[] = {
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SOC_DAPM_SINGLE("IN1_R P Switch", AIC32X4_RMICPGAPIN, 6, 1, 0),
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SOC_DAPM_SINGLE("IN2_R P Switch", AIC32X4_RMICPGAPIN, 4, 1, 0),
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SOC_DAPM_SINGLE("IN3_R P Switch", AIC32X4_RMICPGAPIN, 2, 1, 0),
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};
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static const struct snd_soc_dapm_widget aic32x4_dapm_widgets[] = {
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SND_SOC_DAPM_DAC("Left DAC", "Left Playback", AIC32X4_DACSETUP, 7, 0),
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SND_SOC_DAPM_MIXER("HPL Output Mixer", SND_SOC_NOPM, 0, 0,
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&hpl_output_mixer_controls[0],
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ARRAY_SIZE(hpl_output_mixer_controls)),
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SND_SOC_DAPM_PGA("HPL Power", AIC32X4_OUTPWRCTL, 5, 0, NULL, 0),
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SND_SOC_DAPM_MIXER("LOL Output Mixer", SND_SOC_NOPM, 0, 0,
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&lol_output_mixer_controls[0],
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ARRAY_SIZE(lol_output_mixer_controls)),
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SND_SOC_DAPM_PGA("LOL Power", AIC32X4_OUTPWRCTL, 3, 0, NULL, 0),
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SND_SOC_DAPM_DAC("Right DAC", "Right Playback", AIC32X4_DACSETUP, 6, 0),
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SND_SOC_DAPM_MIXER("HPR Output Mixer", SND_SOC_NOPM, 0, 0,
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&hpr_output_mixer_controls[0],
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ARRAY_SIZE(hpr_output_mixer_controls)),
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SND_SOC_DAPM_PGA("HPR Power", AIC32X4_OUTPWRCTL, 4, 0, NULL, 0),
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SND_SOC_DAPM_MIXER("LOR Output Mixer", SND_SOC_NOPM, 0, 0,
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&lor_output_mixer_controls[0],
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ARRAY_SIZE(lor_output_mixer_controls)),
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SND_SOC_DAPM_PGA("LOR Power", AIC32X4_OUTPWRCTL, 2, 0, NULL, 0),
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SND_SOC_DAPM_MIXER("Left Input Mixer", SND_SOC_NOPM, 0, 0,
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&left_input_mixer_controls[0],
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ARRAY_SIZE(left_input_mixer_controls)),
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SND_SOC_DAPM_MIXER("Right Input Mixer", SND_SOC_NOPM, 0, 0,
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&right_input_mixer_controls[0],
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ARRAY_SIZE(right_input_mixer_controls)),
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SND_SOC_DAPM_ADC("Left ADC", "Left Capture", AIC32X4_ADCSETUP, 7, 0),
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SND_SOC_DAPM_ADC("Right ADC", "Right Capture", AIC32X4_ADCSETUP, 6, 0),
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SND_SOC_DAPM_MICBIAS("Mic Bias", AIC32X4_MICBIAS, 6, 0),
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SND_SOC_DAPM_OUTPUT("HPL"),
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SND_SOC_DAPM_OUTPUT("HPR"),
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SND_SOC_DAPM_OUTPUT("LOL"),
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SND_SOC_DAPM_OUTPUT("LOR"),
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SND_SOC_DAPM_INPUT("IN1_L"),
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SND_SOC_DAPM_INPUT("IN1_R"),
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SND_SOC_DAPM_INPUT("IN2_L"),
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SND_SOC_DAPM_INPUT("IN2_R"),
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SND_SOC_DAPM_INPUT("IN3_L"),
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SND_SOC_DAPM_INPUT("IN3_R"),
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};
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static const struct snd_soc_dapm_route aic32x4_dapm_routes[] = {
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/* Left Output */
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{"HPL Output Mixer", "L_DAC Switch", "Left DAC"},
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{"HPL Output Mixer", "IN1_L Switch", "IN1_L"},
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{"HPL Power", NULL, "HPL Output Mixer"},
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{"HPL", NULL, "HPL Power"},
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{"LOL Output Mixer", "L_DAC Switch", "Left DAC"},
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{"LOL Power", NULL, "LOL Output Mixer"},
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{"LOL", NULL, "LOL Power"},
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/* Right Output */
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{"HPR Output Mixer", "R_DAC Switch", "Right DAC"},
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{"HPR Output Mixer", "IN1_R Switch", "IN1_R"},
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{"HPR Power", NULL, "HPR Output Mixer"},
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{"HPR", NULL, "HPR Power"},
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{"LOR Output Mixer", "R_DAC Switch", "Right DAC"},
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{"LOR Power", NULL, "LOR Output Mixer"},
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{"LOR", NULL, "LOR Power"},
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/* Left input */
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{"Left Input Mixer", "IN1_L P Switch", "IN1_L"},
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{"Left Input Mixer", "IN2_L P Switch", "IN2_L"},
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{"Left Input Mixer", "IN3_L P Switch", "IN3_L"},
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{"Left ADC", NULL, "Left Input Mixer"},
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/* Right Input */
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{"Right Input Mixer", "IN1_R P Switch", "IN1_R"},
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{"Right Input Mixer", "IN2_R P Switch", "IN2_R"},
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{"Right Input Mixer", "IN3_R P Switch", "IN3_R"},
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{"Right ADC", NULL, "Right Input Mixer"},
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||||
};
|
||||
|
||||
static inline int aic32x4_change_page(struct snd_soc_codec *codec,
|
||||
unsigned int new_page)
|
||||
{
|
||||
struct aic32x4_priv *aic32x4 = snd_soc_codec_get_drvdata(codec);
|
||||
u8 data[2];
|
||||
int ret;
|
||||
|
||||
data[0] = 0x00;
|
||||
data[1] = new_page & 0xff;
|
||||
|
||||
ret = codec->hw_write(codec->control_data, data, 2);
|
||||
if (ret == 2) {
|
||||
aic32x4->page_no = new_page;
|
||||
return 0;
|
||||
} else {
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
static int aic32x4_write(struct snd_soc_codec *codec, unsigned int reg,
|
||||
unsigned int val)
|
||||
{
|
||||
struct aic32x4_priv *aic32x4 = snd_soc_codec_get_drvdata(codec);
|
||||
unsigned int page = reg / 128;
|
||||
unsigned int fixed_reg = reg % 128;
|
||||
u8 data[2];
|
||||
int ret;
|
||||
|
||||
/* A write to AIC32X4_PSEL is really a non-explicit page change */
|
||||
if (reg == AIC32X4_PSEL)
|
||||
return aic32x4_change_page(codec, val);
|
||||
|
||||
if (aic32x4->page_no != page) {
|
||||
ret = aic32x4_change_page(codec, page);
|
||||
if (ret != 0)
|
||||
return ret;
|
||||
}
|
||||
|
||||
data[0] = fixed_reg & 0xff;
|
||||
data[1] = val & 0xff;
|
||||
|
||||
if (codec->hw_write(codec->control_data, data, 2) == 2)
|
||||
return 0;
|
||||
else
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
static unsigned int aic32x4_read(struct snd_soc_codec *codec, unsigned int reg)
|
||||
{
|
||||
struct aic32x4_priv *aic32x4 = snd_soc_codec_get_drvdata(codec);
|
||||
unsigned int page = reg / 128;
|
||||
unsigned int fixed_reg = reg % 128;
|
||||
int ret;
|
||||
|
||||
if (aic32x4->page_no != page) {
|
||||
ret = aic32x4_change_page(codec, page);
|
||||
if (ret != 0)
|
||||
return ret;
|
||||
}
|
||||
return i2c_smbus_read_byte_data(codec->control_data, fixed_reg & 0xff);
|
||||
}
|
||||
|
||||
static inline int aic32x4_get_divs(int mclk, int rate)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(aic32x4_divs); i++) {
|
||||
if ((aic32x4_divs[i].rate == rate)
|
||||
&& (aic32x4_divs[i].mclk == mclk)) {
|
||||
return i;
|
||||
}
|
||||
}
|
||||
printk(KERN_ERR "aic32x4: master clock and sample rate is not supported\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
static int aic32x4_add_widgets(struct snd_soc_codec *codec)
|
||||
{
|
||||
snd_soc_dapm_new_controls(codec, aic32x4_dapm_widgets,
|
||||
ARRAY_SIZE(aic32x4_dapm_widgets));
|
||||
|
||||
snd_soc_dapm_add_routes(codec, aic32x4_dapm_routes,
|
||||
ARRAY_SIZE(aic32x4_dapm_routes));
|
||||
|
||||
snd_soc_dapm_new_widgets(codec);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int aic32x4_set_dai_sysclk(struct snd_soc_dai *codec_dai,
|
||||
int clk_id, unsigned int freq, int dir)
|
||||
{
|
||||
struct snd_soc_codec *codec = codec_dai->codec;
|
||||
struct aic32x4_priv *aic32x4 = snd_soc_codec_get_drvdata(codec);
|
||||
|
||||
switch (freq) {
|
||||
case AIC32X4_FREQ_12000000:
|
||||
case AIC32X4_FREQ_24000000:
|
||||
case AIC32X4_FREQ_25000000:
|
||||
aic32x4->sysclk = freq;
|
||||
return 0;
|
||||
}
|
||||
printk(KERN_ERR "aic32x4: invalid frequency to set DAI system clock\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
static int aic32x4_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
|
||||
{
|
||||
struct snd_soc_codec *codec = codec_dai->codec;
|
||||
struct aic32x4_priv *aic32x4 = snd_soc_codec_get_drvdata(codec);
|
||||
u8 iface_reg_1;
|
||||
u8 iface_reg_2;
|
||||
u8 iface_reg_3;
|
||||
|
||||
iface_reg_1 = snd_soc_read(codec, AIC32X4_IFACE1);
|
||||
iface_reg_1 = iface_reg_1 & ~(3 << 6 | 3 << 2);
|
||||
iface_reg_2 = snd_soc_read(codec, AIC32X4_IFACE2);
|
||||
iface_reg_2 = 0;
|
||||
iface_reg_3 = snd_soc_read(codec, AIC32X4_IFACE3);
|
||||
iface_reg_3 = iface_reg_3 & ~(1 << 3);
|
||||
|
||||
/* set master/slave audio interface */
|
||||
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
|
||||
case SND_SOC_DAIFMT_CBM_CFM:
|
||||
aic32x4->master = 1;
|
||||
iface_reg_1 |= AIC32X4_BCLKMASTER | AIC32X4_WCLKMASTER;
|
||||
break;
|
||||
case SND_SOC_DAIFMT_CBS_CFS:
|
||||
aic32x4->master = 0;
|
||||
break;
|
||||
default:
|
||||
printk(KERN_ERR "aic32x4: invalid DAI master/slave interface\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
|
||||
case SND_SOC_DAIFMT_I2S:
|
||||
break;
|
||||
case SND_SOC_DAIFMT_DSP_A:
|
||||
iface_reg_1 |= (AIC32X4_DSP_MODE << AIC32X4_PLLJ_SHIFT);
|
||||
iface_reg_3 |= (1 << 3); /* invert bit clock */
|
||||
iface_reg_2 = 0x01; /* add offset 1 */
|
||||
break;
|
||||
case SND_SOC_DAIFMT_DSP_B:
|
||||
iface_reg_1 |= (AIC32X4_DSP_MODE << AIC32X4_PLLJ_SHIFT);
|
||||
iface_reg_3 |= (1 << 3); /* invert bit clock */
|
||||
break;
|
||||
case SND_SOC_DAIFMT_RIGHT_J:
|
||||
iface_reg_1 |=
|
||||
(AIC32X4_RIGHT_JUSTIFIED_MODE << AIC32X4_PLLJ_SHIFT);
|
||||
break;
|
||||
case SND_SOC_DAIFMT_LEFT_J:
|
||||
iface_reg_1 |=
|
||||
(AIC32X4_LEFT_JUSTIFIED_MODE << AIC32X4_PLLJ_SHIFT);
|
||||
break;
|
||||
default:
|
||||
printk(KERN_ERR "aic32x4: invalid DAI interface format\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
snd_soc_write(codec, AIC32X4_IFACE1, iface_reg_1);
|
||||
snd_soc_write(codec, AIC32X4_IFACE2, iface_reg_2);
|
||||
snd_soc_write(codec, AIC32X4_IFACE3, iface_reg_3);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int aic32x4_hw_params(struct snd_pcm_substream *substream,
|
||||
struct snd_pcm_hw_params *params,
|
||||
struct snd_soc_dai *dai)
|
||||
{
|
||||
struct snd_soc_codec *codec = dai->codec;
|
||||
struct aic32x4_priv *aic32x4 = snd_soc_codec_get_drvdata(codec);
|
||||
u8 data;
|
||||
int i;
|
||||
|
||||
i = aic32x4_get_divs(aic32x4->sysclk, params_rate(params));
|
||||
if (i < 0) {
|
||||
printk(KERN_ERR "aic32x4: sampling rate not supported\n");
|
||||
return i;
|
||||
}
|
||||
|
||||
/* Use PLL as CODEC_CLKIN and DAC_MOD_CLK as BDIV_CLKIN */
|
||||
snd_soc_write(codec, AIC32X4_CLKMUX, AIC32X4_PLLCLKIN);
|
||||
snd_soc_write(codec, AIC32X4_IFACE3, AIC32X4_DACMOD2BCLK);
|
||||
|
||||
/* We will fix R value to 1 and will make P & J=K.D as varialble */
|
||||
data = snd_soc_read(codec, AIC32X4_PLLPR);
|
||||
data &= ~(7 << 4);
|
||||
snd_soc_write(codec, AIC32X4_PLLPR,
|
||||
(data | (aic32x4_divs[i].p_val << 4) | 0x01));
|
||||
|
||||
snd_soc_write(codec, AIC32X4_PLLJ, aic32x4_divs[i].pll_j);
|
||||
|
||||
snd_soc_write(codec, AIC32X4_PLLDMSB, (aic32x4_divs[i].pll_d >> 8));
|
||||
snd_soc_write(codec, AIC32X4_PLLDLSB,
|
||||
(aic32x4_divs[i].pll_d & 0xff));
|
||||
|
||||
/* NDAC divider value */
|
||||
data = snd_soc_read(codec, AIC32X4_NDAC);
|
||||
data &= ~(0x7f);
|
||||
snd_soc_write(codec, AIC32X4_NDAC, data | aic32x4_divs[i].ndac);
|
||||
|
||||
/* MDAC divider value */
|
||||
data = snd_soc_read(codec, AIC32X4_MDAC);
|
||||
data &= ~(0x7f);
|
||||
snd_soc_write(codec, AIC32X4_MDAC, data | aic32x4_divs[i].mdac);
|
||||
|
||||
/* DOSR MSB & LSB values */
|
||||
snd_soc_write(codec, AIC32X4_DOSRMSB, aic32x4_divs[i].dosr >> 8);
|
||||
snd_soc_write(codec, AIC32X4_DOSRLSB,
|
||||
(aic32x4_divs[i].dosr & 0xff));
|
||||
|
||||
/* NADC divider value */
|
||||
data = snd_soc_read(codec, AIC32X4_NADC);
|
||||
data &= ~(0x7f);
|
||||
snd_soc_write(codec, AIC32X4_NADC, data | aic32x4_divs[i].nadc);
|
||||
|
||||
/* MADC divider value */
|
||||
data = snd_soc_read(codec, AIC32X4_MADC);
|
||||
data &= ~(0x7f);
|
||||
snd_soc_write(codec, AIC32X4_MADC, data | aic32x4_divs[i].madc);
|
||||
|
||||
/* AOSR value */
|
||||
snd_soc_write(codec, AIC32X4_AOSR, aic32x4_divs[i].aosr);
|
||||
|
||||
/* BCLK N divider */
|
||||
data = snd_soc_read(codec, AIC32X4_BCLKN);
|
||||
data &= ~(0x7f);
|
||||
snd_soc_write(codec, AIC32X4_BCLKN, data | aic32x4_divs[i].blck_N);
|
||||
|
||||
data = snd_soc_read(codec, AIC32X4_IFACE1);
|
||||
data = data & ~(3 << 4);
|
||||
switch (params_format(params)) {
|
||||
case SNDRV_PCM_FORMAT_S16_LE:
|
||||
break;
|
||||
case SNDRV_PCM_FORMAT_S20_3LE:
|
||||
data |= (AIC32X4_WORD_LEN_20BITS << AIC32X4_DOSRMSB_SHIFT);
|
||||
break;
|
||||
case SNDRV_PCM_FORMAT_S24_LE:
|
||||
data |= (AIC32X4_WORD_LEN_24BITS << AIC32X4_DOSRMSB_SHIFT);
|
||||
break;
|
||||
case SNDRV_PCM_FORMAT_S32_LE:
|
||||
data |= (AIC32X4_WORD_LEN_32BITS << AIC32X4_DOSRMSB_SHIFT);
|
||||
break;
|
||||
}
|
||||
snd_soc_write(codec, AIC32X4_IFACE1, data);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int aic32x4_mute(struct snd_soc_dai *dai, int mute)
|
||||
{
|
||||
struct snd_soc_codec *codec = dai->codec;
|
||||
u8 dac_reg;
|
||||
|
||||
dac_reg = snd_soc_read(codec, AIC32X4_DACMUTE) & ~AIC32X4_MUTEON;
|
||||
if (mute)
|
||||
snd_soc_write(codec, AIC32X4_DACMUTE, dac_reg | AIC32X4_MUTEON);
|
||||
else
|
||||
snd_soc_write(codec, AIC32X4_DACMUTE, dac_reg);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int aic32x4_set_bias_level(struct snd_soc_codec *codec,
|
||||
enum snd_soc_bias_level level)
|
||||
{
|
||||
struct aic32x4_priv *aic32x4 = snd_soc_codec_get_drvdata(codec);
|
||||
u8 value;
|
||||
|
||||
switch (level) {
|
||||
case SND_SOC_BIAS_ON:
|
||||
if (aic32x4->master) {
|
||||
/* Switch on PLL */
|
||||
value = snd_soc_read(codec, AIC32X4_PLLPR);
|
||||
snd_soc_write(codec, AIC32X4_PLLPR,
|
||||
(value | AIC32X4_PLLEN));
|
||||
|
||||
/* Switch on NDAC Divider */
|
||||
value = snd_soc_read(codec, AIC32X4_NDAC);
|
||||
snd_soc_write(codec, AIC32X4_NDAC,
|
||||
value | AIC32X4_NDACEN);
|
||||
|
||||
/* Switch on MDAC Divider */
|
||||
value = snd_soc_read(codec, AIC32X4_MDAC);
|
||||
snd_soc_write(codec, AIC32X4_MDAC,
|
||||
value | AIC32X4_MDACEN);
|
||||
|
||||
/* Switch on NADC Divider */
|
||||
value = snd_soc_read(codec, AIC32X4_NADC);
|
||||
snd_soc_write(codec, AIC32X4_NADC,
|
||||
value | AIC32X4_MDACEN);
|
||||
|
||||
/* Switch on MADC Divider */
|
||||
value = snd_soc_read(codec, AIC32X4_MADC);
|
||||
snd_soc_write(codec, AIC32X4_MADC,
|
||||
value | AIC32X4_MDACEN);
|
||||
|
||||
/* Switch on BCLK_N Divider */
|
||||
value = snd_soc_read(codec, AIC32X4_BCLKN);
|
||||
snd_soc_write(codec, AIC32X4_BCLKN,
|
||||
value | AIC32X4_BCLKEN);
|
||||
}
|
||||
break;
|
||||
case SND_SOC_BIAS_PREPARE:
|
||||
break;
|
||||
case SND_SOC_BIAS_STANDBY:
|
||||
if (aic32x4->master) {
|
||||
/* Switch off PLL */
|
||||
value = snd_soc_read(codec, AIC32X4_PLLPR);
|
||||
snd_soc_write(codec, AIC32X4_PLLPR,
|
||||
(value & ~AIC32X4_PLLEN));
|
||||
|
||||
/* Switch off NDAC Divider */
|
||||
value = snd_soc_read(codec, AIC32X4_NDAC);
|
||||
snd_soc_write(codec, AIC32X4_NDAC,
|
||||
value & ~AIC32X4_NDACEN);
|
||||
|
||||
/* Switch off MDAC Divider */
|
||||
value = snd_soc_read(codec, AIC32X4_MDAC);
|
||||
snd_soc_write(codec, AIC32X4_MDAC,
|
||||
value & ~AIC32X4_MDACEN);
|
||||
|
||||
/* Switch off NADC Divider */
|
||||
value = snd_soc_read(codec, AIC32X4_NADC);
|
||||
snd_soc_write(codec, AIC32X4_NADC,
|
||||
value & ~AIC32X4_NDACEN);
|
||||
|
||||
/* Switch off MADC Divider */
|
||||
value = snd_soc_read(codec, AIC32X4_MADC);
|
||||
snd_soc_write(codec, AIC32X4_MADC,
|
||||
value & ~AIC32X4_MDACEN);
|
||||
value = snd_soc_read(codec, AIC32X4_BCLKN);
|
||||
|
||||
/* Switch off BCLK_N Divider */
|
||||
snd_soc_write(codec, AIC32X4_BCLKN,
|
||||
value & ~AIC32X4_BCLKEN);
|
||||
}
|
||||
break;
|
||||
case SND_SOC_BIAS_OFF:
|
||||
break;
|
||||
}
|
||||
codec->bias_level = level;
|
||||
return 0;
|
||||
}
|
||||
|
||||
#define AIC32X4_RATES SNDRV_PCM_RATE_8000_48000
|
||||
#define AIC32X4_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \
|
||||
| SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
|
||||
|
||||
static struct snd_soc_dai_ops aic32x4_ops = {
|
||||
.hw_params = aic32x4_hw_params,
|
||||
.digital_mute = aic32x4_mute,
|
||||
.set_fmt = aic32x4_set_dai_fmt,
|
||||
.set_sysclk = aic32x4_set_dai_sysclk,
|
||||
};
|
||||
|
||||
static struct snd_soc_dai_driver aic32x4_dai = {
|
||||
.name = "tlv320aic32x4-hifi",
|
||||
.playback = {
|
||||
.stream_name = "Playback",
|
||||
.channels_min = 1,
|
||||
.channels_max = 2,
|
||||
.rates = AIC32X4_RATES,
|
||||
.formats = AIC32X4_FORMATS,},
|
||||
.capture = {
|
||||
.stream_name = "Capture",
|
||||
.channels_min = 1,
|
||||
.channels_max = 2,
|
||||
.rates = AIC32X4_RATES,
|
||||
.formats = AIC32X4_FORMATS,},
|
||||
.ops = &aic32x4_ops,
|
||||
.symmetric_rates = 1,
|
||||
};
|
||||
|
||||
static int aic32x4_suspend(struct snd_soc_codec *codec, pm_message_t state)
|
||||
{
|
||||
aic32x4_set_bias_level(codec, SND_SOC_BIAS_OFF);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int aic32x4_resume(struct snd_soc_codec *codec)
|
||||
{
|
||||
aic32x4_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int aic32x4_probe(struct snd_soc_codec *codec)
|
||||
{
|
||||
struct aic32x4_priv *aic32x4 = snd_soc_codec_get_drvdata(codec);
|
||||
u32 tmp_reg;
|
||||
|
||||
codec->hw_write = (hw_write_t) i2c_master_send;
|
||||
codec->control_data = aic32x4->control_data;
|
||||
|
||||
snd_soc_write(codec, AIC32X4_RESET, 0x01);
|
||||
|
||||
/* Power platform configuration */
|
||||
if (aic32x4->power_cfg & AIC32X4_PWR_MICBIAS_2075_LDOIN) {
|
||||
snd_soc_write(codec, AIC32X4_MICBIAS, AIC32X4_MICBIAS_LDOIN |
|
||||
AIC32X4_MICBIAS_2075V);
|
||||
}
|
||||
if (aic32x4->power_cfg & AIC32X4_PWR_AVDD_DVDD_WEAK_DISABLE) {
|
||||
snd_soc_write(codec, AIC32X4_PWRCFG, AIC32X4_AVDDWEAKDISABLE);
|
||||
}
|
||||
if (aic32x4->power_cfg & AIC32X4_PWR_AIC32X4_LDO_ENABLE) {
|
||||
snd_soc_write(codec, AIC32X4_LDOCTL, AIC32X4_LDOCTLEN);
|
||||
}
|
||||
tmp_reg = snd_soc_read(codec, AIC32X4_CMMODE);
|
||||
if (aic32x4->power_cfg & AIC32X4_PWR_CMMODE_LDOIN_RANGE_18_36) {
|
||||
tmp_reg |= AIC32X4_LDOIN_18_36;
|
||||
}
|
||||
if (aic32x4->power_cfg & AIC32X4_PWR_CMMODE_HP_LDOIN_POWERED) {
|
||||
tmp_reg |= AIC32X4_LDOIN2HP;
|
||||
}
|
||||
snd_soc_write(codec, AIC32X4_CMMODE, tmp_reg);
|
||||
|
||||
/* Do DACs need to be swapped? */
|
||||
if (aic32x4->swapdacs) {
|
||||
snd_soc_write(codec, AIC32X4_DACSETUP, AIC32X4_LDAC2RCHN | AIC32X4_RDAC2LCHN);
|
||||
} else {
|
||||
snd_soc_write(codec, AIC32X4_DACSETUP, AIC32X4_LDAC2LCHN | AIC32X4_RDAC2RCHN);
|
||||
}
|
||||
|
||||
/* Mic PGA routing */
|
||||
if (aic32x4->micpga_routing | AIC32X4_MICPGA_ROUTE_LMIC_IN2R_10K) {
|
||||
snd_soc_write(codec, AIC32X4_LMICPGANIN, AIC32X4_LMICPGANIN_IN2R_10K);
|
||||
}
|
||||
if (aic32x4->micpga_routing | AIC32X4_MICPGA_ROUTE_RMIC_IN1L_10K) {
|
||||
snd_soc_write(codec, AIC32X4_RMICPGANIN, AIC32X4_RMICPGANIN_IN1L_10K);
|
||||
}
|
||||
|
||||
aic32x4_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
|
||||
snd_soc_add_controls(codec, aic32x4_snd_controls,
|
||||
ARRAY_SIZE(aic32x4_snd_controls));
|
||||
aic32x4_add_widgets(codec);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int aic32x4_remove(struct snd_soc_codec *codec)
|
||||
{
|
||||
aic32x4_set_bias_level(codec, SND_SOC_BIAS_OFF);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct snd_soc_codec_driver soc_codec_dev_aic32x4 = {
|
||||
.read = aic32x4_read,
|
||||
.write = aic32x4_write,
|
||||
.probe = aic32x4_probe,
|
||||
.remove = aic32x4_remove,
|
||||
.suspend = aic32x4_suspend,
|
||||
.resume = aic32x4_resume,
|
||||
.set_bias_level = aic32x4_set_bias_level,
|
||||
};
|
||||
|
||||
static __devinit int aic32x4_i2c_probe(struct i2c_client *i2c,
|
||||
const struct i2c_device_id *id)
|
||||
{
|
||||
struct aic32x4_pdata *pdata = i2c->dev.platform_data;
|
||||
struct aic32x4_priv *aic32x4;
|
||||
int ret;
|
||||
|
||||
aic32x4 = kzalloc(sizeof(struct aic32x4_priv), GFP_KERNEL);
|
||||
if (aic32x4 == NULL)
|
||||
return -ENOMEM;
|
||||
|
||||
aic32x4->control_data = i2c;
|
||||
i2c_set_clientdata(i2c, aic32x4);
|
||||
|
||||
if (pdata) {
|
||||
aic32x4->power_cfg = pdata->power_cfg;
|
||||
aic32x4->swapdacs = pdata->swapdacs;
|
||||
aic32x4->micpga_routing = pdata->micpga_routing;
|
||||
} else {
|
||||
aic32x4->power_cfg = 0;
|
||||
aic32x4->swapdacs = false;
|
||||
aic32x4->micpga_routing = 0;
|
||||
}
|
||||
|
||||
ret = snd_soc_register_codec(&i2c->dev,
|
||||
&soc_codec_dev_aic32x4, &aic32x4_dai, 1);
|
||||
if (ret < 0)
|
||||
kfree(aic32x4);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static __devexit int aic32x4_i2c_remove(struct i2c_client *client)
|
||||
{
|
||||
snd_soc_unregister_codec(&client->dev);
|
||||
kfree(i2c_get_clientdata(client));
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct i2c_device_id aic32x4_i2c_id[] = {
|
||||
{ "tlv320aic32x4", 0 },
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(i2c, aic32x4_i2c_id);
|
||||
|
||||
static struct i2c_driver aic32x4_i2c_driver = {
|
||||
.driver = {
|
||||
.name = "tlv320aic32x4",
|
||||
.owner = THIS_MODULE,
|
||||
},
|
||||
.probe = aic32x4_i2c_probe,
|
||||
.remove = __devexit_p(aic32x4_i2c_remove),
|
||||
.id_table = aic32x4_i2c_id,
|
||||
};
|
||||
|
||||
static int __init aic32x4_modinit(void)
|
||||
{
|
||||
int ret = 0;
|
||||
|
||||
ret = i2c_add_driver(&aic32x4_i2c_driver);
|
||||
if (ret != 0) {
|
||||
printk(KERN_ERR "Failed to register aic32x4 I2C driver: %d\n",
|
||||
ret);
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
module_init(aic32x4_modinit);
|
||||
|
||||
static void __exit aic32x4_exit(void)
|
||||
{
|
||||
i2c_del_driver(&aic32x4_i2c_driver);
|
||||
}
|
||||
module_exit(aic32x4_exit);
|
||||
|
||||
MODULE_DESCRIPTION("ASoC tlv320aic32x4 codec driver");
|
||||
MODULE_AUTHOR("Javier Martin <javier.martin@vista-silicon.com>");
|
||||
MODULE_LICENSE("GPL");
|
||||
|
|
@ -0,0 +1,143 @@
|
|||
/*
|
||||
* tlv320aic32x4.h
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _TLV320AIC32X4_H
|
||||
#define _TLV320AIC32X4_H
|
||||
|
||||
/* tlv320aic32x4 register space (in decimal to match datasheet) */
|
||||
|
||||
#define AIC32X4_PAGE1 128
|
||||
|
||||
#define AIC32X4_PSEL 0
|
||||
#define AIC32X4_RESET 1
|
||||
#define AIC32X4_CLKMUX 4
|
||||
#define AIC32X4_PLLPR 5
|
||||
#define AIC32X4_PLLJ 6
|
||||
#define AIC32X4_PLLDMSB 7
|
||||
#define AIC32X4_PLLDLSB 8
|
||||
#define AIC32X4_NDAC 11
|
||||
#define AIC32X4_MDAC 12
|
||||
#define AIC32X4_DOSRMSB 13
|
||||
#define AIC32X4_DOSRLSB 14
|
||||
#define AIC32X4_NADC 18
|
||||
#define AIC32X4_MADC 19
|
||||
#define AIC32X4_AOSR 20
|
||||
#define AIC32X4_CLKMUX2 25
|
||||
#define AIC32X4_CLKOUTM 26
|
||||
#define AIC32X4_IFACE1 27
|
||||
#define AIC32X4_IFACE2 28
|
||||
#define AIC32X4_IFACE3 29
|
||||
#define AIC32X4_BCLKN 30
|
||||
#define AIC32X4_IFACE4 31
|
||||
#define AIC32X4_IFACE5 32
|
||||
#define AIC32X4_IFACE6 33
|
||||
#define AIC32X4_DOUTCTL 53
|
||||
#define AIC32X4_DINCTL 54
|
||||
#define AIC32X4_DACSPB 60
|
||||
#define AIC32X4_ADCSPB 61
|
||||
#define AIC32X4_DACSETUP 63
|
||||
#define AIC32X4_DACMUTE 64
|
||||
#define AIC32X4_LDACVOL 65
|
||||
#define AIC32X4_RDACVOL 66
|
||||
#define AIC32X4_ADCSETUP 81
|
||||
#define AIC32X4_ADCFGA 82
|
||||
#define AIC32X4_LADCVOL 83
|
||||
#define AIC32X4_RADCVOL 84
|
||||
#define AIC32X4_LAGC1 86
|
||||
#define AIC32X4_LAGC2 87
|
||||
#define AIC32X4_LAGC3 88
|
||||
#define AIC32X4_LAGC4 89
|
||||
#define AIC32X4_LAGC5 90
|
||||
#define AIC32X4_LAGC6 91
|
||||
#define AIC32X4_LAGC7 92
|
||||
#define AIC32X4_RAGC1 94
|
||||
#define AIC32X4_RAGC2 95
|
||||
#define AIC32X4_RAGC3 96
|
||||
#define AIC32X4_RAGC4 97
|
||||
#define AIC32X4_RAGC5 98
|
||||
#define AIC32X4_RAGC6 99
|
||||
#define AIC32X4_RAGC7 100
|
||||
#define AIC32X4_PWRCFG (AIC32X4_PAGE1 + 1)
|
||||
#define AIC32X4_LDOCTL (AIC32X4_PAGE1 + 2)
|
||||
#define AIC32X4_OUTPWRCTL (AIC32X4_PAGE1 + 9)
|
||||
#define AIC32X4_CMMODE (AIC32X4_PAGE1 + 10)
|
||||
#define AIC32X4_HPLROUTE (AIC32X4_PAGE1 + 12)
|
||||
#define AIC32X4_HPRROUTE (AIC32X4_PAGE1 + 13)
|
||||
#define AIC32X4_LOLROUTE (AIC32X4_PAGE1 + 14)
|
||||
#define AIC32X4_LORROUTE (AIC32X4_PAGE1 + 15)
|
||||
#define AIC32X4_HPLGAIN (AIC32X4_PAGE1 + 16)
|
||||
#define AIC32X4_HPRGAIN (AIC32X4_PAGE1 + 17)
|
||||
#define AIC32X4_LOLGAIN (AIC32X4_PAGE1 + 18)
|
||||
#define AIC32X4_LORGAIN (AIC32X4_PAGE1 + 19)
|
||||
#define AIC32X4_HEADSTART (AIC32X4_PAGE1 + 20)
|
||||
#define AIC32X4_MICBIAS (AIC32X4_PAGE1 + 51)
|
||||
#define AIC32X4_LMICPGAPIN (AIC32X4_PAGE1 + 52)
|
||||
#define AIC32X4_LMICPGANIN (AIC32X4_PAGE1 + 54)
|
||||
#define AIC32X4_RMICPGAPIN (AIC32X4_PAGE1 + 55)
|
||||
#define AIC32X4_RMICPGANIN (AIC32X4_PAGE1 + 57)
|
||||
#define AIC32X4_FLOATINGINPUT (AIC32X4_PAGE1 + 58)
|
||||
#define AIC32X4_LMICPGAVOL (AIC32X4_PAGE1 + 59)
|
||||
#define AIC32X4_RMICPGAVOL (AIC32X4_PAGE1 + 60)
|
||||
|
||||
#define AIC32X4_FREQ_12000000 12000000
|
||||
#define AIC32X4_FREQ_24000000 24000000
|
||||
#define AIC32X4_FREQ_25000000 25000000
|
||||
|
||||
#define AIC32X4_WORD_LEN_16BITS 0x00
|
||||
#define AIC32X4_WORD_LEN_20BITS 0x01
|
||||
#define AIC32X4_WORD_LEN_24BITS 0x02
|
||||
#define AIC32X4_WORD_LEN_32BITS 0x03
|
||||
|
||||
#define AIC32X4_I2S_MODE 0x00
|
||||
#define AIC32X4_DSP_MODE 0x01
|
||||
#define AIC32X4_RIGHT_JUSTIFIED_MODE 0x02
|
||||
#define AIC32X4_LEFT_JUSTIFIED_MODE 0x03
|
||||
|
||||
#define AIC32X4_AVDDWEAKDISABLE 0x08
|
||||
#define AIC32X4_LDOCTLEN 0x01
|
||||
|
||||
#define AIC32X4_LDOIN_18_36 0x01
|
||||
#define AIC32X4_LDOIN2HP 0x02
|
||||
|
||||
#define AIC32X4_DACSPBLOCK_MASK 0x1f
|
||||
#define AIC32X4_ADCSPBLOCK_MASK 0x1f
|
||||
|
||||
#define AIC32X4_PLLJ_SHIFT 6
|
||||
#define AIC32X4_DOSRMSB_SHIFT 4
|
||||
|
||||
#define AIC32X4_PLLCLKIN 0x03
|
||||
|
||||
#define AIC32X4_MICBIAS_LDOIN 0x08
|
||||
#define AIC32X4_MICBIAS_2075V 0x60
|
||||
|
||||
#define AIC32X4_LMICPGANIN_IN2R_10K 0x10
|
||||
#define AIC32X4_RMICPGANIN_IN1L_10K 0x10
|
||||
|
||||
#define AIC32X4_LMICPGAVOL_NOGAIN 0x80
|
||||
#define AIC32X4_RMICPGAVOL_NOGAIN 0x80
|
||||
|
||||
#define AIC32X4_BCLKMASTER 0x08
|
||||
#define AIC32X4_WCLKMASTER 0x04
|
||||
#define AIC32X4_PLLEN (0x01 << 7)
|
||||
#define AIC32X4_NDACEN (0x01 << 7)
|
||||
#define AIC32X4_MDACEN (0x01 << 7)
|
||||
#define AIC32X4_NADCEN (0x01 << 7)
|
||||
#define AIC32X4_MADCEN (0x01 << 7)
|
||||
#define AIC32X4_BCLKEN (0x01 << 7)
|
||||
#define AIC32X4_DACEN (0x03 << 6)
|
||||
#define AIC32X4_RDAC2LCHN (0x02 << 2)
|
||||
#define AIC32X4_LDAC2RCHN (0x02 << 4)
|
||||
#define AIC32X4_LDAC2LCHN (0x01 << 4)
|
||||
#define AIC32X4_RDAC2RCHN (0x01 << 2)
|
||||
|
||||
#define AIC32X4_SSTEP2WCLK 0x01
|
||||
#define AIC32X4_MUTEON 0x0C
|
||||
#define AIC32X4_DACMOD2BCLK 0x01
|
||||
|
||||
#endif /* _TLV320AIC32X4_H */
|
||||
Loading…
Reference in New Issue