iwlwifi: improve the reports in TX path
Also when things go wrong (queues don't get emtpy), try to get some data from the HW. Signed-off-by: Emmanuel Grumbach <emmanuel.grumbach@intel.com> Signed-off-by: Johannes Berg <johannes.berg@intel.com>
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ddaf5a5b30
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1c3fea82d6
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@ -521,9 +521,6 @@ static void iwlagn_mac_tx(struct ieee80211_hw *hw,
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{
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struct iwl_priv *priv = IWL_MAC80211_GET_DVM(hw);
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IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
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ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
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if (iwlagn_tx_skb(priv, control->sta, skb))
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ieee80211_free_txskb(hw, skb);
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}
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@ -231,13 +231,11 @@ static void iwlagn_tx_cmd_build_hwcrypto(struct iwl_priv *priv,
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memcpy(tx_cmd->key, keyconf->key, keyconf->keylen);
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if (info->flags & IEEE80211_TX_CTL_AMPDU)
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tx_cmd->tx_flags |= TX_CMD_FLG_AGG_CCMP_MSK;
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IWL_DEBUG_TX(priv, "tx_cmd with AES hwcrypto\n");
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break;
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case WLAN_CIPHER_SUITE_TKIP:
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tx_cmd->sec_ctl = TX_CMD_SEC_TKIP;
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ieee80211_get_tkip_p2k(keyconf, skb_frag, tx_cmd->key);
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IWL_DEBUG_TX(priv, "tx_cmd with tkip hwcrypto\n");
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break;
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case WLAN_CIPHER_SUITE_WEP104:
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@ -355,8 +353,6 @@ int iwlagn_tx_skb(struct iwl_priv *priv,
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}
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}
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IWL_DEBUG_TX(priv, "station Id %d\n", sta_id);
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if (sta)
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sta_priv = (void *)sta->drv_priv;
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@ -472,6 +468,9 @@ int iwlagn_tx_skb(struct iwl_priv *priv,
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WARN_ON_ONCE(is_agg &&
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priv->queue_to_mac80211[txq_id] != info->hw_queue);
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IWL_DEBUG_TX(priv, "TX to [%d|%d] Q:%d - seq: 0x%x\n", sta_id, tid,
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txq_id, seq_number);
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if (iwl_trans_tx(priv->trans, skb, dev_cmd, txq_id))
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goto drop_unlock_sta;
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@ -953,12 +952,6 @@ static void iwl_rx_reply_tx_agg(struct iwl_priv *priv,
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if (status & (AGG_TX_STATE_FEW_BYTES_MSK |
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AGG_TX_STATE_ABORT_MSK))
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continue;
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IWL_DEBUG_TX_REPLY(priv, "status %s (0x%08x), "
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"try-count (0x%08x)\n",
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iwl_get_agg_tx_fail_reason(fstatus),
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fstatus & AGG_TX_STATUS_MSK,
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fstatus & AGG_TX_TRY_MSK);
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}
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}
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@ -1212,16 +1205,27 @@ int iwlagn_rx_reply_tx(struct iwl_priv *priv, struct iwl_rx_cmd_buffer *rxb,
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freed++;
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}
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WARN_ON(!is_agg && freed != 1);
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if (!is_agg && freed != 1)
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IWL_ERR(priv, "Q: %d, freed %d\n", txq_id, freed);
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/*
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* An offchannel frame can be send only on the AUX queue, where
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* there is no aggregation (and reordering) so it only is single
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* skb is expected to be processed.
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*/
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WARN_ON(is_offchannel_skb && freed != 1);
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if (is_offchannel_skb && freed != 1)
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IWL_ERR(priv, "OFFCHANNEL SKB freed %d\n", freed);
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}
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IWL_DEBUG_TX_REPLY(priv, "TXQ %d status %s (0x%08x)\n", txq_id,
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iwl_get_tx_fail_reason(status), status);
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IWL_DEBUG_TX_REPLY(priv,
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"\t\t\t\tinitial_rate 0x%x retries %d, idx=%d ssn=%d seq_ctl=0x%x\n",
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le32_to_cpu(tx_resp->rate_n_flags),
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tx_resp->failure_frame, SEQ_TO_INDEX(sequence), ssn,
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le16_to_cpu(tx_resp->seq_ctl));
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iwl_check_abort_status(priv, tx_resp->frame_count, status);
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spin_unlock(&priv->sta_lock);
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@ -890,6 +890,8 @@ static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans)
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struct iwl_queue *q;
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int cnt;
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unsigned long now = jiffies;
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u32 scd_sram_addr;
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u8 buf[16];
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int ret = 0;
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/* waiting for all the tx frames complete might take a while */
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@ -903,11 +905,50 @@ static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans)
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msleep(1);
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if (q->read_ptr != q->write_ptr) {
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IWL_ERR(trans, "fail to flush all tx fifo queues\n");
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IWL_ERR(trans,
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"fail to flush all tx fifo queues Q %d\n", cnt);
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ret = -ETIMEDOUT;
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break;
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}
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}
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if (!ret)
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return 0;
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IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n",
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txq->q.read_ptr, txq->q.write_ptr);
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scd_sram_addr = trans_pcie->scd_base_addr +
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SCD_TX_STTS_QUEUE_OFFSET(txq->q.id);
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iwl_trans_read_mem_bytes(trans, scd_sram_addr, buf, sizeof(buf));
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iwl_print_hex_error(trans, buf, sizeof(buf));
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for (cnt = 0; cnt < FH_TCSR_CHNL_NUM; cnt++)
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IWL_ERR(trans, "FH TRBs(%d) = 0x%08x\n", cnt,
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iwl_read_direct32(trans, FH_TX_TRB_REG(cnt)));
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for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
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u32 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(cnt));
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u8 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7;
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bool active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE));
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u32 tbl_dw =
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iwl_trans_read_mem32(trans, trans_pcie->scd_base_addr +
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SCD_TRANS_TBL_OFFSET_QUEUE(cnt));
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if (cnt & 0x1)
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tbl_dw = (tbl_dw & 0xFFFF0000) >> 16;
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else
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tbl_dw = tbl_dw & 0x0000FFFF;
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IWL_ERR(trans,
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"Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n",
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cnt, active ? "" : "in", fifo, tbl_dw,
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iwl_read_prph(trans,
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SCD_QUEUE_RDPTR(cnt)) & (txq->q.n_bd - 1),
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iwl_read_prph(trans, SCD_QUEUE_WRPTR(cnt)));
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}
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return ret;
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}
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@ -309,6 +309,9 @@ void iwl_pcie_txq_inc_wr_ptr(struct iwl_trans *trans, struct iwl_txq *txq)
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return;
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}
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IWL_DEBUG_TX(trans, "Q:%d WR: 0x%x\n", txq_id,
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txq->q.write_ptr);
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iwl_write_direct32(trans, HBUS_TARG_WRPTR,
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txq->q.write_ptr | (txq_id << 8));
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@ -1660,10 +1663,6 @@ int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb,
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tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys);
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tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys);
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IWL_DEBUG_TX(trans, "sequence nr = 0X%x\n",
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le16_to_cpu(dev_cmd->hdr.sequence));
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IWL_DEBUG_TX(trans, "tx_flags = 0X%x\n", le32_to_cpu(tx_cmd->tx_flags));
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/* Set up entry for this TFD in Tx byte-count array */
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iwl_pcie_txq_update_byte_cnt_tbl(trans, txq, le16_to_cpu(tx_cmd->len));
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