Several fixes for the AVR32 PATA driver
Several fixes for the AVR32 PATA driver: * Updated to use new AVR32 SMC timing API. This removes the need for "magic" constants in signal timing. * Removed the ATA_FLAG_PIO_POLLING, the driver should use interrupts. * Removed .port_disable and .irq_ack as these are no longer needed. * Improved some comments. Signed-off-by: Kristoffer Nyborg Gregertsen <kngregertsen@norway.atmel.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
This commit is contained in:
Kristoffer Nyborg Gregertsen
Jeff Garzik
parent
2d79ab8fd7
commit
1c20a493ca
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@ -28,7 +28,7 @@
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#include <asm/arch/smc.h>
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#define DRV_NAME "pata_at32"
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#define DRV_VERSION "0.0.2"
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#define DRV_VERSION "0.0.3"
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/*
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* CompactFlash controller memory layout relative to the base address:
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@ -64,6 +64,8 @@
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* Mode 2 | 8.3 | 240 ns | 0x07
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* Mode 3 | 11.1 | 180 ns | 0x0f
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* Mode 4 | 16.7 | 120 ns | 0x1f
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*
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* Alter PIO_MASK below according to table to set maximal PIO mode.
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*/
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#define PIO_MASK (0x1f)
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@ -85,36 +87,40 @@ struct at32_ide_info {
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*/
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static int pata_at32_setup_timing(struct device *dev,
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struct at32_ide_info *info,
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const struct ata_timing *timing)
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const struct ata_timing *ata)
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{
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/* These two values are found through testing */
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const int min_recover = 25;
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const int ncs_hold = 15;
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struct smc_config *smc = &info->smc;
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struct smc_timing timing;
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int active;
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int recover;
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memset(&timing, 0, sizeof(struct smc_timing));
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/* Total cycle time */
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smc->read_cycle = timing->cyc8b;
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timing.read_cycle = ata->cyc8b;
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/* DIOR <= CFIOR timings */
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smc->nrd_setup = timing->setup;
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smc->nrd_pulse = timing->act8b;
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timing.nrd_setup = ata->setup;
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timing.nrd_pulse = ata->act8b;
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timing.nrd_recover = ata->rec8b;
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/* Compute recover, extend total cycle if needed */
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active = smc->nrd_setup + smc->nrd_pulse;
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/* Convert nanosecond timing to clock cycles */
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smc_set_timing(smc, &timing);
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/* Add one extra cycle setup due to signal ring */
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smc->nrd_setup = smc->nrd_setup + 1;
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active = smc->nrd_setup + smc->nrd_pulse;
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recover = smc->read_cycle - active;
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if (recover < min_recover) {
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smc->read_cycle = active + min_recover;
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recover = min_recover;
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}
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/* Need at least two cycles recovery */
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if (recover < 2)
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smc->read_cycle = active + 2;
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/* (CS0, CS1, DIR, OE) <= (CFCE1, CFCE2, CFRNW, NCSX) timings */
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smc->ncs_read_setup = 0;
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smc->ncs_read_pulse = active + ncs_hold;
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smc->ncs_read_setup = 1;
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smc->ncs_read_pulse = smc->read_cycle - 2;
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/* Write timings same as read timings */
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smc->write_cycle = smc->read_cycle;
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@ -123,11 +129,13 @@ static int pata_at32_setup_timing(struct device *dev,
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smc->ncs_write_setup = smc->ncs_read_setup;
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smc->ncs_write_pulse = smc->ncs_read_pulse;
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/* Do some debugging output */
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dev_dbg(dev, "SMC: C=%d S=%d P=%d R=%d NCSS=%d NCSP=%d NCSR=%d\n",
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/* Do some debugging output of ATA and SMC timings */
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dev_dbg(dev, "ATA: C=%d S=%d P=%d R=%d\n",
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ata->cyc8b, ata->setup, ata->act8b, ata->rec8b);
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dev_dbg(dev, "SMC: C=%d S=%d P=%d NS=%d NP=%d\n",
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smc->read_cycle, smc->nrd_setup, smc->nrd_pulse,
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recover, smc->ncs_read_setup, smc->ncs_read_pulse,
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smc->read_cycle - smc->ncs_read_pulse);
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smc->ncs_read_setup, smc->ncs_read_pulse);
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/* Finally, configure the SMC */
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return smc_set_configuration(info->cs, smc);
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@ -182,7 +190,6 @@ static struct scsi_host_template at32_sht = {
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};
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static struct ata_port_operations at32_port_ops = {
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.port_disable = ata_port_disable,
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.set_piomode = pata_at32_set_piomode,
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.tf_load = ata_tf_load,
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.tf_read = ata_tf_read,
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@ -203,7 +210,6 @@ static struct ata_port_operations at32_port_ops = {
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.irq_clear = pata_at32_irq_clear,
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.irq_on = ata_irq_on,
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.irq_ack = ata_irq_ack,
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.port_start = ata_sff_port_start,
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};
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@ -223,8 +229,7 @@ static int __init pata_at32_init_one(struct device *dev,
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/* Setup ATA bindings */
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ap->ops = &at32_port_ops;
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ap->pio_mask = PIO_MASK;
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ap->flags = ATA_FLAG_MMIO | ATA_FLAG_SLAVE_POSS
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| ATA_FLAG_PIO_POLLING;
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ap->flags |= ATA_FLAG_MMIO | ATA_FLAG_SLAVE_POSS;
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/*
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* Since all 8-bit taskfile transfers has to go on the lower
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@ -357,12 +362,12 @@ static int __init pata_at32_probe(struct platform_device *pdev)
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info->smc.tdf_mode = 0; /* TDF optimization disabled */
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info->smc.tdf_cycles = 0; /* No TDF wait cycles */
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/* Setup ATA timing */
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/* Setup SMC to ATA timing */
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ret = pata_at32_setup_timing(dev, info, &initial_timing);
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if (ret)
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goto err_setup_timing;
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/* Setup ATA addresses */
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/* Map ATA address space */
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ret = -ENOMEM;
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info->ide_addr = devm_ioremap(dev, info->res_ide.start, 16);
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info->alt_addr = devm_ioremap(dev, info->res_alt.start, 16);
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@ -373,7 +378,7 @@ static int __init pata_at32_probe(struct platform_device *pdev)
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pata_at32_debug_bus(dev, info);
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#endif
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/* Register ATA device */
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/* Setup and register ATA device */
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ret = pata_at32_init_one(dev, info);
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if (ret)
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goto err_ata_device;
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