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x86, intel-mid: remove Intel MID specific serial support 

Since we have a native 8250 driver carrying the Intel MID serial devices the
specific support is not needed anymore. This patch removes it for Intel MID.

Note that the console device name is changed from ttyMFDx to ttySx.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Ingo Molnar <mingo@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Andy Shevchenko 2015-02-23 16:24:44 +02:00 committed by Greg Kroah-Hartman
parent f549e94eff
commit 1bd187de53
10 changed files with 0 additions and 1708 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
arch/x86/Kconfig.debug
View File

@ -43,10 +43,6 @@ config EARLY_PRINTK
with klogd/syslogd or the X server. You should normally N here,
unless you want to debug such a crash.
config EARLY_PRINTK_INTEL_MID
bool "Early printk for Intel MID platform support"
depends on EARLY_PRINTK && X86_INTEL_MID
config EARLY_PRINTK_DBGP
bool "Early printk via EHCI debug port"
depends on EARLY_PRINTK && PCI

3
arch/x86/include/asm/intel-mid.h
View File

@ -136,9 +136,6 @@ extern enum intel_mid_timer_options intel_mid_timer_options;
#define SFI_MTMR_MAX_NUM 8
#define SFI_MRTC_MAX 8
extern struct console early_hsu_console;
extern void hsu_early_console_init(const char *);
extern void intel_scu_devices_create(void);
extern void intel_scu_devices_destroy(void);

6
arch/x86/kernel/early_printk.c
View File

@ -375,12 +375,6 @@ static int __init setup_early_printk(char *buf)
if (!strncmp(buf, "xen", 3))
early_console_register(&xenboot_console, keep);
#endif
#ifdef CONFIG_EARLY_PRINTK_INTEL_MID
if (!strncmp(buf, "hsu", 3)) {
hsu_early_console_init(buf + 3);
early_console_register(&early_hsu_console, keep);
}
#endif
#ifdef CONFIG_EARLY_PRINTK_EFI
if (!strncmp(buf, "efi", 3))
early_console_register(&early_efi_console, keep);

1
arch/x86/platform/intel-mid/Makefile
View File

@ -1,5 +1,4 @@
obj-$(CONFIG_X86_INTEL_MID) += intel-mid.o intel_mid_vrtc.o mfld.o mrfl.o
obj-$(CONFIG_EARLY_PRINTK_INTEL_MID) += early_printk_intel_mid.o
# SFI specific code
ifdef CONFIG_X86_INTEL_MID

112
arch/x86/platform/intel-mid/early_printk_intel_mid.c
View File

@ -1,112 +0,0 @@
/*
* early_printk_intel_mid.c - early consoles for Intel MID platforms
*
* Copyright (c) 2008-2010, Intel Corporation
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; version 2
* of the License.
*/
/*
* This file implements early console named hsu.
* hsu is based on a High Speed UART device which only exists in the Medfield
* platform
*/
#include <linux/serial_reg.h>
#include <linux/serial_mfd.h>
#include <linux/console.h>
#include <linux/kernel.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <asm/fixmap.h>
#include <asm/pgtable.h>
#include <asm/intel-mid.h>
/*
* Following is the early console based on Medfield HSU (High
* Speed UART) device.
*/
#define HSU_PORT_BASE 0xffa28080
static void __iomem *phsu;
void hsu_early_console_init(const char *s)
{
unsigned long paddr, port = 0;
u8 lcr;
/*
* Select the early HSU console port if specified by user in the
* kernel command line.
*/
if (*s && !kstrtoul(s, 10, &port))
port = clamp_val(port, 0, 2);
paddr = HSU_PORT_BASE + port * 0x80;
phsu = (void __iomem *)set_fixmap_offset_nocache(FIX_EARLYCON_MEM_BASE, paddr);
/* Disable FIFO */
writeb(0x0, phsu + UART_FCR);
/* Set to default 115200 bps, 8n1 */
lcr = readb(phsu + UART_LCR);
writeb((0x80 | lcr), phsu + UART_LCR);
writeb(0x18, phsu + UART_DLL);
writeb(lcr, phsu + UART_LCR);
writel(0x3600, phsu + UART_MUL*4);
writeb(0x8, phsu + UART_MCR);
writeb(0x7, phsu + UART_FCR);
writeb(0x3, phsu + UART_LCR);
/* Clear IRQ status */
readb(phsu + UART_LSR);
readb(phsu + UART_RX);
readb(phsu + UART_IIR);
readb(phsu + UART_MSR);
/* Enable FIFO */
writeb(0x7, phsu + UART_FCR);
}
#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
static void early_hsu_putc(char ch)
{
unsigned int timeout = 10000; /* 10ms */
u8 status;
while (--timeout) {
status = readb(phsu + UART_LSR);
if (status & BOTH_EMPTY)
break;
udelay(1);
}
/* Only write the char when there was no timeout */
if (timeout)
writeb(ch, phsu + UART_TX);
}
static void early_hsu_write(struct console *con, const char *str, unsigned n)
{
int i;
for (i = 0; i < n && *str; i++) {
if (*str == '\n')
early_hsu_putc('\r');
early_hsu_putc(*str);
str++;
}
}
struct console early_hsu_console = {
.name = "earlyhsu",
.write = early_hsu_write,
.flags = CON_PRINTBUFFER,
.index = -1,
};

10
drivers/tty/serial/Kconfig
View File

@ -483,16 +483,6 @@ config SERIAL_SA1100_CONSOLE
your boot loader (lilo or loadlin) about how to pass options to the
kernel at boot time.)
config SERIAL_MFD_HSU
tristate "Medfield High Speed UART support"
depends on PCI
select SERIAL_CORE
config SERIAL_MFD_HSU_CONSOLE
bool "Medfield HSU serial console support"
depends on SERIAL_MFD_HSU=y
select SERIAL_CORE_CONSOLE
config SERIAL_BFIN
tristate "Blackfin serial port support"
depends on BLACKFIN

1
drivers/tty/serial/Makefile
View File

@ -78,7 +78,6 @@ obj-$(CONFIG_SERIAL_TIMBERDALE) += timbuart.o
obj-$(CONFIG_SERIAL_GRLIB_GAISLER_APBUART) += apbuart.o
obj-$(CONFIG_SERIAL_ALTERA_JTAGUART) += altera_jtaguart.o
obj-$(CONFIG_SERIAL_VT8500) += vt8500_serial.o
obj-$(CONFIG_SERIAL_MFD_HSU) += mfd.o
obj-$(CONFIG_SERIAL_IFX6X60) += ifx6x60.o
obj-$(CONFIG_SERIAL_PCH_UART) += pch_uart.o
obj-$(CONFIG_SERIAL_MSM_SMD) += msm_smd_tty.o

1505
drivers/tty/serial/mfd.c
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File diff suppressed because it is too large Load Diff

47
include/linux/serial_mfd.h
View File

@ -1,47 +0,0 @@
#ifndef _SERIAL_MFD_H_
#define _SERIAL_MFD_H_
/* HW register offset definition */
#define UART_FOR 0x08
#define UART_PS 0x0C
#define UART_MUL 0x0D
#define UART_DIV 0x0E
#define HSU_GBL_IEN 0x0
#define HSU_GBL_IST 0x4
#define HSU_GBL_INT_BIT_PORT0 0x0
#define HSU_GBL_INT_BIT_PORT1 0x1
#define HSU_GBL_INT_BIT_PORT2 0x2
#define HSU_GBL_INT_BIT_IRI 0x3
#define HSU_GBL_INT_BIT_HDLC 0x4
#define HSU_GBL_INT_BIT_DMA 0x5
#define HSU_GBL_ISR 0x8
#define HSU_GBL_DMASR 0x400
#define HSU_GBL_DMAISR 0x404
#define HSU_PORT_REG_OFFSET 0x80
#define HSU_PORT0_REG_OFFSET 0x80
#define HSU_PORT1_REG_OFFSET 0x100
#define HSU_PORT2_REG_OFFSET 0x180
#define HSU_PORT_REG_LENGTH 0x80
#define HSU_DMA_CHANS_REG_OFFSET 0x500
#define HSU_DMA_CHANS_REG_LENGTH 0x40
#define HSU_CH_SR 0x0 /* channel status reg */
#define HSU_CH_CR 0x4 /* control reg */
#define HSU_CH_DCR 0x8 /* descriptor control reg */
#define HSU_CH_BSR 0x10 /* max fifo buffer size reg */
#define HSU_CH_MOTSR 0x14 /* minimum ocp transfer size */
#define HSU_CH_D0SAR 0x20 /* desc 0 start addr */
#define HSU_CH_D0TSR 0x24 /* desc 0 transfer size */
#define HSU_CH_D1SAR 0x28
#define HSU_CH_D1TSR 0x2C
#define HSU_CH_D2SAR 0x30
#define HSU_CH_D2TSR 0x34
#define HSU_CH_D3SAR 0x38
#define HSU_CH_D3TSR 0x3C
#endif

19
include/uapi/linux/serial_reg.h
View File

@ -241,25 +241,6 @@
#define UART_FCR_PXAR16 0x80 /* receive FIFO threshold = 16 */
#define UART_FCR_PXAR32 0xc0 /* receive FIFO threshold = 32 */
/*
* Intel MID on-chip HSU (High Speed UART) defined bits
*/
#define UART_FCR_HSU_64_1B 0x00 /* receive FIFO treshold = 1 */
#define UART_FCR_HSU_64_16B 0x40 /* receive FIFO treshold = 16 */
#define UART_FCR_HSU_64_32B 0x80 /* receive FIFO treshold = 32 */
#define UART_FCR_HSU_64_56B 0xc0 /* receive FIFO treshold = 56 */
#define UART_FCR_HSU_16_1B 0x00 /* receive FIFO treshold = 1 */
#define UART_FCR_HSU_16_4B 0x40 /* receive FIFO treshold = 4 */
#define UART_FCR_HSU_16_8B 0x80 /* receive FIFO treshold = 8 */
#define UART_FCR_HSU_16_14B 0xc0 /* receive FIFO treshold = 14 */
#define UART_FCR_HSU_64B_FIFO 0x20 /* chose 64 bytes FIFO */
#define UART_FCR_HSU_16B_FIFO 0x00 /* chose 16 bytes FIFO */
#define UART_FCR_HALF_EMPT_TXI 0x00 /* trigger TX_EMPT IRQ for half empty */
#define UART_FCR_FULL_EMPT_TXI 0x08 /* trigger TX_EMPT IRQ for full empty */
/*
* These register definitions are for the 16C950
*/