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arm64: tegra: Device tree changes for v5.19-rc1 

This adds some improvements on Tegra234 (QSPI, CCPLEX), improves the
 SDMMC clock speed on Tegra194 and adds the ASRC audio block on various
 chip generations. Memory controller channels are also added on Tegra186
 and later and the missing DFLL reset is added for Tegra210.
 -----BEGIN PGP SIGNATURE-----
 
 iQJHBAABCAAxFiEEiOrDCAFJzPfAjcif3SOs138+s6EFAmJ1LsgTHHRyZWRpbmdA
 bnZpZGlhLmNvbQAKCRDdI6zXfz6zoZKcD/4rxLjWUWGLqTxg1ZtMpWgWpqQAOgn1
 lCQCcK75WFOSXWhzFVlvxvDff5RS80vDXHNS9mPT5S9uI2PiqiHKY6v/fOQkddI4
 Gk78BGbAtSzCUCoTKYf/iWdiNYhYU7SfgxdZplb8JLAsRCbgxirbnBD+QkMvD4T3
 ksTAgUUDespZzJ4NksNWMCWC2iehQu594sXWbMzMTxojC5i1QlanEfX8yg3C5O8C
 c+NpA9q/JHYg1MiSoDP7Co4Kgj8Bfu0Fxm8DGsaNKSMVh6Ai45TC/5ED7gCBkgLA
 ObaMQcb6gOnco5LdCAipDMyKml1qiK3YiOa+92CnWocMMWMbg1dlQ8IBoacycOgj
 hV6/egdcMtmzIK9rj4fGVFH3zbkqw2JeY0IWtZH+5zgJZjsCofIK0PsmgPIewEnj
 iglEuAWmV4qev/8KB2cbcpRiggLKBZ1o3lpOatKNugNy/T4Aie1C/2tfUEV0Ie07
 n/9EkgHHlSXZGwI7zvFwTeiI/IOIySg2BVZsQi//0QVRsj7w9cKv+mHoQ/bZZQFc
 nXhiMEHhKuWDhbRrlpshI1XUJ5knGz9lCJPrcRV8/9rL0A4zDH+IfH966Jpdepo5
 Qh8MdncxOlrflZTOLhbOjemyCU8ieahu8yTcpziyUHqKcxKXDnjJXC6Cg0TpeuX3
 QDuWvinVDDHoLw==
 =KBZh
 -----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmJ1h4sACgkQmmx57+YA
 GNmbcBAAj+oXraktDfkgmiEg2vcBS92H/ik/09RdifgTomjEQMHNpB+Kp+c6xXuh
 rHZU/HMqNuuVImmZImTDGqYKXzJMsEckIzBWiXsIP3vNNooJbWyDC5YxPftZqCED
 tfXfra0U6hCumX03o9l6Tywf2pfawxsO28QFE+xGffKHa53GruIYkj62prXCJWqD
 GOcCoBkqulNPVoIsQAtCp3JNxnvR3JmYxNlCdbIrTp6zGnhYsMyLFeEdcamS1rCO
 ZyQ//byFjhTGWr5e3w3LD4ZPekAFN0elWXGLjyz+oitxIAm/jL/4JpZwkbL+qS35
 MDO57gQB/nc5wfM2Ojm3rIk2Vs0DeX3V92TcSKPVTqHPqciySb1ftDa5CLzRPyCQ
 fcLxZHWP1YTHvfcSG0MQLhixp3GW8OhJiSQElqjhWE4LpNmWreElnFAxZ9oiiDTb
 58xnU4vaYb7RzqZVmyXuBWaxXH5NQKjri+OFGjbqvH9CI+KVQeH2829otEhbHTad
 nfBeoZqp9CjzY9ejBWFduCeXLEDO52HGa33BDkJPeO/PENmgmDBZMxo+hJOL2ZZx
 htpHFlllj0eC/QomGp9zJfadZbslRGigWr9X868whDROhBlL/onFh6iEqPmREhTv
 M4waPbQynA9928AfYFSxXJmUdvbusxvppU1e4eISWWzC3DyHlHE=
 =wsbV
 -----END PGP SIGNATURE-----

Merge tag 'tegra-for-5.19-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/dt

arm64: tegra: Device tree changes for v5.19-rc1

This adds some improvements on Tegra234 (QSPI, CCPLEX), improves the
SDMMC clock speed on Tegra194 and adds the ASRC audio block on various
chip generations. Memory controller channels are also added on Tegra186
and later and the missing DFLL reset is added for Tegra210.

* tag 'tegra-for-5.19-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
  arm64: tegra: Add missing DFLL reset on Tegra210
  arm64: tegra: Add memory controller channels
  arm64: tegra: Enable ASRC on various platforms
  arm64: tegra: Add ASRC device on Tegra186 and later
  arm64: tegra: Update PWM fan node name
  arm64: tegra: Add node for Tegra234 CCPLEX cluster
  arm64: tegra: Add QSPI controllers on Tegra234
  arm64: tegra: Update SDMMC1/3 clock source for Tegra194

Link: https://lore.kernel.org/r/20220506143005.3916655-5-thierry.reding@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2022-05-06 22:39:39 +02:00
parent 72a21285a7 0017f2c856
commit 1bc44c1e79
13 changed files with 1038 additions and 13 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

223
arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts
View File

@ -811,6 +811,110 @@
remote-endpoint = <&mixer_out5_ep>;
};
};
xbar_asrc_in1_port: port@63 {
reg = <0x63>;
xbar_asrc_in1_ep: endpoint {
remote-endpoint = <&asrc_in1_ep>;
};
};
port@64 {
reg = <0x64>;
xbar_asrc_out1_ep: endpoint {
remote-endpoint = <&asrc_out1_ep>;
};
};
xbar_asrc_in2_port: port@65 {
reg = <0x65>;
xbar_asrc_in2_ep: endpoint {
remote-endpoint = <&asrc_in2_ep>;
};
};
port@66 {
reg = <0x66>;
xbar_asrc_out2_ep: endpoint {
remote-endpoint = <&asrc_out2_ep>;
};
};
xbar_asrc_in3_port: port@67 {
reg = <0x67>;
xbar_asrc_in3_ep: endpoint {
remote-endpoint = <&asrc_in3_ep>;
};
};
port@68 {
reg = <0x68>;
xbar_asrc_out3_ep: endpoint {
remote-endpoint = <&asrc_out3_ep>;
};
};
xbar_asrc_in4_port: port@69 {
reg = <0x69>;
xbar_asrc_in4_ep: endpoint {
remote-endpoint = <&asrc_in4_ep>;
};
};
port@6a {
reg = <0x6a>;
xbar_asrc_out4_ep: endpoint {
remote-endpoint = <&asrc_out4_ep>;
};
};
xbar_asrc_in5_port: port@6b {
reg = <0x6b>;
xbar_asrc_in5_ep: endpoint {
remote-endpoint = <&asrc_in5_ep>;
};
};
port@6c {
reg = <0x6c>;
xbar_asrc_out5_ep: endpoint {
remote-endpoint = <&asrc_out5_ep>;
};
};
xbar_asrc_in6_port: port@6d {
reg = <0x6d>;
xbar_asrc_in6_ep: endpoint {
remote-endpoint = <&asrc_in6_ep>;
};
};
port@6e {
reg = <0x6e>;
xbar_asrc_out6_ep: endpoint {
remote-endpoint = <&asrc_out6_ep>;
};
};
xbar_asrc_in7_port: port@6f {
reg = <0x6f>;
xbar_asrc_in7_ep: endpoint {
remote-endpoint = <&asrc_in7_ep>;
};
};
};
admaif@290f000 {
@ -1935,6 +2039,119 @@
};
};
};
asrc@2910000 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0x0>;
asrc_in1_ep: endpoint {
remote-endpoint = <&xbar_asrc_in1_ep>;
};
};
port@1 {
reg = <0x1>;
asrc_in2_ep: endpoint {
remote-endpoint = <&xbar_asrc_in2_ep>;
};
};
port@2 {
reg = <0x2>;
asrc_in3_ep: endpoint {
remote-endpoint = <&xbar_asrc_in3_ep>;
};
};
port@3 {
reg = <0x3>;
asrc_in4_ep: endpoint {
remote-endpoint = <&xbar_asrc_in4_ep>;
};
};
port@4 {
reg = <0x4>;
asrc_in5_ep: endpoint {
remote-endpoint = <&xbar_asrc_in5_ep>;
};
};
port@5 {
reg = <0x5>;
asrc_in6_ep: endpoint {
remote-endpoint = <&xbar_asrc_in6_ep>;
};
};
port@6 {
reg = <0x6>;
asrc_in7_ep: endpoint {
remote-endpoint = <&xbar_asrc_in7_ep>;
};
};
asrc_out1_port: port@7 {
reg = <0x7>;
asrc_out1_ep: endpoint {
remote-endpoint = <&xbar_asrc_out1_ep>;
};
};
asrc_out2_port: port@8 {
reg = <0x8>;
asrc_out2_ep: endpoint {
remote-endpoint = <&xbar_asrc_out2_ep>;
};
};
asrc_out3_port: port@9 {
reg = <0x9>;
asrc_out3_ep: endpoint {
remote-endpoint = <&xbar_asrc_out3_ep>;
};
};
asrc_out4_port: port@a {
reg = <0xa>;
asrc_out4_ep: endpoint {
remote-endpoint = <&xbar_asrc_out4_ep>;
};
};
asrc_out5_port: port@b {
reg = <0xb>;
asrc_out5_ep: endpoint {
remote-endpoint = <&xbar_asrc_out5_ep>;
};
};
asrc_out6_port: port@c {
reg = <0xc>;
asrc_out6_ep: endpoint {
remote-endpoint = <&xbar_asrc_out6_ep>;
};
};
};
};
};
};
@ -2331,6 +2548,10 @@
<&xbar_mixer_in5_port>, <&xbar_mixer_in6_port>,
<&xbar_mixer_in7_port>, <&xbar_mixer_in8_port>,
<&xbar_mixer_in9_port>, <&xbar_mixer_in10_port>,
<&xbar_asrc_in1_port>, <&xbar_asrc_in2_port>,
<&xbar_asrc_in3_port>, <&xbar_asrc_in4_port>,
<&xbar_asrc_in5_port>, <&xbar_asrc_in6_port>,
<&xbar_asrc_in7_port>,
/* HW accelerators */
<&sfc1_out_port>, <&sfc2_out_port>,
<&sfc3_out_port>, <&sfc4_out_port>,
@ -2348,6 +2569,8 @@
<&mixer_out1_port>, <&mixer_out2_port>,
<&mixer_out3_port>, <&mixer_out4_port>,
<&mixer_out5_port>,
<&asrc_out1_port>, <&asrc_out2_port>, <&asrc_out3_port>,
<&asrc_out4_port>, <&asrc_out5_port>, <&asrc_out6_port>,
/* I/O */
<&i2s1_port>, <&i2s2_port>, <&i2s3_port>, <&i2s4_port>,
<&i2s5_port>, <&i2s6_port>, <&dmic1_port>, <&dmic2_port>,

2
arch/arm64/boot/dts/nvidia/tegra186-p3509-0000+p3636-0001.dts
View File

@ -349,7 +349,7 @@
status = "okay";
};
fan: fan {
fan: pwm-fan {
compatible = "pwm-fan";
pwms = <&pwm4 0 45334>;

15
arch/arm64/boot/dts/nvidia/tegra186.dtsi
View File

@ -516,12 +516,25 @@
sound-name-prefix = "MIXER1";
status = "disabled";
};
tegra_asrc: asrc@2910000 {
compatible = "nvidia,tegra186-asrc";
reg = <0x2910000 0x2000>;
sound-name-prefix = "ASRC1";
status = "disabled";
};
};
};
mc: memory-controller@2c00000 {
compatible = "nvidia,tegra186-mc";
reg = <0x0 0x02c00000 0x0 0xb0000>;
reg = <0x0 0x02c00000 0x0 0x10000>, /* MC-SID */
<0x0 0x02c10000 0x0 0x10000>, /* Broadcast channel */
<0x0 0x02c20000 0x0 0x10000>, /* MC0 */
<0x0 0x02c30000 0x0 0x10000>, /* MC1 */
<0x0 0x02c40000 0x0 0x10000>, /* MC2 */
<0x0 0x02c50000 0x0 0x10000>; /* MC3 */
reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3";
interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";

225
arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts
View File

@ -764,6 +764,110 @@
remote-endpoint = <&mixer_out5_ep>;
};
};
xbar_asrc_in1_port: port@63 {
reg = <0x63>;
xbar_asrc_in1_ep: endpoint {
remote-endpoint = <&asrc_in1_ep>;
};
};
port@64 {
reg = <0x64>;
xbar_asrc_out1_ep: endpoint {
remote-endpoint = <&asrc_out1_ep>;
};
};
xbar_asrc_in2_port: port@65 {
reg = <0x65>;
xbar_asrc_in2_ep: endpoint {
remote-endpoint = <&asrc_in2_ep>;
};
};
port@66 {
reg = <0x66>;
xbar_asrc_out2_ep: endpoint {
remote-endpoint = <&asrc_out2_ep>;
};
};
xbar_asrc_in3_port: port@67 {
reg = <0x67>;
xbar_asrc_in3_ep: endpoint {
remote-endpoint = <&asrc_in3_ep>;
};
};
port@68 {
reg = <0x68>;
xbar_asrc_out3_ep: endpoint {
remote-endpoint = <&asrc_out3_ep>;
};
};
xbar_asrc_in4_port: port@69 {
reg = <0x69>;
xbar_asrc_in4_ep: endpoint {
remote-endpoint = <&asrc_in4_ep>;
};
};
port@6a {
reg = <0x6a>;
xbar_asrc_out4_ep: endpoint {
remote-endpoint = <&asrc_out4_ep>;
};
};
xbar_asrc_in5_port: port@6b {
reg = <0x6b>;
xbar_asrc_in5_ep: endpoint {
remote-endpoint = <&asrc_in5_ep>;
};
};
port@6c {
reg = <0x6c>;
xbar_asrc_out5_ep: endpoint {
remote-endpoint = <&asrc_out5_ep>;
};
};
xbar_asrc_in6_port: port@6d {
reg = <0x6d>;
xbar_asrc_in6_ep: endpoint {
remote-endpoint = <&asrc_in6_ep>;
};
};
port@6e {
reg = <0x6e>;
xbar_asrc_out6_ep: endpoint {
remote-endpoint = <&asrc_out6_ep>;
};
};
xbar_asrc_in7_port: port@6f {
reg = <0x6f>;
xbar_asrc_in7_ep: endpoint {
remote-endpoint = <&asrc_in7_ep>;
};
};
};
admaif@290f000 {
@ -1734,6 +1838,119 @@
};
};
};
asrc@2910000 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0x0>;
asrc_in1_ep: endpoint {
remote-endpoint = <&xbar_asrc_in1_ep>;
};
};
port@1 {
reg = <0x1>;
asrc_in2_ep: endpoint {
remote-endpoint = <&xbar_asrc_in2_ep>;
};
};
port@2 {
reg = <0x2>;
asrc_in3_ep: endpoint {
remote-endpoint = <&xbar_asrc_in3_ep>;
};
};
port@3 {
reg = <0x3>;
asrc_in4_ep: endpoint {
remote-endpoint = <&xbar_asrc_in4_ep>;
};
};
port@4 {
reg = <0x4>;
asrc_in5_ep: endpoint {
remote-endpoint = <&xbar_asrc_in5_ep>;
};
};
port@5 {
reg = <0x5>;
asrc_in6_ep: endpoint {
remote-endpoint = <&xbar_asrc_in6_ep>;
};
};
port@6 {
reg = <0x6>;
asrc_in7_ep: endpoint {
remote-endpoint = <&xbar_asrc_in7_ep>;
};
};
asrc_out1_port: port@7 {
reg = <0x7>;
asrc_out1_ep: endpoint {
remote-endpoint = <&xbar_asrc_out1_ep>;
};
};
asrc_out2_port: port@8 {
reg = <0x8>;
asrc_out2_ep: endpoint {
remote-endpoint = <&xbar_asrc_out2_ep>;
};
};
asrc_out3_port: port@9 {
reg = <0x9>;
asrc_out3_ep: endpoint {
remote-endpoint = <&xbar_asrc_out3_ep>;
};
};
asrc_out4_port: port@a {
reg = <0xa>;
asrc_out4_ep: endpoint {
remote-endpoint = <&xbar_asrc_out4_ep>;
};
};
asrc_out5_port: port@b {
reg = <0xb>;
asrc_out5_ep: endpoint {
remote-endpoint = <&xbar_asrc_out5_ep>;
};
};
asrc_out6_port: port@c {
reg = <0xc>;
asrc_out6_ep: endpoint {
remote-endpoint = <&xbar_asrc_out6_ep>;
};
};
};
};
};
};
@ -1989,7 +2206,7 @@
"p2u-5", "p2u-6", "p2u-7";
};
fan: fan {
fan: pwm-fan {
compatible = "pwm-fan";
pwms = <&pwm4 0 45334>;
@ -2052,6 +2269,10 @@
<&xbar_mixer_in5_port>, <&xbar_mixer_in6_port>,
<&xbar_mixer_in7_port>, <&xbar_mixer_in8_port>,
<&xbar_mixer_in9_port>, <&xbar_mixer_in10_port>,
<&xbar_asrc_in1_port>, <&xbar_asrc_in2_port>,
<&xbar_asrc_in3_port>, <&xbar_asrc_in4_port>,
<&xbar_asrc_in5_port>, <&xbar_asrc_in6_port>,
<&xbar_asrc_in7_port>,
/* HW accelerators */
<&sfc1_out_port>, <&sfc2_out_port>,
<&sfc3_out_port>, <&sfc4_out_port>,
@ -2068,6 +2289,8 @@
<&adx4_out3_port>, <&adx4_out4_port>,
<&mixer_out1_port>, <&mixer_out2_port>, <&mixer_out3_port>,
<&mixer_out4_port>, <&mixer_out5_port>,
<&asrc_out1_port>, <&asrc_out2_port>, <&asrc_out3_port>,
<&asrc_out4_port>, <&asrc_out5_port>, <&asrc_out6_port>,
/* BE I/O Ports */
<&i2s1_port>, <&i2s2_port>, <&i2s4_port>, <&i2s6_port>,
<&dmic3_port>;

225
arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi
View File

@ -774,6 +774,110 @@
remote-endpoint = <&mixer_out5_ep>;
};
};
xbar_asrc_in1_port: port@63 {
reg = <0x63>;
xbar_asrc_in1_ep: endpoint {
remote-endpoint = <&asrc_in1_ep>;
};
};
port@64 {
reg = <0x64>;
xbar_asrc_out1_ep: endpoint {
remote-endpoint = <&asrc_out1_ep>;
};
};
xbar_asrc_in2_port: port@65 {
reg = <0x65>;
xbar_asrc_in2_ep: endpoint {
remote-endpoint = <&asrc_in2_ep>;
};
};
port@66 {
reg = <0x66>;
xbar_asrc_out2_ep: endpoint {
remote-endpoint = <&asrc_out2_ep>;
};
};
xbar_asrc_in3_port: port@67 {
reg = <0x67>;
xbar_asrc_in3_ep: endpoint {
remote-endpoint = <&asrc_in3_ep>;
};
};
port@68 {
reg = <0x68>;
xbar_asrc_out3_ep: endpoint {
remote-endpoint = <&asrc_out3_ep>;
};
};
xbar_asrc_in4_port: port@69 {
reg = <0x69>;
xbar_asrc_in4_ep: endpoint {
remote-endpoint = <&asrc_in4_ep>;
};
};
port@6a {
reg = <0x6a>;
xbar_asrc_out4_ep: endpoint {
remote-endpoint = <&asrc_out4_ep>;
};
};
xbar_asrc_in5_port: port@6b {
reg = <0x6b>;
xbar_asrc_in5_ep: endpoint {
remote-endpoint = <&asrc_in5_ep>;
};
};
port@6c {
reg = <0x6c>;
xbar_asrc_out5_ep: endpoint {
remote-endpoint = <&asrc_out5_ep>;
};
};
xbar_asrc_in6_port: port@6d {
reg = <0x6d>;
xbar_asrc_in6_ep: endpoint {
remote-endpoint = <&asrc_in6_ep>;
};
};
port@6e {
reg = <0x6e>;
xbar_asrc_out6_ep: endpoint {
remote-endpoint = <&asrc_out6_ep>;
};
};
xbar_asrc_in7_port: port@6f {
reg = <0x6f>;
xbar_asrc_in7_ep: endpoint {
remote-endpoint = <&asrc_in7_ep>;
};
};
};
admaif@290f000 {
@ -1794,6 +1898,119 @@
};
};
};
asrc@2910000 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0x0>;
asrc_in1_ep: endpoint {
remote-endpoint = <&xbar_asrc_in1_ep>;
};
};
port@1 {
reg = <0x1>;
asrc_in2_ep: endpoint {
remote-endpoint = <&xbar_asrc_in2_ep>;
};
};
port@2 {
reg = <0x2>;
asrc_in3_ep: endpoint {
remote-endpoint = <&xbar_asrc_in3_ep>;
};
};
port@3 {
reg = <0x3>;
asrc_in4_ep: endpoint {
remote-endpoint = <&xbar_asrc_in4_ep>;
};
};
port@4 {
reg = <0x4>;
asrc_in5_ep: endpoint {
remote-endpoint = <&xbar_asrc_in5_ep>;
};
};
port@5 {
reg = <0x5>;
asrc_in6_ep: endpoint {
remote-endpoint = <&xbar_asrc_in6_ep>;
};
};
port@6 {
reg = <0x6>;
asrc_in7_ep: endpoint {
remote-endpoint = <&xbar_asrc_in7_ep>;
};
};
asrc_out1_port: port@7 {
reg = <0x7>;
asrc_out1_ep: endpoint {
remote-endpoint = <&xbar_asrc_out1_ep>;
};
};
asrc_out2_port: port@8 {
reg = <0x8>;
asrc_out2_ep: endpoint {
remote-endpoint = <&xbar_asrc_out2_ep>;
};
};
asrc_out3_port: port@9 {
reg = <0x9>;
asrc_out3_ep: endpoint {
remote-endpoint = <&xbar_asrc_out3_ep>;
};
};
asrc_out4_port: port@a {
reg = <0xa>;
asrc_out4_ep: endpoint {
remote-endpoint = <&xbar_asrc_out4_ep>;
};
};
asrc_out5_port: port@b {
reg = <0xb>;
asrc_out5_ep: endpoint {
remote-endpoint = <&xbar_asrc_out5_ep>;
};
};
asrc_out6_port: port@c {
reg = <0xc>;
asrc_out6_ep: endpoint {
remote-endpoint = <&xbar_asrc_out6_ep>;
};
};
};
};
};
};
@ -1993,7 +2210,7 @@
"p2u-5", "p2u-6", "p2u-7";
};
fan: fan {
fan: pwm-fan {
compatible = "pwm-fan";
pwms = <&pwm6 0 45334>;
@ -2102,6 +2319,10 @@
<&xbar_mixer_in5_port>, <&xbar_mixer_in6_port>,
<&xbar_mixer_in7_port>, <&xbar_mixer_in8_port>,
<&xbar_mixer_in9_port>, <&xbar_mixer_in10_port>,
<&xbar_asrc_in1_port>, <&xbar_asrc_in2_port>,
<&xbar_asrc_in3_port>, <&xbar_asrc_in4_port>,
<&xbar_asrc_in5_port>, <&xbar_asrc_in6_port>,
<&xbar_asrc_in7_port>,
/* HW accelerators */
<&sfc1_out_port>, <&sfc2_out_port>,
<&sfc3_out_port>, <&sfc4_out_port>,
@ -2119,6 +2340,8 @@
<&mixer_out1_port>, <&mixer_out2_port>,
<&mixer_out3_port>, <&mixer_out4_port>,
<&mixer_out5_port>,
<&asrc_out1_port>, <&asrc_out2_port>, <&asrc_out3_port>,
<&asrc_out4_port>, <&asrc_out5_port>, <&asrc_out6_port>,
/* BE I/O Ports */
<&i2s3_port>, <&i2s5_port>,
<&dmic1_port>, <&dmic2_port>, <&dmic4_port>,

42
arch/arm64/boot/dts/nvidia/tegra194.dtsi
View File

@ -569,6 +569,14 @@
sound-name-prefix = "MIXER1";
status = "disabled";
};
tegra_asrc: asrc@2910000 {
compatible = "nvidia,tegra194-asrc",
"nvidia,tegra186-asrc";
reg = <0x2910000 0x2000>;
sound-name-prefix = "ASRC1";
status = "disabled";
};
};
};
@ -604,9 +612,27 @@
mc: memory-controller@2c00000 {
compatible = "nvidia,tegra194-mc";
reg = <0x02c00000 0x100000>,
<0x02b80000 0x040000>,
<0x01700000 0x100000>;
reg = <0x02c00000 0x10000>, /* MC-SID */
<0x02c10000 0x10000>, /* MC Broadcast*/
<0x02c20000 0x10000>, /* MC0 */
<0x02c30000 0x10000>, /* MC1 */
<0x02c40000 0x10000>, /* MC2 */
<0x02c50000 0x10000>, /* MC3 */
<0x02b80000 0x10000>, /* MC4 */
<0x02b90000 0x10000>, /* MC5 */
<0x02ba0000 0x10000>, /* MC6 */
<0x02bb0000 0x10000>, /* MC7 */
<0x01700000 0x10000>, /* MC8 */
<0x01710000 0x10000>, /* MC9 */
<0x01720000 0x10000>, /* MC10 */
<0x01730000 0x10000>, /* MC11 */
<0x01740000 0x10000>, /* MC12 */
<0x01750000 0x10000>, /* MC13 */
<0x01760000 0x10000>, /* MC14 */
<0x01770000 0x10000>; /* MC15 */
reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10",
"ch11", "ch12", "ch13", "ch14", "ch15";
interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
#interconnect-cells = <1>;
status = "disabled";
@ -934,6 +960,11 @@
clocks = <&bpmp TEGRA194_CLK_SDMMC1>,
<&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>;
clock-names = "sdhci", "tmclk";
assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC1>,
<&bpmp TEGRA194_CLK_PLLC4_MUXED>;
assigned-clock-parents =
<&bpmp TEGRA194_CLK_PLLC4_MUXED>,
<&bpmp TEGRA194_CLK_PLLC4_VCO_DIV2>;
resets = <&bpmp TEGRA194_RESET_SDMMC1>;
reset-names = "sdhci";
interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRA &emc>,
@ -968,6 +999,11 @@
clocks = <&bpmp TEGRA194_CLK_SDMMC3>,
<&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>;
clock-names = "sdhci", "tmclk";
assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC3>,
<&bpmp TEGRA194_CLK_PLLC4_MUXED>;
assigned-clock-parents =
<&bpmp TEGRA194_CLK_PLLC4_MUXED>,
<&bpmp TEGRA194_CLK_PLLC4_VCO_DIV2>;
resets = <&bpmp TEGRA194_RESET_SDMMC3>;
reset-names = "sdhci";
interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCR &emc>,

2
arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts
View File

@ -1657,7 +1657,7 @@
};
};
fan: fan {
fan: pwm-fan {
compatible = "pwm-fan";
pwms = <&pwm 3 45334>;

5
arch/arm64/boot/dts/nvidia/tegra210.dtsi
View File

@ -1366,8 +1366,9 @@
<&tegra_car TEGRA210_CLK_DFLL_REF>,
<&tegra_car TEGRA210_CLK_I2C5>;
clock-names = "soc", "ref", "i2c";
resets = <&tegra_car TEGRA210_RST_DFLL_DVCO>;
reset-names = "dvco";
resets = <&tegra_car TEGRA210_RST_DFLL_DVCO>,
<&tegra_car 155>;
reset-names = "dvco", "dfll";
#clock-cells = <0>;
clock-output-names = "dfllCPU_out";
status = "disabled";

12
arch/arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi
View File

@ -7,6 +7,18 @@
compatible = "nvidia,p3701-0000", "nvidia,tegra234";
bus@0 {
spi@3270000 {
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <102000000>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
};
};
mmc@3460000 {
status = "okay";
bus-width = <8>;

223
arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts
View File

@ -763,6 +763,110 @@
remote-endpoint = <&mix_out5>;
};
};
xbar_asrc_in1_port: port@63 {
reg = <0x63>;
xbar_asrc_in1_ep: endpoint {
remote-endpoint = <&asrc_in1_ep>;
};
};
port@64 {
reg = <0x64>;
xbar_asrc_out1_ep: endpoint {
remote-endpoint = <&asrc_out1_ep>;
};
};
xbar_asrc_in2_port: port@65 {
reg = <0x65>;
xbar_asrc_in2_ep: endpoint {
remote-endpoint = <&asrc_in2_ep>;
};
};
port@66 {
reg = <0x66>;
xbar_asrc_out2_ep: endpoint {
remote-endpoint = <&asrc_out2_ep>;
};
};
xbar_asrc_in3_port: port@67 {
reg = <0x67>;
xbar_asrc_in3_ep: endpoint {
remote-endpoint = <&asrc_in3_ep>;
};
};
port@68 {
reg = <0x68>;
xbar_asrc_out3_ep: endpoint {
remote-endpoint = <&asrc_out3_ep>;
};
};
xbar_asrc_in4_port: port@69 {
reg = <0x69>;
xbar_asrc_in4_ep: endpoint {
remote-endpoint = <&asrc_in4_ep>;
};
};
port@6a {
reg = <0x6a>;
xbar_asrc_out4_ep: endpoint {
remote-endpoint = <&asrc_out4_ep>;
};
};
xbar_asrc_in5_port: port@6b {
reg = <0x6b>;
xbar_asrc_in5_ep: endpoint {
remote-endpoint = <&asrc_in5_ep>;
};
};
port@6c {
reg = <0x6c>;
xbar_asrc_out5_ep: endpoint {
remote-endpoint = <&asrc_out5_ep>;
};
};
xbar_asrc_in6_port: port@6d {
reg = <0x6d>;
xbar_asrc_in6_ep: endpoint {
remote-endpoint = <&asrc_in6_ep>;
};
};
port@6e {
reg = <0x6e>;
xbar_asrc_out6_ep: endpoint {
remote-endpoint = <&asrc_out6_ep>;
};
};
xbar_asrc_in7_port: port@6f {
reg = <0x6f>;
xbar_asrc_in7_ep: endpoint {
remote-endpoint = <&asrc_in7_ep>;
};
};
};
i2s@2901000 {
@ -1733,6 +1837,119 @@
};
};
};
asrc@2910000 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0x0>;
asrc_in1_ep: endpoint {
remote-endpoint = <&xbar_asrc_in1_ep>;
};
};
port@1 {
reg = <0x1>;
asrc_in2_ep: endpoint {
remote-endpoint = <&xbar_asrc_in2_ep>;
};
};
port@2 {
reg = <0x2>;
asrc_in3_ep: endpoint {
remote-endpoint = <&xbar_asrc_in3_ep>;
};
};
port@3 {
reg = <0x3>;
asrc_in4_ep: endpoint {
remote-endpoint = <&xbar_asrc_in4_ep>;
};
};
port@4 {
reg = <0x4>;
asrc_in5_ep: endpoint {
remote-endpoint = <&xbar_asrc_in5_ep>;
};
};
port@5 {
reg = <0x5>;
asrc_in6_ep: endpoint {
remote-endpoint = <&xbar_asrc_in6_ep>;
};
};
port@6 {
reg = <0x6>;
asrc_in7_ep: endpoint {
remote-endpoint = <&xbar_asrc_in7_ep>;
};
};
asrc_out1_port: port@7 {
reg = <0x7>;
asrc_out1_ep: endpoint {
remote-endpoint = <&xbar_asrc_out1_ep>;
};
};
asrc_out2_port: port@8 {
reg = <0x8>;
asrc_out2_ep: endpoint {
remote-endpoint = <&xbar_asrc_out2_ep>;
};
};
asrc_out3_port: port@9 {
reg = <0x9>;
asrc_out3_ep: endpoint {
remote-endpoint = <&xbar_asrc_out3_ep>;
};
};
asrc_out4_port: port@a {
reg = <0xa>;
asrc_out4_ep: endpoint {
remote-endpoint = <&xbar_asrc_out4_ep>;
};
};
asrc_out5_port: port@b {
reg = <0xb>;
asrc_out5_ep: endpoint {
remote-endpoint = <&xbar_asrc_out5_ep>;
};
};
asrc_out6_port: port@c {
reg = <0xc>;
asrc_out6_ep: endpoint {
remote-endpoint = <&xbar_asrc_out6_ep>;
};
};
};
};
};
dma-controller@2930000 {
@ -1823,6 +2040,10 @@
<&xbar_mix_in5_port>, <&xbar_mix_in6_port>,
<&xbar_mix_in7_port>, <&xbar_mix_in8_port>,
<&xbar_mix_in9_port>, <&xbar_mix_in10_port>,
<&xbar_asrc_in1_port>, <&xbar_asrc_in2_port>,
<&xbar_asrc_in3_port>, <&xbar_asrc_in4_port>,
<&xbar_asrc_in5_port>, <&xbar_asrc_in6_port>,
<&xbar_asrc_in7_port>,
/* HW accelerators */
<&sfc1_out_port>, <&sfc2_out_port>,
<&sfc3_out_port>, <&sfc4_out_port>,
@ -1839,6 +2060,8 @@
<&adx4_out3_port>, <&adx4_out4_port>,
<&mix_out1_port>, <&mix_out2_port>, <&mix_out3_port>,
<&mix_out4_port>, <&mix_out5_port>,
<&asrc_out1_port>, <&asrc_out2_port>, <&asrc_out3_port>,
<&asrc_out4_port>, <&asrc_out5_port>, <&asrc_out6_port>,
/* BE I/O Ports */
<&i2s1_port>, <&i2s2_port>, <&i2s4_port>, <&i2s6_port>,
<&dmic3_port>;

67
arch/arm64/boot/dts/nvidia/tegra234.dtsi
View File

@ -378,6 +378,14 @@
iommus = <&smmu_niso0 TEGRA234_SID_APE>;
status = "disabled";
};
tegra_asrc: asrc@2910000 {
compatible = "nvidia,tegra234-asrc",
"nvidia,tegra186-asrc";
reg = <0x2910000 0x2000>;
sound-name-prefix = "ASRC1";
status = "disabled";
};
};
adma: dma-controller@2930000 {
@ -507,9 +515,27 @@
mc: memory-controller@2c00000 {
compatible = "nvidia,tegra234-mc";
reg = <0x02c00000 0x100000>,
<0x02b80000 0x040000>,
<0x01700000 0x100000>;
reg = <0x02c00000 0x10000>, /* MC-SID */
<0x02c10000 0x10000>, /* MC Broadcast*/
<0x02c20000 0x10000>, /* MC0 */
<0x02c30000 0x10000>, /* MC1 */
<0x02c40000 0x10000>, /* MC2 */
<0x02c50000 0x10000>, /* MC3 */
<0x02b80000 0x10000>, /* MC4 */
<0x02b90000 0x10000>, /* MC5 */
<0x02ba0000 0x10000>, /* MC6 */
<0x02bb0000 0x10000>, /* MC7 */
<0x01700000 0x10000>, /* MC8 */
<0x01710000 0x10000>, /* MC9 */
<0x01720000 0x10000>, /* MC10 */
<0x01730000 0x10000>, /* MC11 */
<0x01740000 0x10000>, /* MC12 */
<0x01750000 0x10000>, /* MC13 */
<0x01760000 0x10000>, /* MC14 */
<0x01770000 0x10000>; /* MC15 */
reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10",
"ch11", "ch12", "ch13", "ch14", "ch15";
interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
#interconnect-cells = <1>;
status = "okay";
@ -654,6 +680,20 @@
reset-names = "i2c";
};
spi@3270000 {
compatible = "nvidia,tegra234-qspi";
reg = <0x3270000 0x1000>;
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&bpmp TEGRA234_CLK_QSPI0_2X_PM>,
<&bpmp TEGRA234_CLK_QSPI0_PM>;
clock-names = "qspi", "qspi_out";
resets = <&bpmp TEGRA234_RESET_QSPI0>;
reset-names = "qspi";
status = "disabled";
};
pwm1: pwm@3280000 {
compatible = "nvidia,tegra194-pwm",
"nvidia,tegra186-pwm";
@ -666,6 +706,20 @@
#pwm-cells = <2>;
};
spi@3300000 {
compatible = "nvidia,tegra234-qspi";
reg = <0x3300000 0x1000>;
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&bpmp TEGRA234_CLK_QSPI1_2X_PM>,
<&bpmp TEGRA234_CLK_QSPI1_PM>;
clock-names = "qspi", "qspi_out";
resets = <&bpmp TEGRA234_RESET_QSPI1>;
reset-names = "qspi";
status = "disabled";
};
mmc@3460000 {
compatible = "nvidia,tegra234-sdhci", "nvidia,tegra186-sdhci";
reg = <0x03460000 0x20000>;
@ -1258,6 +1312,13 @@
};
};
ccplex@e000000 {
compatible = "nvidia,tegra234-ccplex-cluster";
reg = <0x0 0x0e000000 0x0 0x5ffff>;
nvidia,bpmp = <&bpmp>;
status = "okay";
};
sram@40000000 {
compatible = "nvidia,tegra234-sysram", "mmio-sram";
reg = <0x0 0x40000000 0x0 0x80000>;

8
include/dt-bindings/clock/tegra234-clock.h
View File

@ -140,6 +140,14 @@
#define TEGRA234_CLK_PEX2_C9_CORE 173U
/** @brief output of gate CLK_ENB_PEX2_CORE_10 */
#define TEGRA234_CLK_PEX2_C10_CORE 187U
/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_QSPI0 switch divider output */
#define TEGRA234_CLK_QSPI0_2X_PM 192U
/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_QSPI1 switch divider output */
#define TEGRA234_CLK_QSPI1_2X_PM 193U
/** @brief output of the divider QSPI_CLK_DIV2_SEL in CLK_RST_CONTROLLER_CLK_SOURCE_QSPI0 */
#define TEGRA234_CLK_QSPI0_PM 194U
/** @brief output of the divider QSPI_CLK_DIV2_SEL in CLK_RST_CONTROLLER_CLK_SOURCE_QSPI1 */
#define TEGRA234_CLK_QSPI1_PM 195U
/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM switch divider output */
#define TEGRA234_CLK_SDMMC_LEGACY_TM 219U
/** @brief output of gate CLK_ENB_PEX0_CORE_0 */

2
include/dt-bindings/reset/tegra234-reset.h
View File

@ -40,6 +40,8 @@
#define TEGRA234_RESET_PWM6 73U
#define TEGRA234_RESET_PWM7 74U
#define TEGRA234_RESET_PWM8 75U
#define TEGRA234_RESET_QSPI0 76U
#define TEGRA234_RESET_QSPI1 77U
#define TEGRA234_RESET_SDMMC4 85U
#define TEGRA234_RESET_UARTA 100U
#define TEGRA234_RESET_PEX0_CORE_0 116U