net: dsa: mv88e6xxx: Use chip-wide max frame size for MTU
Some of the chips in the mv88e6xxx family don't support jumbo configuration per port. But they do have a chip-wide max frame size that can be used. Use this to approximate the behaviour of configuring a port based MTU. Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -2699,6 +2699,8 @@ static int mv88e6xxx_get_max_mtu(struct dsa_switch *ds, int port)
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if (chip->info->ops->port_set_jumbo_size)
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return 10240;
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else if (chip->info->ops->set_max_frame_size)
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return 1632;
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return 1522;
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}
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@ -2710,6 +2712,8 @@ static int mv88e6xxx_change_mtu(struct dsa_switch *ds, int port, int new_mtu)
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mv88e6xxx_reg_lock(chip);
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if (chip->info->ops->port_set_jumbo_size)
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ret = chip->info->ops->port_set_jumbo_size(chip, port, new_mtu);
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else if (chip->info->ops->set_max_frame_size)
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ret = chip->info->ops->set_max_frame_size(chip, new_mtu);
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else
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if (new_mtu > 1522)
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ret = -EINVAL;
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@ -3450,6 +3454,7 @@ static const struct mv88e6xxx_ops mv88e6085_ops = {
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.vtu_getnext = mv88e6352_g1_vtu_getnext,
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.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
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.phylink_validate = mv88e6185_phylink_validate,
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.set_max_frame_size = mv88e6185_g1_set_max_frame_size,
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};
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static const struct mv88e6xxx_ops mv88e6095_ops = {
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@ -3478,6 +3483,7 @@ static const struct mv88e6xxx_ops mv88e6095_ops = {
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.vtu_getnext = mv88e6185_g1_vtu_getnext,
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.vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
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.phylink_validate = mv88e6185_phylink_validate,
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.set_max_frame_size = mv88e6185_g1_set_max_frame_size,
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};
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static const struct mv88e6xxx_ops mv88e6097_ops = {
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@ -3515,6 +3521,7 @@ static const struct mv88e6xxx_ops mv88e6097_ops = {
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.vtu_getnext = mv88e6352_g1_vtu_getnext,
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.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
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.phylink_validate = mv88e6185_phylink_validate,
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.set_max_frame_size = mv88e6185_g1_set_max_frame_size,
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};
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static const struct mv88e6xxx_ops mv88e6123_ops = {
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@ -3549,6 +3556,7 @@ static const struct mv88e6xxx_ops mv88e6123_ops = {
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.vtu_getnext = mv88e6352_g1_vtu_getnext,
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.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
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.phylink_validate = mv88e6185_phylink_validate,
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.set_max_frame_size = mv88e6185_g1_set_max_frame_size,
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};
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static const struct mv88e6xxx_ops mv88e6131_ops = {
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@ -3938,6 +3946,7 @@ static const struct mv88e6xxx_ops mv88e6185_ops = {
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.vtu_getnext = mv88e6185_g1_vtu_getnext,
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.vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
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.phylink_validate = mv88e6185_phylink_validate,
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.set_max_frame_size = mv88e6185_g1_set_max_frame_size,
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};
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static const struct mv88e6xxx_ops mv88e6190_ops = {
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@ -552,6 +552,9 @@ struct mv88e6xxx_ops {
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void (*phylink_validate)(struct mv88e6xxx_chip *chip, int port,
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unsigned long *mask,
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struct phylink_link_state *state);
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/* Max Frame Size */
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int (*set_max_frame_size)(struct mv88e6xxx_chip *chip, int mtu);
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};
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struct mv88e6xxx_irq_ops {
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@ -196,6 +196,23 @@ int mv88e6185_g1_ppu_disable(struct mv88e6xxx_chip *chip)
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return mv88e6185_g1_wait_ppu_disabled(chip);
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}
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int mv88e6185_g1_set_max_frame_size(struct mv88e6xxx_chip *chip, int mtu)
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{
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u16 val;
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int err;
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err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val);
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if (err)
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return err;
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val &= ~MV88E6185_G1_CTL1_MAX_FRAME_1632;
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if (mtu > 1518)
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val |= MV88E6185_G1_CTL1_MAX_FRAME_1632;
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return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val);
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}
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/* Offset 0x10: IP-PRI Mapping Register 0
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* Offset 0x11: IP-PRI Mapping Register 1
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* Offset 0x12: IP-PRI Mapping Register 2
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@ -282,6 +282,8 @@ int mv88e6250_g1_reset(struct mv88e6xxx_chip *chip);
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int mv88e6185_g1_ppu_enable(struct mv88e6xxx_chip *chip);
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int mv88e6185_g1_ppu_disable(struct mv88e6xxx_chip *chip);
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int mv88e6185_g1_set_max_frame_size(struct mv88e6xxx_chip *chip, int mtu);
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int mv88e6xxx_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port);
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int mv88e6320_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port);
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int mv88e6390_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port);
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