drm/i915: Pass clock limits down to PLL matcher
As we already know the limits for the hardware clock, pass it down rather than recomputing them for each match. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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@ -642,26 +642,23 @@ static const intel_limit_t intel_limits_ironlake_display_port = {
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.find_pll = intel_find_pll_ironlake_dp,
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.find_pll = intel_find_pll_ironlake_dp,
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};
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};
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static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc)
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static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
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int refclk)
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{
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{
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struct drm_device *dev = crtc->dev;
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struct drm_device *dev = crtc->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct drm_i915_private *dev_priv = dev->dev_private;
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const intel_limit_t *limit;
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const intel_limit_t *limit;
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int refclk = 120;
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if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
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if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
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if (dev_priv->lvds_use_ssc && dev_priv->lvds_ssc_freq == 100)
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refclk = 100;
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if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
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if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
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LVDS_CLKB_POWER_UP) {
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LVDS_CLKB_POWER_UP) {
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/* LVDS dual channel */
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/* LVDS dual channel */
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if (refclk == 100)
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if (refclk == 100000)
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limit = &intel_limits_ironlake_dual_lvds_100m;
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limit = &intel_limits_ironlake_dual_lvds_100m;
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else
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else
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limit = &intel_limits_ironlake_dual_lvds;
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limit = &intel_limits_ironlake_dual_lvds;
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} else {
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} else {
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if (refclk == 100)
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if (refclk == 100000)
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limit = &intel_limits_ironlake_single_lvds_100m;
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limit = &intel_limits_ironlake_single_lvds_100m;
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else
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else
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limit = &intel_limits_ironlake_single_lvds;
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limit = &intel_limits_ironlake_single_lvds;
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@ -702,13 +699,13 @@ static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
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return limit;
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return limit;
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}
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}
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static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
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static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
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{
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{
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struct drm_device *dev = crtc->dev;
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struct drm_device *dev = crtc->dev;
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const intel_limit_t *limit;
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const intel_limit_t *limit;
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if (HAS_PCH_SPLIT(dev))
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if (HAS_PCH_SPLIT(dev))
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limit = intel_ironlake_limit(crtc);
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limit = intel_ironlake_limit(crtc, refclk);
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else if (IS_G4X(dev)) {
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else if (IS_G4X(dev)) {
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limit = intel_g4x_limit(crtc);
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limit = intel_g4x_limit(crtc);
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} else if (IS_PINEVIEW(dev)) {
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} else if (IS_PINEVIEW(dev)) {
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@ -773,11 +770,10 @@ bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
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* the given connectors.
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* the given connectors.
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*/
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*/
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static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock)
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static bool intel_PLL_is_valid(struct drm_device *dev,
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const intel_limit_t *limit,
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const intel_clock_t *clock)
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{
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{
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const intel_limit_t *limit = intel_limit (crtc);
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struct drm_device *dev = crtc->dev;
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if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
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if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
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INTELPllInvalid ("p1 out of range\n");
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INTELPllInvalid ("p1 out of range\n");
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if (clock->p < limit->p.min || limit->p.max < clock->p)
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if (clock->p < limit->p.min || limit->p.max < clock->p)
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@ -849,8 +845,8 @@ intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
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int this_err;
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int this_err;
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intel_clock(dev, refclk, &clock);
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intel_clock(dev, refclk, &clock);
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if (!intel_PLL_is_valid(dev, limit,
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if (!intel_PLL_is_valid(crtc, &clock))
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&clock))
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continue;
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continue;
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this_err = abs(clock.dot - target);
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this_err = abs(clock.dot - target);
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@ -912,9 +908,11 @@ intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
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int this_err;
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int this_err;
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intel_clock(dev, refclk, &clock);
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intel_clock(dev, refclk, &clock);
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if (!intel_PLL_is_valid(crtc, &clock))
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if (!intel_PLL_is_valid(dev, limit,
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&clock))
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continue;
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continue;
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this_err = abs(clock.dot - target) ;
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this_err = abs(clock.dot - target);
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if (this_err < err_most) {
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if (this_err < err_most) {
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*best_clock = clock;
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*best_clock = clock;
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err_most = this_err;
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err_most = this_err;
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@ -3655,7 +3653,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
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* refclk, or FALSE. The returned values represent the clock equation:
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* refclk, or FALSE. The returned values represent the clock equation:
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* reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
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* reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
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*/
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*/
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limit = intel_limit(crtc);
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limit = intel_limit(crtc, refclk);
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ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
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ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
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if (!ok) {
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if (!ok) {
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DRM_ERROR("Couldn't find PLL settings for mode!\n");
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DRM_ERROR("Couldn't find PLL settings for mode!\n");
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