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EDAC, synopsys: Improve code readability 

Clean up the driver code. Update the debug messages for EDAC errors
reported. Increase the indentation of the macros for better readability.

Signed-off-by: Manish Narani <manish.narani@xilinx.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
CC: Mauro Carvalho Chehab <mchehab@kernel.org>
CC: Michal Simek <michal.simek@xilinx.com>
CC: amit.kucheria@linaro.org
CC: devicetree@vger.kernel.org
CC: leoyang.li@nxp.com
CC: linux-arm-kernel@lists.infradead.org
CC: linux-edac <linux-edac@vger.kernel.org>
CC: manish.narani@xilinx.com
CC: mark.rutland@arm.com
CC: mchehab@kernel.org
CC: michal.simek@xilinx.com
CC: robh+dt@kernel.org
CC: sudeep.holla@arm.com
Link: http://lkml.kernel.org/r/1538667328-9465-2-git-send-email-manish.narani@xilinx.com
This commit is contained in:
Manish Narani 2018-10-04 21:05:19 +05:30 committed by Borislav Petkov
parent 651022382c
commit 1b51adc6b7
1 changed files with 52 additions and 52 deletions
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104
drivers/edac/synopsys_edac.c
View File

@ -26,74 +26,74 @@
#include "edac_module.h" #include "edac_module.h"
/* Number of cs_rows needed per memory controller */ /* Number of cs_rows needed per memory controller */
#define SYNPS_EDAC_NR_CSROWS 1 #define SYNPS_EDAC_NR_CSROWS 1
/* Number of channels per memory controller */ /* Number of channels per memory controller */
#define SYNPS_EDAC_NR_CHANS 1 #define SYNPS_EDAC_NR_CHANS 1
/* Granularity of reported error in bytes */ /* Granularity of reported error in bytes */
#define SYNPS_EDAC_ERR_GRAIN 1 #define SYNPS_EDAC_ERR_GRAIN 1
#define SYNPS_EDAC_MSG_SIZE 256 #define SYNPS_EDAC_MSG_SIZE 256
#define SYNPS_EDAC_MOD_STRING "synps_edac" #define SYNPS_EDAC_MOD_STRING "synps_edac"
#define SYNPS_EDAC_MOD_VER "1" #define SYNPS_EDAC_MOD_VER "1"
/* Synopsys DDR memory controller registers that are relevant to ECC */ /* Synopsys DDR memory controller registers that are relevant to ECC */
#define CTRL_OFST 0x0 #define CTRL_OFST 0x0
#define T_ZQ_OFST 0xA4 #define T_ZQ_OFST 0xA4
/* ECC control register */ /* ECC control register */
#define ECC_CTRL_OFST 0xC4 #define ECC_CTRL_OFST 0xC4
/* ECC log register */ /* ECC log register */
#define CE_LOG_OFST 0xC8 #define CE_LOG_OFST 0xC8
/* ECC address register */ /* ECC address register */
#define CE_ADDR_OFST 0xCC #define CE_ADDR_OFST 0xCC
/* ECC data[31:0] register */ /* ECC data[31:0] register */
#define CE_DATA_31_0_OFST 0xD0 #define CE_DATA_31_0_OFST 0xD0
/* Uncorrectable error info registers */ /* Uncorrectable error info registers */
#define UE_LOG_OFST 0xDC #define UE_LOG_OFST 0xDC
#define UE_ADDR_OFST 0xE0 #define UE_ADDR_OFST 0xE0
#define UE_DATA_31_0_OFST 0xE4 #define UE_DATA_31_0_OFST 0xE4
#define STAT_OFST 0xF0 #define STAT_OFST 0xF0
#define SCRUB_OFST 0xF4 #define SCRUB_OFST 0xF4
/* Control register bit field definitions */ /* Control register bit field definitions */
#define CTRL_BW_MASK 0xC #define CTRL_BW_MASK 0xC
#define CTRL_BW_SHIFT 2 #define CTRL_BW_SHIFT 2
#define DDRCTL_WDTH_16 1 #define DDRCTL_WDTH_16 1
#define DDRCTL_WDTH_32 0 #define DDRCTL_WDTH_32 0
/* ZQ register bit field definitions */ /* ZQ register bit field definitions */
#define T_ZQ_DDRMODE_MASK 0x2 #define T_ZQ_DDRMODE_MASK 0x2
/* ECC control register bit field definitions */ /* ECC control register bit field definitions */
#define ECC_CTRL_CLR_CE_ERR 0x2 #define ECC_CTRL_CLR_CE_ERR 0x2
#define ECC_CTRL_CLR_UE_ERR 0x1 #define ECC_CTRL_CLR_UE_ERR 0x1
/* ECC correctable/uncorrectable error log register definitions */ /* ECC correctable/uncorrectable error log register definitions */
#define LOG_VALID 0x1 #define LOG_VALID 0x1
#define CE_LOG_BITPOS_MASK 0xFE #define CE_LOG_BITPOS_MASK 0xFE
#define CE_LOG_BITPOS_SHIFT 1 #define CE_LOG_BITPOS_SHIFT 1
/* ECC correctable/uncorrectable error address register definitions */ /* ECC correctable/uncorrectable error address register definitions */
#define ADDR_COL_MASK 0xFFF #define ADDR_COL_MASK 0xFFF
#define ADDR_ROW_MASK 0xFFFF000 #define ADDR_ROW_MASK 0xFFFF000
#define ADDR_ROW_SHIFT 12 #define ADDR_ROW_SHIFT 12
#define ADDR_BANK_MASK 0x70000000 #define ADDR_BANK_MASK 0x70000000
#define ADDR_BANK_SHIFT 28 #define ADDR_BANK_SHIFT 28
/* ECC statistic register definitions */ /* ECC statistic register definitions */
#define STAT_UECNT_MASK 0xFF #define STAT_UECNT_MASK 0xFF
#define STAT_CECNT_MASK 0xFF00 #define STAT_CECNT_MASK 0xFF00
#define STAT_CECNT_SHIFT 8 #define STAT_CECNT_SHIFT 8
/* ECC scrub register definitions */ /* ECC scrub register definitions */
#define SCRUB_MODE_MASK 0x7 #define SCRUB_MODE_MASK 0x7
#define SCRUB_MODE_SECDED 0x4 #define SCRUB_MODE_SECDED 0x4
/** /**
* struct ecc_error_info - ECC error log information * struct ecc_error_info - ECC error log information
@ -172,7 +172,7 @@ static int synps_edac_geterror_info(void __iomem *base,
p->ceinfo.col = regval & ADDR_COL_MASK; p->ceinfo.col = regval & ADDR_COL_MASK;
p->ceinfo.bank = (regval & ADDR_BANK_MASK) >> ADDR_BANK_SHIFT; p->ceinfo.bank = (regval & ADDR_BANK_MASK) >> ADDR_BANK_SHIFT;
p->ceinfo.data = readl(base + CE_DATA_31_0_OFST); p->ceinfo.data = readl(base + CE_DATA_31_0_OFST);
edac_dbg(3, "ce bit position: %d data: %d\n", p->ceinfo.bitpos, edac_dbg(3, "CE bit position: %d data: %d\n", p->ceinfo.bitpos,
p->ceinfo.data); p->ceinfo.data);
clearval = ECC_CTRL_CLR_CE_ERR; clearval = ECC_CTRL_CLR_CE_ERR;
@ -250,7 +250,7 @@ static void synps_edac_check(struct mem_ctl_info *mci)
priv->ue_cnt += priv->stat.ue_cnt; priv->ue_cnt += priv->stat.ue_cnt;
synps_edac_handle_error(mci, &priv->stat); synps_edac_handle_error(mci, &priv->stat);
edac_dbg(3, "Total error count ce %d ue %d\n", edac_dbg(3, "Total error count CE %d UE %d\n",
priv->ce_cnt, priv->ue_cnt); priv->ce_cnt, priv->ue_cnt);
} }
@ -295,9 +295,9 @@ static enum dev_type synps_edac_get_dtype(const void __iomem *base)
*/ */
static bool synps_edac_get_eccstate(void __iomem *base) static bool synps_edac_get_eccstate(void __iomem *base)
{ {
bool state = false;
enum dev_type dt; enum dev_type dt;
u32 ecctype; u32 ecctype;
bool state = false;
dt = synps_edac_get_dtype(base); dt = synps_edac_get_dtype(base);
if (dt == DEV_UNKNOWN) if (dt == DEV_UNKNOWN)
@ -359,23 +359,23 @@ static enum mem_type synps_edac_get_mtype(const void __iomem *base)
*/ */
static int synps_edac_init_csrows(struct mem_ctl_info *mci) static int synps_edac_init_csrows(struct mem_ctl_info *mci)
{ {
struct synps_edac_priv *priv = mci->pvt_info;
struct csrow_info *csi; struct csrow_info *csi;
struct dimm_info *dimm; struct dimm_info *dimm;
struct synps_edac_priv *priv = mci->pvt_info; u32 size, row;
u32 size; int j;
int row, j;
for (row = 0; row < mci->nr_csrows; row++) { for (row = 0; row < mci->nr_csrows; row++) {
csi = mci->csrows[row]; csi = mci->csrows[row];
size = synps_edac_get_memsize(); size = synps_edac_get_memsize();
for (j = 0; j < csi->nr_channels; j++) { for (j = 0; j < csi->nr_channels; j++) {
dimm = csi->channels[j]->dimm; dimm = csi->channels[j]->dimm;
dimm->edac_mode = EDAC_FLAG_SECDED; dimm->edac_mode = EDAC_FLAG_SECDED;
dimm->mtype = synps_edac_get_mtype(priv->baseaddr); dimm->mtype = synps_edac_get_mtype(priv->baseaddr);
dimm->nr_pages = (size >> PAGE_SHIFT) / csi->nr_channels; dimm->nr_pages = (size >> PAGE_SHIFT) / csi->nr_channels;
dimm->grain = SYNPS_EDAC_ERR_GRAIN; dimm->grain = SYNPS_EDAC_ERR_GRAIN;
dimm->dtype = synps_edac_get_dtype(priv->baseaddr); dimm->dtype = synps_edac_get_dtype(priv->baseaddr);
} }
} }
@ -434,12 +434,12 @@ static int synps_edac_mc_init(struct mem_ctl_info *mci,
*/ */
static int synps_edac_mc_probe(struct platform_device *pdev) static int synps_edac_mc_probe(struct platform_device *pdev)
{ {
struct mem_ctl_info *mci;
struct edac_mc_layer layers[2]; struct edac_mc_layer layers[2];
struct synps_edac_priv *priv; struct synps_edac_priv *priv;
int rc; struct mem_ctl_info *mci;
struct resource *res;
void __iomem *baseaddr; void __iomem *baseaddr;
struct resource *res;
int rc;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0); res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
baseaddr = devm_ioremap_resource(&pdev->dev, res); baseaddr = devm_ioremap_resource(&pdev->dev, res);