irqchip core changes for v3.17 (round #3)
- gic
- Add GICv3 driver
- atmel
- Move atmel aic driver from arch code to irqchip/
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Merge tag 'irqchip-core-3.17-3' of git://git.infradead.org/users/jcooper/linux into irq/core
irqchip core changes for v3.17 (round #3) from Jason Cooper
* gic: Add GICv3 driver
* atmel: Move atmel aic driver from arch code to irqchip/
This commit is contained in:
Thomas Gleixner
commit
1b0733837a
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@ -10,6 +10,7 @@ config ARM64
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select ARM_AMBA
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select ARM_ARCH_TIMER
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select ARM_GIC
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select ARM_GIC_V3
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select BUILDTIME_EXTABLE_SORT
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select CLONE_BACKWARDS
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select COMMON_CLK
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|
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@ -22,6 +22,7 @@
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#include <linux/linkage.h>
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#include <linux/init.h>
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#include <linux/irqchip/arm-gic-v3.h>
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#include <asm/assembler.h>
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#include <asm/ptrace.h>
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@ -296,6 +297,23 @@ CPU_LE( bic x0, x0, #(3 << 24) ) // Clear the EE and E0E bits for EL1
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msr cnthctl_el2, x0
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msr cntvoff_el2, xzr // Clear virtual offset
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#ifdef CONFIG_ARM_GIC_V3
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/* GICv3 system register access */
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mrs x0, id_aa64pfr0_el1
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ubfx x0, x0, #24, #4
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cmp x0, #1
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b.ne 3f
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mrs x0, ICC_SRE_EL2
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orr x0, x0, #ICC_SRE_EL2_SRE // Set ICC_SRE_EL2.SRE==1
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orr x0, x0, #ICC_SRE_EL2_ENABLE // Set ICC_SRE_EL2.Enable==1
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msr ICC_SRE_EL2, x0
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isb // Make sure SRE is now set
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msr ICH_HCR_EL2, xzr // Reset ICC_HCR_EL2 to defaults
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3:
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#endif
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/* Populate ID registers. */
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mrs x0, midr_el1
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mrs x1, mpidr_el1
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@ -19,6 +19,7 @@
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#include <linux/init.h>
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#include <linux/linkage.h>
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#include <linux/irqchip/arm-gic-v3.h>
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#include <asm/assembler.h>
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#include <asm/ptrace.h>
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@ -10,6 +10,11 @@ config ARM_GIC
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config GIC_NON_BANKED
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bool
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config ARM_GIC_V3
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bool
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select IRQ_DOMAIN
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select MULTI_IRQ_HANDLER
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config ARM_NVIC
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bool
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select IRQ_DOMAIN
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@ -30,6 +35,20 @@ config ARM_VIC_NR
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The maximum number of VICs available in the system, for
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power management.
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config ATMEL_AIC_IRQ
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bool
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select GENERIC_IRQ_CHIP
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select IRQ_DOMAIN
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select MULTI_IRQ_HANDLER
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select SPARSE_IRQ
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config ATMEL_AIC5_IRQ
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bool
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select GENERIC_IRQ_CHIP
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select IRQ_DOMAIN
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select MULTI_IRQ_HANDLER
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select SPARSE_IRQ
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config BRCMSTB_L2_IRQ
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bool
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depends on ARM
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|
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@ -16,9 +16,12 @@ obj-$(CONFIG_ORION_IRQCHIP) += irq-orion.o
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obj-$(CONFIG_ARCH_SUNXI) += irq-sun4i.o
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obj-$(CONFIG_ARCH_SUNXI) += irq-sunxi-nmi.o
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obj-$(CONFIG_ARCH_SPEAR3XX) += spear-shirq.o
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obj-$(CONFIG_ARM_GIC) += irq-gic.o
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obj-$(CONFIG_ARM_GIC) += irq-gic.o irq-gic-common.o
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obj-$(CONFIG_ARM_GIC_V3) += irq-gic-v3.o irq-gic-common.o
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obj-$(CONFIG_ARM_NVIC) += irq-nvic.o
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obj-$(CONFIG_ARM_VIC) += irq-vic.o
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obj-$(CONFIG_ATMEL_AIC_IRQ) += irq-atmel-aic-common.o irq-atmel-aic.o
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obj-$(CONFIG_ATMEL_AIC5_IRQ) += irq-atmel-aic-common.o irq-atmel-aic5.o
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obj-$(CONFIG_IMGPDC_IRQ) += irq-imgpdc.o
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obj-$(CONFIG_SIRF_IRQ) += irq-sirfsoc.o
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obj-$(CONFIG_RENESAS_INTC_IRQPIN) += irq-renesas-intc-irqpin.o
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|
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@ -0,0 +1,254 @@
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/*
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* Atmel AT91 common AIC (Advanced Interrupt Controller) code shared by
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* irq-atmel-aic and irq-atmel-aic5 drivers
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*
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* Copyright (C) 2004 SAN People
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* Copyright (C) 2004 ATMEL
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* Copyright (C) Rick Bronson
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* Copyright (C) 2014 Free Electrons
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*
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* Author: Boris BREZILLON <boris.brezillon@free-electrons.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/errno.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/irqdomain.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/slab.h>
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#include "irq-atmel-aic-common.h"
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#define AT91_AIC_PRIOR GENMASK(2, 0)
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#define AT91_AIC_IRQ_MIN_PRIORITY 0
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#define AT91_AIC_IRQ_MAX_PRIORITY 7
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#define AT91_AIC_SRCTYPE GENMASK(7, 6)
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#define AT91_AIC_SRCTYPE_LOW (0 << 5)
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#define AT91_AIC_SRCTYPE_FALLING (1 << 5)
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#define AT91_AIC_SRCTYPE_HIGH (2 << 5)
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#define AT91_AIC_SRCTYPE_RISING (3 << 5)
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struct aic_chip_data {
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u32 ext_irqs;
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};
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static void aic_common_shutdown(struct irq_data *d)
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{
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struct irq_chip_type *ct = irq_data_get_chip_type(d);
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ct->chip.irq_mask(d);
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}
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int aic_common_set_type(struct irq_data *d, unsigned type, unsigned *val)
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{
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
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struct aic_chip_data *aic = gc->private;
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unsigned aic_type;
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switch (type) {
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case IRQ_TYPE_LEVEL_HIGH:
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aic_type = AT91_AIC_SRCTYPE_HIGH;
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break;
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case IRQ_TYPE_EDGE_RISING:
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aic_type = AT91_AIC_SRCTYPE_RISING;
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break;
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case IRQ_TYPE_LEVEL_LOW:
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if (!(d->mask & aic->ext_irqs))
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return -EINVAL;
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aic_type = AT91_AIC_SRCTYPE_LOW;
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break;
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case IRQ_TYPE_EDGE_FALLING:
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if (!(d->mask & aic->ext_irqs))
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return -EINVAL;
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aic_type = AT91_AIC_SRCTYPE_FALLING;
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break;
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default:
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return -EINVAL;
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}
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*val &= AT91_AIC_SRCTYPE;
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*val |= aic_type;
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return 0;
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}
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int aic_common_set_priority(int priority, unsigned *val)
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{
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if (priority < AT91_AIC_IRQ_MIN_PRIORITY ||
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priority > AT91_AIC_IRQ_MAX_PRIORITY)
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return -EINVAL;
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*val &= AT91_AIC_PRIOR;
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*val |= priority;
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return 0;
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}
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int aic_common_irq_domain_xlate(struct irq_domain *d,
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struct device_node *ctrlr,
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const u32 *intspec,
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unsigned int intsize,
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irq_hw_number_t *out_hwirq,
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unsigned int *out_type)
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{
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if (WARN_ON(intsize < 3))
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return -EINVAL;
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if (WARN_ON((intspec[2] < AT91_AIC_IRQ_MIN_PRIORITY) ||
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(intspec[2] > AT91_AIC_IRQ_MAX_PRIORITY)))
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return -EINVAL;
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*out_hwirq = intspec[0];
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*out_type = intspec[1] & IRQ_TYPE_SENSE_MASK;
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return 0;
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}
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static void __init aic_common_ext_irq_of_init(struct irq_domain *domain)
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{
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struct device_node *node = domain->of_node;
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struct irq_chip_generic *gc;
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struct aic_chip_data *aic;
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struct property *prop;
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const __be32 *p;
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u32 hwirq;
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gc = irq_get_domain_generic_chip(domain, 0);
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aic = gc->private;
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aic->ext_irqs |= 1;
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of_property_for_each_u32(node, "atmel,external-irqs", prop, p, hwirq) {
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gc = irq_get_domain_generic_chip(domain, hwirq);
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if (!gc) {
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pr_warn("AIC: external irq %d >= %d skip it\n",
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hwirq, domain->revmap_size);
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continue;
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}
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aic = gc->private;
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aic->ext_irqs |= (1 << (hwirq % 32));
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}
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}
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#define AT91_RTC_IDR 0x24
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#define AT91_RTC_IMR 0x28
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#define AT91_RTC_IRQ_MASK 0x1f
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void __init aic_common_rtc_irq_fixup(struct device_node *root)
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{
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struct device_node *np;
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void __iomem *regs;
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np = of_find_compatible_node(root, NULL, "atmel,at91rm9200-rtc");
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if (!np)
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np = of_find_compatible_node(root, NULL,
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"atmel,at91sam9x5-rtc");
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if (!np)
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return;
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regs = of_iomap(np, 0);
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of_node_put(np);
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if (!regs)
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return;
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writel(AT91_RTC_IRQ_MASK, regs + AT91_RTC_IDR);
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iounmap(regs);
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}
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void __init aic_common_irq_fixup(const struct of_device_id *matches)
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{
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struct device_node *root = of_find_node_by_path("/");
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const struct of_device_id *match;
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if (!root)
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||||
return;
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match = of_match_node(matches, root);
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of_node_put(root);
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|
||||
if (match) {
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||||
void (*fixup)(struct device_node *) = match->data;
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fixup(root);
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||||
}
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of_node_put(root);
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||||
}
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|
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struct irq_domain *__init aic_common_of_init(struct device_node *node,
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||||
const struct irq_domain_ops *ops,
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||||
const char *name, int nirqs)
|
||||
{
|
||||
struct irq_chip_generic *gc;
|
||||
struct irq_domain *domain;
|
||||
struct aic_chip_data *aic;
|
||||
void __iomem *reg_base;
|
||||
int nchips;
|
||||
int ret;
|
||||
int i;
|
||||
|
||||
nchips = DIV_ROUND_UP(nirqs, 32);
|
||||
|
||||
reg_base = of_iomap(node, 0);
|
||||
if (!reg_base)
|
||||
return ERR_PTR(-ENOMEM);
|
||||
|
||||
aic = kcalloc(nchips, sizeof(*aic), GFP_KERNEL);
|
||||
if (!aic) {
|
||||
ret = -ENOMEM;
|
||||
goto err_iounmap;
|
||||
}
|
||||
|
||||
domain = irq_domain_add_linear(node, nchips * 32, ops, aic);
|
||||
if (!domain) {
|
||||
ret = -ENOMEM;
|
||||
goto err_free_aic;
|
||||
}
|
||||
|
||||
ret = irq_alloc_domain_generic_chips(domain, 32, 1, name,
|
||||
handle_level_irq, 0, 0,
|
||||
IRQCHIP_SKIP_SET_WAKE);
|
||||
if (ret)
|
||||
goto err_domain_remove;
|
||||
|
||||
for (i = 0; i < nchips; i++) {
|
||||
gc = irq_get_domain_generic_chip(domain, i * 32);
|
||||
|
||||
gc->reg_base = reg_base;
|
||||
|
||||
gc->unused = 0;
|
||||
gc->wake_enabled = ~0;
|
||||
gc->chip_types[0].type = IRQ_TYPE_SENSE_MASK;
|
||||
gc->chip_types[0].handler = handle_fasteoi_irq;
|
||||
gc->chip_types[0].chip.irq_eoi = irq_gc_eoi;
|
||||
gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake;
|
||||
gc->chip_types[0].chip.irq_shutdown = aic_common_shutdown;
|
||||
gc->private = &aic[i];
|
||||
}
|
||||
|
||||
aic_common_ext_irq_of_init(domain);
|
||||
|
||||
return domain;
|
||||
|
||||
err_domain_remove:
|
||||
irq_domain_remove(domain);
|
||||
|
||||
err_free_aic:
|
||||
kfree(aic);
|
||||
|
||||
err_iounmap:
|
||||
iounmap(reg_base);
|
||||
|
||||
return ERR_PTR(ret);
|
||||
}
|
||||
|
|
@ -0,0 +1,39 @@
|
|||
/*
|
||||
* Atmel AT91 common AIC (Advanced Interrupt Controller) header file
|
||||
*
|
||||
* Copyright (C) 2004 SAN People
|
||||
* Copyright (C) 2004 ATMEL
|
||||
* Copyright (C) Rick Bronson
|
||||
* Copyright (C) 2014 Free Electrons
|
||||
*
|
||||
* Author: Boris BREZILLON <boris.brezillon@free-electrons.com>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#ifndef __IRQ_ATMEL_AIC_COMMON_H
|
||||
#define __IRQ_ATMEL_AIC_COMMON_H
|
||||
|
||||
|
||||
int aic_common_set_type(struct irq_data *d, unsigned type, unsigned *val);
|
||||
|
||||
int aic_common_set_priority(int priority, unsigned *val);
|
||||
|
||||
int aic_common_irq_domain_xlate(struct irq_domain *d,
|
||||
struct device_node *ctrlr,
|
||||
const u32 *intspec,
|
||||
unsigned int intsize,
|
||||
irq_hw_number_t *out_hwirq,
|
||||
unsigned int *out_type);
|
||||
|
||||
struct irq_domain *__init aic_common_of_init(struct device_node *node,
|
||||
const struct irq_domain_ops *ops,
|
||||
const char *name, int nirqs);
|
||||
|
||||
void __init aic_common_rtc_irq_fixup(struct device_node *root);
|
||||
|
||||
void __init aic_common_irq_fixup(const struct of_device_id *matches);
|
||||
|
||||
#endif /* __IRQ_ATMEL_AIC_COMMON_H */
|
||||
|
|
@ -0,0 +1,262 @@
|
|||
/*
|
||||
* Atmel AT91 AIC (Advanced Interrupt Controller) driver
|
||||
*
|
||||
* Copyright (C) 2004 SAN People
|
||||
* Copyright (C) 2004 ATMEL
|
||||
* Copyright (C) Rick Bronson
|
||||
* Copyright (C) 2014 Free Electrons
|
||||
*
|
||||
* Author: Boris BREZILLON <boris.brezillon@free-electrons.com>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#include <linux/init.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/mm.h>
|
||||
#include <linux/bitmap.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/of_irq.h>
|
||||
#include <linux/irqdomain.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/io.h>
|
||||
|
||||
#include <asm/exception.h>
|
||||
#include <asm/mach/irq.h>
|
||||
|
||||
#include "irq-atmel-aic-common.h"
|
||||
#include "irqchip.h"
|
||||
|
||||
/* Number of irq lines managed by AIC */
|
||||
#define NR_AIC_IRQS 32
|
||||
|
||||
#define AT91_AIC_SMR(n) ((n) * 4)
|
||||
|
||||
#define AT91_AIC_SVR(n) (0x80 + ((n) * 4))
|
||||
#define AT91_AIC_IVR 0x100
|
||||
#define AT91_AIC_FVR 0x104
|
||||
#define AT91_AIC_ISR 0x108
|
||||
|
||||
#define AT91_AIC_IPR 0x10c
|
||||
#define AT91_AIC_IMR 0x110
|
||||
#define AT91_AIC_CISR 0x114
|
||||
|
||||
#define AT91_AIC_IECR 0x120
|
||||
#define AT91_AIC_IDCR 0x124
|
||||
#define AT91_AIC_ICCR 0x128
|
||||
#define AT91_AIC_ISCR 0x12c
|
||||
#define AT91_AIC_EOICR 0x130
|
||||
#define AT91_AIC_SPU 0x134
|
||||
#define AT91_AIC_DCR 0x138
|
||||
|
||||
static struct irq_domain *aic_domain;
|
||||
|
||||
static asmlinkage void __exception_irq_entry
|
||||
aic_handle(struct pt_regs *regs)
|
||||
{
|
||||
struct irq_domain_chip_generic *dgc = aic_domain->gc;
|
||||
struct irq_chip_generic *gc = dgc->gc[0];
|
||||
u32 irqnr;
|
||||
u32 irqstat;
|
||||
|
||||
irqnr = irq_reg_readl(gc->reg_base + AT91_AIC_IVR);
|
||||
irqstat = irq_reg_readl(gc->reg_base + AT91_AIC_ISR);
|
||||
|
||||
irqnr = irq_find_mapping(aic_domain, irqnr);
|
||||
|
||||
if (!irqstat)
|
||||
irq_reg_writel(0, gc->reg_base + AT91_AIC_EOICR);
|
||||
else
|
||||
handle_IRQ(irqnr, regs);
|
||||
}
|
||||
|
||||
static int aic_retrigger(struct irq_data *d)
|
||||
{
|
||||
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
|
||||
|
||||
/* Enable interrupt on AIC5 */
|
||||
irq_gc_lock(gc);
|
||||
irq_reg_writel(d->mask, gc->reg_base + AT91_AIC_ISCR);
|
||||
irq_gc_unlock(gc);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int aic_set_type(struct irq_data *d, unsigned type)
|
||||
{
|
||||
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
|
||||
unsigned int smr;
|
||||
int ret;
|
||||
|
||||
smr = irq_reg_readl(gc->reg_base + AT91_AIC_SMR(d->hwirq));
|
||||
ret = aic_common_set_type(d, type, &smr);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
irq_reg_writel(smr, gc->reg_base + AT91_AIC_SMR(d->hwirq));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
static void aic_suspend(struct irq_data *d)
|
||||
{
|
||||
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
|
||||
|
||||
irq_gc_lock(gc);
|
||||
irq_reg_writel(gc->mask_cache, gc->reg_base + AT91_AIC_IDCR);
|
||||
irq_reg_writel(gc->wake_active, gc->reg_base + AT91_AIC_IECR);
|
||||
irq_gc_unlock(gc);
|
||||
}
|
||||
|
||||
static void aic_resume(struct irq_data *d)
|
||||
{
|
||||
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
|
||||
|
||||
irq_gc_lock(gc);
|
||||
irq_reg_writel(gc->wake_active, gc->reg_base + AT91_AIC_IDCR);
|
||||
irq_reg_writel(gc->mask_cache, gc->reg_base + AT91_AIC_IECR);
|
||||
irq_gc_unlock(gc);
|
||||
}
|
||||
|
||||
static void aic_pm_shutdown(struct irq_data *d)
|
||||
{
|
||||
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
|
||||
|
||||
irq_gc_lock(gc);
|
||||
irq_reg_writel(0xffffffff, gc->reg_base + AT91_AIC_IDCR);
|
||||
irq_reg_writel(0xffffffff, gc->reg_base + AT91_AIC_ICCR);
|
||||
irq_gc_unlock(gc);
|
||||
}
|
||||
#else
|
||||
#define aic_suspend NULL
|
||||
#define aic_resume NULL
|
||||
#define aic_pm_shutdown NULL
|
||||
#endif /* CONFIG_PM */
|
||||
|
||||
static void __init aic_hw_init(struct irq_domain *domain)
|
||||
{
|
||||
struct irq_chip_generic *gc = irq_get_domain_generic_chip(domain, 0);
|
||||
int i;
|
||||
|
||||
/*
|
||||
* Perform 8 End Of Interrupt Command to make sure AIC
|
||||
* will not Lock out nIRQ
|
||||
*/
|
||||
for (i = 0; i < 8; i++)
|
||||
irq_reg_writel(0, gc->reg_base + AT91_AIC_EOICR);
|
||||
|
||||
/*
|
||||
* Spurious Interrupt ID in Spurious Vector Register.
|
||||
* When there is no current interrupt, the IRQ Vector Register
|
||||
* reads the value stored in AIC_SPU
|
||||
*/
|
||||
irq_reg_writel(0xffffffff, gc->reg_base + AT91_AIC_SPU);
|
||||
|
||||
/* No debugging in AIC: Debug (Protect) Control Register */
|
||||
irq_reg_writel(0, gc->reg_base + AT91_AIC_DCR);
|
||||
|
||||
/* Disable and clear all interrupts initially */
|
||||
irq_reg_writel(0xffffffff, gc->reg_base + AT91_AIC_IDCR);
|
||||
irq_reg_writel(0xffffffff, gc->reg_base + AT91_AIC_ICCR);
|
||||
|
||||
for (i = 0; i < 32; i++)
|
||||
irq_reg_writel(i, gc->reg_base + AT91_AIC_SVR(i));
|
||||
}
|
||||
|
||||
static int aic_irq_domain_xlate(struct irq_domain *d,
|
||||
struct device_node *ctrlr,
|
||||
const u32 *intspec, unsigned int intsize,
|
||||
irq_hw_number_t *out_hwirq,
|
||||
unsigned int *out_type)
|
||||
{
|
||||
struct irq_domain_chip_generic *dgc = d->gc;
|
||||
struct irq_chip_generic *gc;
|
||||
unsigned smr;
|
||||
int idx;
|
||||
int ret;
|
||||
|
||||
if (!dgc)
|
||||
return -EINVAL;
|
||||
|
||||
ret = aic_common_irq_domain_xlate(d, ctrlr, intspec, intsize,
|
||||
out_hwirq, out_type);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
idx = intspec[0] / dgc->irqs_per_chip;
|
||||
if (idx >= dgc->num_chips)
|
||||
return -EINVAL;
|
||||
|
||||
gc = dgc->gc[idx];
|
||||
|
||||
irq_gc_lock(gc);
|
||||
smr = irq_reg_readl(gc->reg_base + AT91_AIC_SMR(*out_hwirq));
|
||||
ret = aic_common_set_priority(intspec[2], &smr);
|
||||
if (!ret)
|
||||
irq_reg_writel(smr, gc->reg_base + AT91_AIC_SMR(*out_hwirq));
|
||||
irq_gc_unlock(gc);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static const struct irq_domain_ops aic_irq_ops = {
|
||||
.map = irq_map_generic_chip,
|
||||
.xlate = aic_irq_domain_xlate,
|
||||
};
|
||||
|
||||
static void __init at91sam9_aic_irq_fixup(struct device_node *root)
|
||||
{
|
||||
aic_common_rtc_irq_fixup(root);
|
||||
}
|
||||
|
||||
static const struct of_device_id __initdata aic_irq_fixups[] = {
|
||||
{ .compatible = "atmel,at91sam9g45", .data = at91sam9_aic_irq_fixup },
|
||||
{ .compatible = "atmel,at91sam9n12", .data = at91sam9_aic_irq_fixup },
|
||||
{ .compatible = "atmel,at91sam9rl", .data = at91sam9_aic_irq_fixup },
|
||||
{ .compatible = "atmel,at91sam9x5", .data = at91sam9_aic_irq_fixup },
|
||||
{ /* sentinel */ },
|
||||
};
|
||||
|
||||
static int __init aic_of_init(struct device_node *node,
|
||||
struct device_node *parent)
|
||||
{
|
||||
struct irq_chip_generic *gc;
|
||||
struct irq_domain *domain;
|
||||
|
||||
if (aic_domain)
|
||||
return -EEXIST;
|
||||
|
||||
domain = aic_common_of_init(node, &aic_irq_ops, "atmel-aic",
|
||||
NR_AIC_IRQS);
|
||||
if (IS_ERR(domain))
|
||||
return PTR_ERR(domain);
|
||||
|
||||
aic_common_irq_fixup(aic_irq_fixups);
|
||||
|
||||
aic_domain = domain;
|
||||
gc = irq_get_domain_generic_chip(domain, 0);
|
||||
|
||||
gc->chip_types[0].regs.eoi = AT91_AIC_EOICR;
|
||||
gc->chip_types[0].regs.enable = AT91_AIC_IECR;
|
||||
gc->chip_types[0].regs.disable = AT91_AIC_IDCR;
|
||||
gc->chip_types[0].chip.irq_mask = irq_gc_mask_disable_reg;
|
||||
gc->chip_types[0].chip.irq_unmask = irq_gc_unmask_enable_reg;
|
||||
gc->chip_types[0].chip.irq_retrigger = aic_retrigger;
|
||||
gc->chip_types[0].chip.irq_set_type = aic_set_type;
|
||||
gc->chip_types[0].chip.irq_suspend = aic_suspend;
|
||||
gc->chip_types[0].chip.irq_resume = aic_resume;
|
||||
gc->chip_types[0].chip.irq_pm_shutdown = aic_pm_shutdown;
|
||||
|
||||
aic_hw_init(domain);
|
||||
set_handle_irq(aic_handle);
|
||||
|
||||
return 0;
|
||||
}
|
||||
IRQCHIP_DECLARE(at91rm9200_aic, "atmel,at91rm9200-aic", aic_of_init);
|
||||
|
|
@ -0,0 +1,353 @@
|
|||
/*
|
||||
* Atmel AT91 AIC5 (Advanced Interrupt Controller) driver
|
||||
*
|
||||
* Copyright (C) 2004 SAN People
|
||||
* Copyright (C) 2004 ATMEL
|
||||
* Copyright (C) Rick Bronson
|
||||
* Copyright (C) 2014 Free Electrons
|
||||
*
|
||||
* Author: Boris BREZILLON <boris.brezillon@free-electrons.com>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#include <linux/init.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/mm.h>
|
||||
#include <linux/bitmap.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/of_irq.h>
|
||||
#include <linux/irqdomain.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/io.h>
|
||||
|
||||
#include <asm/exception.h>
|
||||
#include <asm/mach/irq.h>
|
||||
|
||||
#include "irq-atmel-aic-common.h"
|
||||
#include "irqchip.h"
|
||||
|
||||
/* Number of irq lines managed by AIC */
|
||||
#define NR_AIC5_IRQS 128
|
||||
|
||||
#define AT91_AIC5_SSR 0x0
|
||||
#define AT91_AIC5_INTSEL_MSK (0x7f << 0)
|
||||
|
||||
#define AT91_AIC5_SMR 0x4
|
||||
|
||||
#define AT91_AIC5_SVR 0x8
|
||||
#define AT91_AIC5_IVR 0x10
|
||||
#define AT91_AIC5_FVR 0x14
|
||||
#define AT91_AIC5_ISR 0x18
|
||||
|
||||
#define AT91_AIC5_IPR0 0x20
|
||||
#define AT91_AIC5_IPR1 0x24
|
||||
#define AT91_AIC5_IPR2 0x28
|
||||
#define AT91_AIC5_IPR3 0x2c
|
||||
#define AT91_AIC5_IMR 0x30
|
||||
#define AT91_AIC5_CISR 0x34
|
||||
|
||||
#define AT91_AIC5_IECR 0x40
|
||||
#define AT91_AIC5_IDCR 0x44
|
||||
#define AT91_AIC5_ICCR 0x48
|
||||
#define AT91_AIC5_ISCR 0x4c
|
||||
#define AT91_AIC5_EOICR 0x38
|
||||
#define AT91_AIC5_SPU 0x3c
|
||||
#define AT91_AIC5_DCR 0x6c
|
||||
|
||||
#define AT91_AIC5_FFER 0x50
|
||||
#define AT91_AIC5_FFDR 0x54
|
||||
#define AT91_AIC5_FFSR 0x58
|
||||
|
||||
static struct irq_domain *aic5_domain;
|
||||
|
||||
static asmlinkage void __exception_irq_entry
|
||||
aic5_handle(struct pt_regs *regs)
|
||||
{
|
||||
struct irq_domain_chip_generic *dgc = aic5_domain->gc;
|
||||
struct irq_chip_generic *gc = dgc->gc[0];
|
||||
u32 irqnr;
|
||||
u32 irqstat;
|
||||
|
||||
irqnr = irq_reg_readl(gc->reg_base + AT91_AIC5_IVR);
|
||||
irqstat = irq_reg_readl(gc->reg_base + AT91_AIC5_ISR);
|
||||
|
||||
irqnr = irq_find_mapping(aic5_domain, irqnr);
|
||||
|
||||
if (!irqstat)
|
||||
irq_reg_writel(0, gc->reg_base + AT91_AIC5_EOICR);
|
||||
else
|
||||
handle_IRQ(irqnr, regs);
|
||||
}
|
||||
|
||||
static void aic5_mask(struct irq_data *d)
|
||||
{
|
||||
struct irq_domain *domain = d->domain;
|
||||
struct irq_domain_chip_generic *dgc = domain->gc;
|
||||
struct irq_chip_generic *gc = dgc->gc[0];
|
||||
|
||||
/* Disable interrupt on AIC5 */
|
||||
irq_gc_lock(gc);
|
||||
irq_reg_writel(d->hwirq, gc->reg_base + AT91_AIC5_SSR);
|
||||
irq_reg_writel(1, gc->reg_base + AT91_AIC5_IDCR);
|
||||
gc->mask_cache &= ~d->mask;
|
||||
irq_gc_unlock(gc);
|
||||
}
|
||||
|
||||
static void aic5_unmask(struct irq_data *d)
|
||||
{
|
||||
struct irq_domain *domain = d->domain;
|
||||
struct irq_domain_chip_generic *dgc = domain->gc;
|
||||
struct irq_chip_generic *gc = dgc->gc[0];
|
||||
|
||||
/* Enable interrupt on AIC5 */
|
||||
irq_gc_lock(gc);
|
||||
irq_reg_writel(d->hwirq, gc->reg_base + AT91_AIC5_SSR);
|
||||
irq_reg_writel(1, gc->reg_base + AT91_AIC5_IECR);
|
||||
gc->mask_cache |= d->mask;
|
||||
irq_gc_unlock(gc);
|
||||
}
|
||||
|
||||
static int aic5_retrigger(struct irq_data *d)
|
||||
{
|
||||
struct irq_domain *domain = d->domain;
|
||||
struct irq_domain_chip_generic *dgc = domain->gc;
|
||||
struct irq_chip_generic *gc = dgc->gc[0];
|
||||
|
||||
/* Enable interrupt on AIC5 */
|
||||
irq_gc_lock(gc);
|
||||
irq_reg_writel(d->hwirq, gc->reg_base + AT91_AIC5_SSR);
|
||||
irq_reg_writel(1, gc->reg_base + AT91_AIC5_ISCR);
|
||||
irq_gc_unlock(gc);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int aic5_set_type(struct irq_data *d, unsigned type)
|
||||
{
|
||||
struct irq_domain *domain = d->domain;
|
||||
struct irq_domain_chip_generic *dgc = domain->gc;
|
||||
struct irq_chip_generic *gc = dgc->gc[0];
|
||||
unsigned int smr;
|
||||
int ret;
|
||||
|
||||
irq_gc_lock(gc);
|
||||
irq_reg_writel(d->hwirq, gc->reg_base + AT91_AIC5_SSR);
|
||||
smr = irq_reg_readl(gc->reg_base + AT91_AIC5_SMR);
|
||||
ret = aic_common_set_type(d, type, &smr);
|
||||
if (!ret)
|
||||
irq_reg_writel(smr, gc->reg_base + AT91_AIC5_SMR);
|
||||
irq_gc_unlock(gc);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
static void aic5_suspend(struct irq_data *d)
|
||||
{
|
||||
struct irq_domain *domain = d->domain;
|
||||
struct irq_domain_chip_generic *dgc = domain->gc;
|
||||
struct irq_chip_generic *bgc = dgc->gc[0];
|
||||
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
|
||||
int i;
|
||||
u32 mask;
|
||||
|
||||
irq_gc_lock(bgc);
|
||||
for (i = 0; i < dgc->irqs_per_chip; i++) {
|
||||
mask = 1 << i;
|
||||
if ((mask & gc->mask_cache) == (mask & gc->wake_active))
|
||||
continue;
|
||||
|
||||
irq_reg_writel(i + gc->irq_base,
|
||||
bgc->reg_base + AT91_AIC5_SSR);
|
||||
if (mask & gc->wake_active)
|
||||
irq_reg_writel(1, bgc->reg_base + AT91_AIC5_IECR);
|
||||
else
|
||||
irq_reg_writel(1, bgc->reg_base + AT91_AIC5_IDCR);
|
||||
}
|
||||
irq_gc_unlock(bgc);
|
||||
}
|
||||
|
||||
static void aic5_resume(struct irq_data *d)
|
||||
{
|
||||
struct irq_domain *domain = d->domain;
|
||||
struct irq_domain_chip_generic *dgc = domain->gc;
|
||||
struct irq_chip_generic *bgc = dgc->gc[0];
|
||||
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
|
||||
int i;
|
||||
u32 mask;
|
||||
|
||||
irq_gc_lock(bgc);
|
||||
for (i = 0; i < dgc->irqs_per_chip; i++) {
|
||||
mask = 1 << i;
|
||||
if ((mask & gc->mask_cache) == (mask & gc->wake_active))
|
||||
continue;
|
||||
|
||||
irq_reg_writel(i + gc->irq_base,
|
||||
bgc->reg_base + AT91_AIC5_SSR);
|
||||
if (mask & gc->mask_cache)
|
||||
irq_reg_writel(1, bgc->reg_base + AT91_AIC5_IECR);
|
||||
else
|
||||
irq_reg_writel(1, bgc->reg_base + AT91_AIC5_IDCR);
|
||||
}
|
||||
irq_gc_unlock(bgc);
|
||||
}
|
||||
|
||||
static void aic5_pm_shutdown(struct irq_data *d)
|
||||
{
|
||||
struct irq_domain *domain = d->domain;
|
||||
struct irq_domain_chip_generic *dgc = domain->gc;
|
||||
struct irq_chip_generic *bgc = dgc->gc[0];
|
||||
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
|
||||
int i;
|
||||
|
||||
irq_gc_lock(bgc);
|
||||
for (i = 0; i < dgc->irqs_per_chip; i++) {
|
||||
irq_reg_writel(i + gc->irq_base,
|
||||
bgc->reg_base + AT91_AIC5_SSR);
|
||||
irq_reg_writel(1, bgc->reg_base + AT91_AIC5_IDCR);
|
||||
irq_reg_writel(1, bgc->reg_base + AT91_AIC5_ICCR);
|
||||
}
|
||||
irq_gc_unlock(bgc);
|
||||
}
|
||||
#else
|
||||
#define aic5_suspend NULL
|
||||
#define aic5_resume NULL
|
||||
#define aic5_pm_shutdown NULL
|
||||
#endif /* CONFIG_PM */
|
||||
|
||||
static void __init aic5_hw_init(struct irq_domain *domain)
|
||||
{
|
||||
struct irq_chip_generic *gc = irq_get_domain_generic_chip(domain, 0);
|
||||
int i;
|
||||
|
||||
/*
|
||||
* Perform 8 End Of Interrupt Command to make sure AIC
|
||||
* will not Lock out nIRQ
|
||||
*/
|
||||
for (i = 0; i < 8; i++)
|
||||
irq_reg_writel(0, gc->reg_base + AT91_AIC5_EOICR);
|
||||
|
||||
/*
|
||||
* Spurious Interrupt ID in Spurious Vector Register.
|
||||
* When there is no current interrupt, the IRQ Vector Register
|
||||
* reads the value stored in AIC_SPU
|
||||
*/
|
||||
irq_reg_writel(0xffffffff, gc->reg_base + AT91_AIC5_SPU);
|
||||
|
||||
/* No debugging in AIC: Debug (Protect) Control Register */
|
||||
irq_reg_writel(0, gc->reg_base + AT91_AIC5_DCR);
|
||||
|
||||
/* Disable and clear all interrupts initially */
|
||||
for (i = 0; i < domain->revmap_size; i++) {
|
||||
irq_reg_writel(i, gc->reg_base + AT91_AIC5_SSR);
|
||||
irq_reg_writel(i, gc->reg_base + AT91_AIC5_SVR);
|
||||
irq_reg_writel(1, gc->reg_base + AT91_AIC5_IDCR);
|
||||
irq_reg_writel(1, gc->reg_base + AT91_AIC5_ICCR);
|
||||
}
|
||||
}
|
||||
|
||||
static int aic5_irq_domain_xlate(struct irq_domain *d,
|
||||
struct device_node *ctrlr,
|
||||
const u32 *intspec, unsigned int intsize,
|
||||
irq_hw_number_t *out_hwirq,
|
||||
unsigned int *out_type)
|
||||
{
|
||||
struct irq_domain_chip_generic *dgc = d->gc;
|
||||
struct irq_chip_generic *gc;
|
||||
unsigned smr;
|
||||
int ret;
|
||||
|
||||
if (!dgc)
|
||||
return -EINVAL;
|
||||
|
||||
ret = aic_common_irq_domain_xlate(d, ctrlr, intspec, intsize,
|
||||
out_hwirq, out_type);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
gc = dgc->gc[0];
|
||||
|
||||
irq_gc_lock(gc);
|
||||
irq_reg_writel(*out_hwirq, gc->reg_base + AT91_AIC5_SSR);
|
||||
smr = irq_reg_readl(gc->reg_base + AT91_AIC5_SMR);
|
||||
ret = aic_common_set_priority(intspec[2], &smr);
|
||||
if (!ret)
|
||||
irq_reg_writel(intspec[2] | smr, gc->reg_base + AT91_AIC5_SMR);
|
||||
irq_gc_unlock(gc);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static const struct irq_domain_ops aic5_irq_ops = {
|
||||
.map = irq_map_generic_chip,
|
||||
.xlate = aic5_irq_domain_xlate,
|
||||
};
|
||||
|
||||
static void __init sama5d3_aic_irq_fixup(struct device_node *root)
|
||||
{
|
||||
aic_common_rtc_irq_fixup(root);
|
||||
}
|
||||
|
||||
static const struct of_device_id __initdata aic5_irq_fixups[] = {
|
||||
{ .compatible = "atmel,sama5d3", .data = sama5d3_aic_irq_fixup },
|
||||
{ /* sentinel */ },
|
||||
};
|
||||
|
||||
static int __init aic5_of_init(struct device_node *node,
|
||||
struct device_node *parent,
|
||||
int nirqs)
|
||||
{
|
||||
struct irq_chip_generic *gc;
|
||||
struct irq_domain *domain;
|
||||
int nchips;
|
||||
int i;
|
||||
|
||||
if (nirqs > NR_AIC5_IRQS)
|
||||
return -EINVAL;
|
||||
|
||||
if (aic5_domain)
|
||||
return -EEXIST;
|
||||
|
||||
domain = aic_common_of_init(node, &aic5_irq_ops, "atmel-aic5",
|
||||
nirqs);
|
||||
if (IS_ERR(domain))
|
||||
return PTR_ERR(domain);
|
||||
|
||||
aic_common_irq_fixup(aic5_irq_fixups);
|
||||
|
||||
aic5_domain = domain;
|
||||
nchips = aic5_domain->revmap_size / 32;
|
||||
for (i = 0; i < nchips; i++) {
|
||||
gc = irq_get_domain_generic_chip(domain, i * 32);
|
||||
|
||||
gc->chip_types[0].regs.eoi = AT91_AIC5_EOICR;
|
||||
gc->chip_types[0].chip.irq_mask = aic5_mask;
|
||||
gc->chip_types[0].chip.irq_unmask = aic5_unmask;
|
||||
gc->chip_types[0].chip.irq_retrigger = aic5_retrigger;
|
||||
gc->chip_types[0].chip.irq_set_type = aic5_set_type;
|
||||
gc->chip_types[0].chip.irq_suspend = aic5_suspend;
|
||||
gc->chip_types[0].chip.irq_resume = aic5_resume;
|
||||
gc->chip_types[0].chip.irq_pm_shutdown = aic5_pm_shutdown;
|
||||
}
|
||||
|
||||
aic5_hw_init(domain);
|
||||
set_handle_irq(aic5_handle);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#define NR_SAMA5D3_IRQS 50
|
||||
|
||||
static int __init sama5d3_aic5_of_init(struct device_node *node,
|
||||
struct device_node *parent)
|
||||
{
|
||||
return aic5_of_init(node, parent, NR_SAMA5D3_IRQS);
|
||||
}
|
||||
IRQCHIP_DECLARE(sama5d3_aic5, "atmel,sama5d3-aic", sama5d3_aic5_of_init);
|
||||
|
|
@ -0,0 +1,115 @@
|
|||
/*
|
||||
* Copyright (C) 2002 ARM Limited, All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/irqchip/arm-gic.h>
|
||||
|
||||
#include "irq-gic-common.h"
|
||||
|
||||
void gic_configure_irq(unsigned int irq, unsigned int type,
|
||||
void __iomem *base, void (*sync_access)(void))
|
||||
{
|
||||
u32 enablemask = 1 << (irq % 32);
|
||||
u32 enableoff = (irq / 32) * 4;
|
||||
u32 confmask = 0x2 << ((irq % 16) * 2);
|
||||
u32 confoff = (irq / 16) * 4;
|
||||
bool enabled = false;
|
||||
u32 val;
|
||||
|
||||
/*
|
||||
* Read current configuration register, and insert the config
|
||||
* for "irq", depending on "type".
|
||||
*/
|
||||
val = readl_relaxed(base + GIC_DIST_CONFIG + confoff);
|
||||
if (type == IRQ_TYPE_LEVEL_HIGH)
|
||||
val &= ~confmask;
|
||||
else if (type == IRQ_TYPE_EDGE_RISING)
|
||||
val |= confmask;
|
||||
|
||||
/*
|
||||
* As recommended by the spec, disable the interrupt before changing
|
||||
* the configuration
|
||||
*/
|
||||
if (readl_relaxed(base + GIC_DIST_ENABLE_SET + enableoff) & enablemask) {
|
||||
writel_relaxed(enablemask, base + GIC_DIST_ENABLE_CLEAR + enableoff);
|
||||
if (sync_access)
|
||||
sync_access();
|
||||
enabled = true;
|
||||
}
|
||||
|
||||
/*
|
||||
* Write back the new configuration, and possibly re-enable
|
||||
* the interrupt.
|
||||
*/
|
||||
writel_relaxed(val, base + GIC_DIST_CONFIG + confoff);
|
||||
|
||||
if (enabled)
|
||||
writel_relaxed(enablemask, base + GIC_DIST_ENABLE_SET + enableoff);
|
||||
|
||||
if (sync_access)
|
||||
sync_access();
|
||||
}
|
||||
|
||||
void __init gic_dist_config(void __iomem *base, int gic_irqs,
|
||||
void (*sync_access)(void))
|
||||
{
|
||||
unsigned int i;
|
||||
|
||||
/*
|
||||
* Set all global interrupts to be level triggered, active low.
|
||||
*/
|
||||
for (i = 32; i < gic_irqs; i += 16)
|
||||
writel_relaxed(0, base + GIC_DIST_CONFIG + i / 4);
|
||||
|
||||
/*
|
||||
* Set priority on all global interrupts.
|
||||
*/
|
||||
for (i = 32; i < gic_irqs; i += 4)
|
||||
writel_relaxed(0xa0a0a0a0, base + GIC_DIST_PRI + i);
|
||||
|
||||
/*
|
||||
* Disable all interrupts. Leave the PPI and SGIs alone
|
||||
* as they are enabled by redistributor registers.
|
||||
*/
|
||||
for (i = 32; i < gic_irqs; i += 32)
|
||||
writel_relaxed(0xffffffff, base + GIC_DIST_ENABLE_CLEAR + i / 8);
|
||||
|
||||
if (sync_access)
|
||||
sync_access();
|
||||
}
|
||||
|
||||
void gic_cpu_config(void __iomem *base, void (*sync_access)(void))
|
||||
{
|
||||
int i;
|
||||
|
||||
/*
|
||||
* Deal with the banked PPI and SGI interrupts - disable all
|
||||
* PPI interrupts, ensure all SGI interrupts are enabled.
|
||||
*/
|
||||
writel_relaxed(0xffff0000, base + GIC_DIST_ENABLE_CLEAR);
|
||||
writel_relaxed(0x0000ffff, base + GIC_DIST_ENABLE_SET);
|
||||
|
||||
/*
|
||||
* Set priority on PPI and SGI interrupts
|
||||
*/
|
||||
for (i = 0; i < 32; i += 4)
|
||||
writel_relaxed(0xa0a0a0a0, base + GIC_DIST_PRI + i * 4 / 4);
|
||||
|
||||
if (sync_access)
|
||||
sync_access();
|
||||
}
|
||||
|
|
@ -0,0 +1,29 @@
|
|||
/*
|
||||
* Copyright (C) 2002 ARM Limited, All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef _IRQ_GIC_COMMON_H
|
||||
#define _IRQ_GIC_COMMON_H
|
||||
|
||||
#include <linux/of.h>
|
||||
#include <linux/irqdomain.h>
|
||||
|
||||
void gic_configure_irq(unsigned int irq, unsigned int type,
|
||||
void __iomem *base, void (*sync_access)(void));
|
||||
void gic_dist_config(void __iomem *base, int gic_irqs,
|
||||
void (*sync_access)(void));
|
||||
void gic_cpu_config(void __iomem *base, void (*sync_access)(void));
|
||||
|
||||
#endif /* _IRQ_GIC_COMMON_H */
|
||||
|
|
@ -0,0 +1,692 @@
|
|||
/*
|
||||
* Copyright (C) 2013, 2014 ARM Limited, All Rights Reserved.
|
||||
* Author: Marc Zyngier <marc.zyngier@arm.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#include <linux/cpu.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/of_irq.h>
|
||||
#include <linux/percpu.h>
|
||||
#include <linux/slab.h>
|
||||
|
||||
#include <linux/irqchip/arm-gic-v3.h>
|
||||
|
||||
#include <asm/cputype.h>
|
||||
#include <asm/exception.h>
|
||||
#include <asm/smp_plat.h>
|
||||
|
||||
#include "irq-gic-common.h"
|
||||
#include "irqchip.h"
|
||||
|
||||
struct gic_chip_data {
|
||||
void __iomem *dist_base;
|
||||
void __iomem **redist_base;
|
||||
void __percpu __iomem **rdist;
|
||||
struct irq_domain *domain;
|
||||
u64 redist_stride;
|
||||
u32 redist_regions;
|
||||
unsigned int irq_nr;
|
||||
};
|
||||
|
||||
static struct gic_chip_data gic_data __read_mostly;
|
||||
|
||||
#define gic_data_rdist() (this_cpu_ptr(gic_data.rdist))
|
||||
#define gic_data_rdist_rd_base() (*gic_data_rdist())
|
||||
#define gic_data_rdist_sgi_base() (gic_data_rdist_rd_base() + SZ_64K)
|
||||
|
||||
/* Our default, arbitrary priority value. Linux only uses one anyway. */
|
||||
#define DEFAULT_PMR_VALUE 0xf0
|
||||
|
||||
static inline unsigned int gic_irq(struct irq_data *d)
|
||||
{
|
||||
return d->hwirq;
|
||||
}
|
||||
|
||||
static inline int gic_irq_in_rdist(struct irq_data *d)
|
||||
{
|
||||
return gic_irq(d) < 32;
|
||||
}
|
||||
|
||||
static inline void __iomem *gic_dist_base(struct irq_data *d)
|
||||
{
|
||||
if (gic_irq_in_rdist(d)) /* SGI+PPI -> SGI_base for this CPU */
|
||||
return gic_data_rdist_sgi_base();
|
||||
|
||||
if (d->hwirq <= 1023) /* SPI -> dist_base */
|
||||
return gic_data.dist_base;
|
||||
|
||||
if (d->hwirq >= 8192)
|
||||
BUG(); /* LPI Detected!!! */
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static void gic_do_wait_for_rwp(void __iomem *base)
|
||||
{
|
||||
u32 count = 1000000; /* 1s! */
|
||||
|
||||
while (readl_relaxed(base + GICD_CTLR) & GICD_CTLR_RWP) {
|
||||
count--;
|
||||
if (!count) {
|
||||
pr_err_ratelimited("RWP timeout, gone fishing\n");
|
||||
return;
|
||||
}
|
||||
cpu_relax();
|
||||
udelay(1);
|
||||
};
|
||||
}
|
||||
|
||||
/* Wait for completion of a distributor change */
|
||||
static void gic_dist_wait_for_rwp(void)
|
||||
{
|
||||
gic_do_wait_for_rwp(gic_data.dist_base);
|
||||
}
|
||||
|
||||
/* Wait for completion of a redistributor change */
|
||||
static void gic_redist_wait_for_rwp(void)
|
||||
{
|
||||
gic_do_wait_for_rwp(gic_data_rdist_rd_base());
|
||||
}
|
||||
|
||||
/* Low level accessors */
|
||||
static u64 gic_read_iar(void)
|
||||
{
|
||||
u64 irqstat;
|
||||
|
||||
asm volatile("mrs %0, " __stringify(ICC_IAR1_EL1) : "=r" (irqstat));
|
||||
return irqstat;
|
||||
}
|
||||
|
||||
static void gic_write_pmr(u64 val)
|
||||
{
|
||||
asm volatile("msr " __stringify(ICC_PMR_EL1) ", %0" : : "r" (val));
|
||||
}
|
||||
|
||||
static void gic_write_ctlr(u64 val)
|
||||
{
|
||||
asm volatile("msr " __stringify(ICC_CTLR_EL1) ", %0" : : "r" (val));
|
||||
isb();
|
||||
}
|
||||
|
||||
static void gic_write_grpen1(u64 val)
|
||||
{
|
||||
asm volatile("msr " __stringify(ICC_GRPEN1_EL1) ", %0" : : "r" (val));
|
||||
isb();
|
||||
}
|
||||
|
||||
static void gic_write_sgi1r(u64 val)
|
||||
{
|
||||
asm volatile("msr " __stringify(ICC_SGI1R_EL1) ", %0" : : "r" (val));
|
||||
}
|
||||
|
||||
static void gic_enable_sre(void)
|
||||
{
|
||||
u64 val;
|
||||
|
||||
asm volatile("mrs %0, " __stringify(ICC_SRE_EL1) : "=r" (val));
|
||||
val |= ICC_SRE_EL1_SRE;
|
||||
asm volatile("msr " __stringify(ICC_SRE_EL1) ", %0" : : "r" (val));
|
||||
isb();
|
||||
|
||||
/*
|
||||
* Need to check that the SRE bit has actually been set. If
|
||||
* not, it means that SRE is disabled at EL2. We're going to
|
||||
* die painfully, and there is nothing we can do about it.
|
||||
*
|
||||
* Kindly inform the luser.
|
||||
*/
|
||||
asm volatile("mrs %0, " __stringify(ICC_SRE_EL1) : "=r" (val));
|
||||
if (!(val & ICC_SRE_EL1_SRE))
|
||||
pr_err("GIC: unable to set SRE (disabled at EL2), panic ahead\n");
|
||||
}
|
||||
|
||||
static void gic_enable_redist(void)
|
||||
{
|
||||
void __iomem *rbase;
|
||||
u32 count = 1000000; /* 1s! */
|
||||
u32 val;
|
||||
|
||||
rbase = gic_data_rdist_rd_base();
|
||||
|
||||
/* Wake up this CPU redistributor */
|
||||
val = readl_relaxed(rbase + GICR_WAKER);
|
||||
val &= ~GICR_WAKER_ProcessorSleep;
|
||||
writel_relaxed(val, rbase + GICR_WAKER);
|
||||
|
||||
while (readl_relaxed(rbase + GICR_WAKER) & GICR_WAKER_ChildrenAsleep) {
|
||||
count--;
|
||||
if (!count) {
|
||||
pr_err_ratelimited("redist didn't wake up...\n");
|
||||
return;
|
||||
}
|
||||
cpu_relax();
|
||||
udelay(1);
|
||||
};
|
||||
}
|
||||
|
||||
/*
|
||||
* Routines to disable, enable, EOI and route interrupts
|
||||
*/
|
||||
static void gic_poke_irq(struct irq_data *d, u32 offset)
|
||||
{
|
||||
u32 mask = 1 << (gic_irq(d) % 32);
|
||||
void (*rwp_wait)(void);
|
||||
void __iomem *base;
|
||||
|
||||
if (gic_irq_in_rdist(d)) {
|
||||
base = gic_data_rdist_sgi_base();
|
||||
rwp_wait = gic_redist_wait_for_rwp;
|
||||
} else {
|
||||
base = gic_data.dist_base;
|
||||
rwp_wait = gic_dist_wait_for_rwp;
|
||||
}
|
||||
|
||||
writel_relaxed(mask, base + offset + (gic_irq(d) / 32) * 4);
|
||||
rwp_wait();
|
||||
}
|
||||
|
||||
static int gic_peek_irq(struct irq_data *d, u32 offset)
|
||||
{
|
||||
u32 mask = 1 << (gic_irq(d) % 32);
|
||||
void __iomem *base;
|
||||
|
||||
if (gic_irq_in_rdist(d))
|
||||
base = gic_data_rdist_sgi_base();
|
||||
else
|
||||
base = gic_data.dist_base;
|
||||
|
||||
return !!(readl_relaxed(base + offset + (gic_irq(d) / 32) * 4) & mask);
|
||||
}
|
||||
|
||||
static void gic_mask_irq(struct irq_data *d)
|
||||
{
|
||||
gic_poke_irq(d, GICD_ICENABLER);
|
||||
}
|
||||
|
||||
static void gic_unmask_irq(struct irq_data *d)
|
||||
{
|
||||
gic_poke_irq(d, GICD_ISENABLER);
|
||||
}
|
||||
|
||||
static void gic_eoi_irq(struct irq_data *d)
|
||||
{
|
||||
gic_write_eoir(gic_irq(d));
|
||||
}
|
||||
|
||||
static int gic_set_type(struct irq_data *d, unsigned int type)
|
||||
{
|
||||
unsigned int irq = gic_irq(d);
|
||||
void (*rwp_wait)(void);
|
||||
void __iomem *base;
|
||||
|
||||
/* Interrupt configuration for SGIs can't be changed */
|
||||
if (irq < 16)
|
||||
return -EINVAL;
|
||||
|
||||
if (type != IRQ_TYPE_LEVEL_HIGH && type != IRQ_TYPE_EDGE_RISING)
|
||||
return -EINVAL;
|
||||
|
||||
if (gic_irq_in_rdist(d)) {
|
||||
base = gic_data_rdist_sgi_base();
|
||||
rwp_wait = gic_redist_wait_for_rwp;
|
||||
} else {
|
||||
base = gic_data.dist_base;
|
||||
rwp_wait = gic_dist_wait_for_rwp;
|
||||
}
|
||||
|
||||
gic_configure_irq(irq, type, base, rwp_wait);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static u64 gic_mpidr_to_affinity(u64 mpidr)
|
||||
{
|
||||
u64 aff;
|
||||
|
||||
aff = (MPIDR_AFFINITY_LEVEL(mpidr, 3) << 32 |
|
||||
MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 |
|
||||
MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 |
|
||||
MPIDR_AFFINITY_LEVEL(mpidr, 0));
|
||||
|
||||
return aff;
|
||||
}
|
||||
|
||||
static asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)
|
||||
{
|
||||
u64 irqnr;
|
||||
|
||||
do {
|
||||
irqnr = gic_read_iar();
|
||||
|
||||
if (likely(irqnr > 15 && irqnr < 1020)) {
|
||||
u64 irq = irq_find_mapping(gic_data.domain, irqnr);
|
||||
if (likely(irq)) {
|
||||
handle_IRQ(irq, regs);
|
||||
continue;
|
||||
}
|
||||
|
||||
WARN_ONCE(true, "Unexpected SPI received!\n");
|
||||
gic_write_eoir(irqnr);
|
||||
}
|
||||
if (irqnr < 16) {
|
||||
gic_write_eoir(irqnr);
|
||||
#ifdef CONFIG_SMP
|
||||
handle_IPI(irqnr, regs);
|
||||
#else
|
||||
WARN_ONCE(true, "Unexpected SGI received!\n");
|
||||
#endif
|
||||
continue;
|
||||
}
|
||||
} while (irqnr != ICC_IAR1_EL1_SPURIOUS);
|
||||
}
|
||||
|
||||
static void __init gic_dist_init(void)
|
||||
{
|
||||
unsigned int i;
|
||||
u64 affinity;
|
||||
void __iomem *base = gic_data.dist_base;
|
||||
|
||||
/* Disable the distributor */
|
||||
writel_relaxed(0, base + GICD_CTLR);
|
||||
gic_dist_wait_for_rwp();
|
||||
|
||||
gic_dist_config(base, gic_data.irq_nr, gic_dist_wait_for_rwp);
|
||||
|
||||
/* Enable distributor with ARE, Group1 */
|
||||
writel_relaxed(GICD_CTLR_ARE_NS | GICD_CTLR_ENABLE_G1A | GICD_CTLR_ENABLE_G1,
|
||||
base + GICD_CTLR);
|
||||
|
||||
/*
|
||||
* Set all global interrupts to the boot CPU only. ARE must be
|
||||
* enabled.
|
||||
*/
|
||||
affinity = gic_mpidr_to_affinity(cpu_logical_map(smp_processor_id()));
|
||||
for (i = 32; i < gic_data.irq_nr; i++)
|
||||
writeq_relaxed(affinity, base + GICD_IROUTER + i * 8);
|
||||
}
|
||||
|
||||
static int gic_populate_rdist(void)
|
||||
{
|
||||
u64 mpidr = cpu_logical_map(smp_processor_id());
|
||||
u64 typer;
|
||||
u32 aff;
|
||||
int i;
|
||||
|
||||
/*
|
||||
* Convert affinity to a 32bit value that can be matched to
|
||||
* GICR_TYPER bits [63:32].
|
||||
*/
|
||||
aff = (MPIDR_AFFINITY_LEVEL(mpidr, 3) << 24 |
|
||||
MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 |
|
||||
MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 |
|
||||
MPIDR_AFFINITY_LEVEL(mpidr, 0));
|
||||
|
||||
for (i = 0; i < gic_data.redist_regions; i++) {
|
||||
void __iomem *ptr = gic_data.redist_base[i];
|
||||
u32 reg;
|
||||
|
||||
reg = readl_relaxed(ptr + GICR_PIDR2) & GIC_PIDR2_ARCH_MASK;
|
||||
if (reg != GIC_PIDR2_ARCH_GICv3 &&
|
||||
reg != GIC_PIDR2_ARCH_GICv4) { /* We're in trouble... */
|
||||
pr_warn("No redistributor present @%p\n", ptr);
|
||||
break;
|
||||
}
|
||||
|
||||
do {
|
||||
typer = readq_relaxed(ptr + GICR_TYPER);
|
||||
if ((typer >> 32) == aff) {
|
||||
gic_data_rdist_rd_base() = ptr;
|
||||
pr_info("CPU%d: found redistributor %llx @%p\n",
|
||||
smp_processor_id(),
|
||||
(unsigned long long)mpidr, ptr);
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (gic_data.redist_stride) {
|
||||
ptr += gic_data.redist_stride;
|
||||
} else {
|
||||
ptr += SZ_64K * 2; /* Skip RD_base + SGI_base */
|
||||
if (typer & GICR_TYPER_VLPIS)
|
||||
ptr += SZ_64K * 2; /* Skip VLPI_base + reserved page */
|
||||
}
|
||||
} while (!(typer & GICR_TYPER_LAST));
|
||||
}
|
||||
|
||||
/* We couldn't even deal with ourselves... */
|
||||
WARN(true, "CPU%d: mpidr %llx has no re-distributor!\n",
|
||||
smp_processor_id(), (unsigned long long)mpidr);
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
static void gic_cpu_init(void)
|
||||
{
|
||||
void __iomem *rbase;
|
||||
|
||||
/* Register ourselves with the rest of the world */
|
||||
if (gic_populate_rdist())
|
||||
return;
|
||||
|
||||
gic_enable_redist();
|
||||
|
||||
rbase = gic_data_rdist_sgi_base();
|
||||
|
||||
gic_cpu_config(rbase, gic_redist_wait_for_rwp);
|
||||
|
||||
/* Enable system registers */
|
||||
gic_enable_sre();
|
||||
|
||||
/* Set priority mask register */
|
||||
gic_write_pmr(DEFAULT_PMR_VALUE);
|
||||
|
||||
/* EOI deactivates interrupt too (mode 0) */
|
||||
gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop_dir);
|
||||
|
||||
/* ... and let's hit the road... */
|
||||
gic_write_grpen1(1);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
static int gic_secondary_init(struct notifier_block *nfb,
|
||||
unsigned long action, void *hcpu)
|
||||
{
|
||||
if (action == CPU_STARTING || action == CPU_STARTING_FROZEN)
|
||||
gic_cpu_init();
|
||||
return NOTIFY_OK;
|
||||
}
|
||||
|
||||
/*
|
||||
* Notifier for enabling the GIC CPU interface. Set an arbitrarily high
|
||||
* priority because the GIC needs to be up before the ARM generic timers.
|
||||
*/
|
||||
static struct notifier_block gic_cpu_notifier = {
|
||||
.notifier_call = gic_secondary_init,
|
||||
.priority = 100,
|
||||
};
|
||||
|
||||
static u16 gic_compute_target_list(int *base_cpu, const struct cpumask *mask,
|
||||
u64 cluster_id)
|
||||
{
|
||||
int cpu = *base_cpu;
|
||||
u64 mpidr = cpu_logical_map(cpu);
|
||||
u16 tlist = 0;
|
||||
|
||||
while (cpu < nr_cpu_ids) {
|
||||
/*
|
||||
* If we ever get a cluster of more than 16 CPUs, just
|
||||
* scream and skip that CPU.
|
||||
*/
|
||||
if (WARN_ON((mpidr & 0xff) >= 16))
|
||||
goto out;
|
||||
|
||||
tlist |= 1 << (mpidr & 0xf);
|
||||
|
||||
cpu = cpumask_next(cpu, mask);
|
||||
if (cpu == nr_cpu_ids)
|
||||
goto out;
|
||||
|
||||
mpidr = cpu_logical_map(cpu);
|
||||
|
||||
if (cluster_id != (mpidr & ~0xffUL)) {
|
||||
cpu--;
|
||||
goto out;
|
||||
}
|
||||
}
|
||||
out:
|
||||
*base_cpu = cpu;
|
||||
return tlist;
|
||||
}
|
||||
|
||||
static void gic_send_sgi(u64 cluster_id, u16 tlist, unsigned int irq)
|
||||
{
|
||||
u64 val;
|
||||
|
||||
val = (MPIDR_AFFINITY_LEVEL(cluster_id, 3) << 48 |
|
||||
MPIDR_AFFINITY_LEVEL(cluster_id, 2) << 32 |
|
||||
irq << 24 |
|
||||
MPIDR_AFFINITY_LEVEL(cluster_id, 1) << 16 |
|
||||
tlist);
|
||||
|
||||
pr_debug("CPU%d: ICC_SGI1R_EL1 %llx\n", smp_processor_id(), val);
|
||||
gic_write_sgi1r(val);
|
||||
}
|
||||
|
||||
static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq)
|
||||
{
|
||||
int cpu;
|
||||
|
||||
if (WARN_ON(irq >= 16))
|
||||
return;
|
||||
|
||||
/*
|
||||
* Ensure that stores to Normal memory are visible to the
|
||||
* other CPUs before issuing the IPI.
|
||||
*/
|
||||
smp_wmb();
|
||||
|
||||
for_each_cpu_mask(cpu, *mask) {
|
||||
u64 cluster_id = cpu_logical_map(cpu) & ~0xffUL;
|
||||
u16 tlist;
|
||||
|
||||
tlist = gic_compute_target_list(&cpu, mask, cluster_id);
|
||||
gic_send_sgi(cluster_id, tlist, irq);
|
||||
}
|
||||
|
||||
/* Force the above writes to ICC_SGI1R_EL1 to be executed */
|
||||
isb();
|
||||
}
|
||||
|
||||
static void gic_smp_init(void)
|
||||
{
|
||||
set_smp_cross_call(gic_raise_softirq);
|
||||
register_cpu_notifier(&gic_cpu_notifier);
|
||||
}
|
||||
|
||||
static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
|
||||
bool force)
|
||||
{
|
||||
unsigned int cpu = cpumask_any_and(mask_val, cpu_online_mask);
|
||||
void __iomem *reg;
|
||||
int enabled;
|
||||
u64 val;
|
||||
|
||||
if (gic_irq_in_rdist(d))
|
||||
return -EINVAL;
|
||||
|
||||
/* If interrupt was enabled, disable it first */
|
||||
enabled = gic_peek_irq(d, GICD_ISENABLER);
|
||||
if (enabled)
|
||||
gic_mask_irq(d);
|
||||
|
||||
reg = gic_dist_base(d) + GICD_IROUTER + (gic_irq(d) * 8);
|
||||
val = gic_mpidr_to_affinity(cpu_logical_map(cpu));
|
||||
|
||||
writeq_relaxed(val, reg);
|
||||
|
||||
/*
|
||||
* If the interrupt was enabled, enabled it again. Otherwise,
|
||||
* just wait for the distributor to have digested our changes.
|
||||
*/
|
||||
if (enabled)
|
||||
gic_unmask_irq(d);
|
||||
else
|
||||
gic_dist_wait_for_rwp();
|
||||
|
||||
return IRQ_SET_MASK_OK;
|
||||
}
|
||||
#else
|
||||
#define gic_set_affinity NULL
|
||||
#define gic_smp_init() do { } while(0)
|
||||
#endif
|
||||
|
||||
static struct irq_chip gic_chip = {
|
||||
.name = "GICv3",
|
||||
.irq_mask = gic_mask_irq,
|
||||
.irq_unmask = gic_unmask_irq,
|
||||
.irq_eoi = gic_eoi_irq,
|
||||
.irq_set_type = gic_set_type,
|
||||
.irq_set_affinity = gic_set_affinity,
|
||||
};
|
||||
|
||||
static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq,
|
||||
irq_hw_number_t hw)
|
||||
{
|
||||
/* SGIs are private to the core kernel */
|
||||
if (hw < 16)
|
||||
return -EPERM;
|
||||
/* PPIs */
|
||||
if (hw < 32) {
|
||||
irq_set_percpu_devid(irq);
|
||||
irq_set_chip_and_handler(irq, &gic_chip,
|
||||
handle_percpu_devid_irq);
|
||||
set_irq_flags(irq, IRQF_VALID | IRQF_NOAUTOEN);
|
||||
}
|
||||
/* SPIs */
|
||||
if (hw >= 32 && hw < gic_data.irq_nr) {
|
||||
irq_set_chip_and_handler(irq, &gic_chip,
|
||||
handle_fasteoi_irq);
|
||||
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
|
||||
}
|
||||
irq_set_chip_data(irq, d->host_data);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int gic_irq_domain_xlate(struct irq_domain *d,
|
||||
struct device_node *controller,
|
||||
const u32 *intspec, unsigned int intsize,
|
||||
unsigned long *out_hwirq, unsigned int *out_type)
|
||||
{
|
||||
if (d->of_node != controller)
|
||||
return -EINVAL;
|
||||
if (intsize < 3)
|
||||
return -EINVAL;
|
||||
|
||||
switch(intspec[0]) {
|
||||
case 0: /* SPI */
|
||||
*out_hwirq = intspec[1] + 32;
|
||||
break;
|
||||
case 1: /* PPI */
|
||||
*out_hwirq = intspec[1] + 16;
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
*out_type = intspec[2] & IRQ_TYPE_SENSE_MASK;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct irq_domain_ops gic_irq_domain_ops = {
|
||||
.map = gic_irq_domain_map,
|
||||
.xlate = gic_irq_domain_xlate,
|
||||
};
|
||||
|
||||
static int __init gic_of_init(struct device_node *node, struct device_node *parent)
|
||||
{
|
||||
void __iomem *dist_base;
|
||||
void __iomem **redist_base;
|
||||
u64 redist_stride;
|
||||
u32 redist_regions;
|
||||
u32 reg;
|
||||
int gic_irqs;
|
||||
int err;
|
||||
int i;
|
||||
|
||||
dist_base = of_iomap(node, 0);
|
||||
if (!dist_base) {
|
||||
pr_err("%s: unable to map gic dist registers\n",
|
||||
node->full_name);
|
||||
return -ENXIO;
|
||||
}
|
||||
|
||||
reg = readl_relaxed(dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK;
|
||||
if (reg != GIC_PIDR2_ARCH_GICv3 && reg != GIC_PIDR2_ARCH_GICv4) {
|
||||
pr_err("%s: no distributor detected, giving up\n",
|
||||
node->full_name);
|
||||
err = -ENODEV;
|
||||
goto out_unmap_dist;
|
||||
}
|
||||
|
||||
if (of_property_read_u32(node, "#redistributor-regions", &redist_regions))
|
||||
redist_regions = 1;
|
||||
|
||||
redist_base = kzalloc(sizeof(*redist_base) * redist_regions, GFP_KERNEL);
|
||||
if (!redist_base) {
|
||||
err = -ENOMEM;
|
||||
goto out_unmap_dist;
|
||||
}
|
||||
|
||||
for (i = 0; i < redist_regions; i++) {
|
||||
redist_base[i] = of_iomap(node, 1 + i);
|
||||
if (!redist_base[i]) {
|
||||
pr_err("%s: couldn't map region %d\n",
|
||||
node->full_name, i);
|
||||
err = -ENODEV;
|
||||
goto out_unmap_rdist;
|
||||
}
|
||||
}
|
||||
|
||||
if (of_property_read_u64(node, "redistributor-stride", &redist_stride))
|
||||
redist_stride = 0;
|
||||
|
||||
gic_data.dist_base = dist_base;
|
||||
gic_data.redist_base = redist_base;
|
||||
gic_data.redist_regions = redist_regions;
|
||||
gic_data.redist_stride = redist_stride;
|
||||
|
||||
/*
|
||||
* Find out how many interrupts are supported.
|
||||
* The GIC only supports up to 1020 interrupt sources (SGI+PPI+SPI)
|
||||
*/
|
||||
gic_irqs = readl_relaxed(gic_data.dist_base + GICD_TYPER) & 0x1f;
|
||||
gic_irqs = (gic_irqs + 1) * 32;
|
||||
if (gic_irqs > 1020)
|
||||
gic_irqs = 1020;
|
||||
gic_data.irq_nr = gic_irqs;
|
||||
|
||||
gic_data.domain = irq_domain_add_tree(node, &gic_irq_domain_ops,
|
||||
&gic_data);
|
||||
gic_data.rdist = alloc_percpu(typeof(*gic_data.rdist));
|
||||
|
||||
if (WARN_ON(!gic_data.domain) || WARN_ON(!gic_data.rdist)) {
|
||||
err = -ENOMEM;
|
||||
goto out_free;
|
||||
}
|
||||
|
||||
set_handle_irq(gic_handle_irq);
|
||||
|
||||
gic_smp_init();
|
||||
gic_dist_init();
|
||||
gic_cpu_init();
|
||||
|
||||
return 0;
|
||||
|
||||
out_free:
|
||||
if (gic_data.domain)
|
||||
irq_domain_remove(gic_data.domain);
|
||||
free_percpu(gic_data.rdist);
|
||||
out_unmap_rdist:
|
||||
for (i = 0; i < redist_regions; i++)
|
||||
if (redist_base[i])
|
||||
iounmap(redist_base[i]);
|
||||
kfree(redist_base);
|
||||
out_unmap_dist:
|
||||
iounmap(dist_base);
|
||||
return err;
|
||||
}
|
||||
|
||||
IRQCHIP_DECLARE(gic_v3, "arm,gic-v3", gic_of_init);
|
||||
|
|
@ -46,6 +46,7 @@
|
|||
#include <asm/exception.h>
|
||||
#include <asm/smp_plat.h>
|
||||
|
||||
#include "irq-gic-common.h"
|
||||
#include "irqchip.h"
|
||||
|
||||
union gic_base {
|
||||
|
|
@ -188,12 +189,6 @@ static int gic_set_type(struct irq_data *d, unsigned int type)
|
|||
{
|
||||
void __iomem *base = gic_dist_base(d);
|
||||
unsigned int gicirq = gic_irq(d);
|
||||
u32 enablemask = 1 << (gicirq % 32);
|
||||
u32 enableoff = (gicirq / 32) * 4;
|
||||
u32 confmask = 0x2 << ((gicirq % 16) * 2);
|
||||
u32 confoff = (gicirq / 16) * 4;
|
||||
bool enabled = false;
|
||||
u32 val;
|
||||
|
||||
/* Interrupt configuration for SGIs can't be changed */
|
||||
if (gicirq < 16)
|
||||
|
|
@ -207,25 +202,7 @@ static int gic_set_type(struct irq_data *d, unsigned int type)
|
|||
if (gic_arch_extn.irq_set_type)
|
||||
gic_arch_extn.irq_set_type(d, type);
|
||||
|
||||
val = readl_relaxed(base + GIC_DIST_CONFIG + confoff);
|
||||
if (type == IRQ_TYPE_LEVEL_HIGH)
|
||||
val &= ~confmask;
|
||||
else if (type == IRQ_TYPE_EDGE_RISING)
|
||||
val |= confmask;
|
||||
|
||||
/*
|
||||
* As recommended by the spec, disable the interrupt before changing
|
||||
* the configuration
|
||||
*/
|
||||
if (readl_relaxed(base + GIC_DIST_ENABLE_SET + enableoff) & enablemask) {
|
||||
writel_relaxed(enablemask, base + GIC_DIST_ENABLE_CLEAR + enableoff);
|
||||
enabled = true;
|
||||
}
|
||||
|
||||
writel_relaxed(val, base + GIC_DIST_CONFIG + confoff);
|
||||
|
||||
if (enabled)
|
||||
writel_relaxed(enablemask, base + GIC_DIST_ENABLE_SET + enableoff);
|
||||
gic_configure_irq(gicirq, type, base, NULL);
|
||||
|
||||
raw_spin_unlock(&irq_controller_lock);
|
||||
|
||||
|
|
@ -386,12 +363,6 @@ static void __init gic_dist_init(struct gic_chip_data *gic)
|
|||
|
||||
writel_relaxed(0, base + GIC_DIST_CTRL);
|
||||
|
||||
/*
|
||||
* Set all global interrupts to be level triggered, active low.
|
||||
*/
|
||||
for (i = 32; i < gic_irqs; i += 16)
|
||||
writel_relaxed(0, base + GIC_DIST_CONFIG + i * 4 / 16);
|
||||
|
||||
/*
|
||||
* Set all global interrupts to this CPU only.
|
||||
*/
|
||||
|
|
@ -401,18 +372,7 @@ static void __init gic_dist_init(struct gic_chip_data *gic)
|
|||
for (i = 32; i < gic_irqs; i += 4)
|
||||
writel_relaxed(cpumask, base + GIC_DIST_TARGET + i * 4 / 4);
|
||||
|
||||
/*
|
||||
* Set priority on all global interrupts.
|
||||
*/
|
||||
for (i = 32; i < gic_irqs; i += 4)
|
||||
writel_relaxed(0xa0a0a0a0, base + GIC_DIST_PRI + i * 4 / 4);
|
||||
|
||||
/*
|
||||
* Disable all interrupts. Leave the PPI and SGIs alone
|
||||
* as these enables are banked registers.
|
||||
*/
|
||||
for (i = 32; i < gic_irqs; i += 32)
|
||||
writel_relaxed(0xffffffff, base + GIC_DIST_ENABLE_CLEAR + i * 4 / 32);
|
||||
gic_dist_config(base, gic_irqs, NULL);
|
||||
|
||||
writel_relaxed(1, base + GIC_DIST_CTRL);
|
||||
}
|
||||
|
|
@ -439,18 +399,7 @@ static void gic_cpu_init(struct gic_chip_data *gic)
|
|||
if (i != cpu)
|
||||
gic_cpu_map[i] &= ~cpu_mask;
|
||||
|
||||
/*
|
||||
* Deal with the banked PPI and SGI interrupts - disable all
|
||||
* PPI interrupts, ensure all SGI interrupts are enabled.
|
||||
*/
|
||||
writel_relaxed(0xffff0000, dist_base + GIC_DIST_ENABLE_CLEAR);
|
||||
writel_relaxed(0x0000ffff, dist_base + GIC_DIST_ENABLE_SET);
|
||||
|
||||
/*
|
||||
* Set priority on PPI and SGI interrupts
|
||||
*/
|
||||
for (i = 0; i < 32; i += 4)
|
||||
writel_relaxed(0xa0a0a0a0, dist_base + GIC_DIST_PRI + i * 4 / 4);
|
||||
gic_cpu_config(dist_base, NULL);
|
||||
|
||||
writel_relaxed(0xf0, base + GIC_CPU_PRIMASK);
|
||||
writel_relaxed(1, base + GIC_CPU_CTRL);
|
||||
|
|
|
|||
|
|
@ -771,6 +771,8 @@ void irq_gc_eoi(struct irq_data *d);
|
|||
int irq_gc_set_wake(struct irq_data *d, unsigned int on);
|
||||
|
||||
/* Setup functions for irq_chip_generic */
|
||||
int irq_map_generic_chip(struct irq_domain *d, unsigned int virq,
|
||||
irq_hw_number_t hw_irq);
|
||||
struct irq_chip_generic *
|
||||
irq_alloc_generic_chip(const char *name, int nr_ct, unsigned int irq_base,
|
||||
void __iomem *reg_base, irq_flow_handler_t handler);
|
||||
|
|
|
|||
|
|
@ -0,0 +1,198 @@
|
|||
/*
|
||||
* Copyright (C) 2013, 2014 ARM Limited, All Rights Reserved.
|
||||
* Author: Marc Zyngier <marc.zyngier@arm.com>
|
||||
*
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
#ifndef __LINUX_IRQCHIP_ARM_GIC_V3_H
|
||||
#define __LINUX_IRQCHIP_ARM_GIC_V3_H
|
||||
|
||||
/*
|
||||
* Distributor registers. We assume we're running non-secure, with ARE
|
||||
* being set. Secure-only and non-ARE registers are not described.
|
||||
*/
|
||||
#define GICD_CTLR 0x0000
|
||||
#define GICD_TYPER 0x0004
|
||||
#define GICD_IIDR 0x0008
|
||||
#define GICD_STATUSR 0x0010
|
||||
#define GICD_SETSPI_NSR 0x0040
|
||||
#define GICD_CLRSPI_NSR 0x0048
|
||||
#define GICD_SETSPI_SR 0x0050
|
||||
#define GICD_CLRSPI_SR 0x0058
|
||||
#define GICD_SEIR 0x0068
|
||||
#define GICD_ISENABLER 0x0100
|
||||
#define GICD_ICENABLER 0x0180
|
||||
#define GICD_ISPENDR 0x0200
|
||||
#define GICD_ICPENDR 0x0280
|
||||
#define GICD_ISACTIVER 0x0300
|
||||
#define GICD_ICACTIVER 0x0380
|
||||
#define GICD_IPRIORITYR 0x0400
|
||||
#define GICD_ICFGR 0x0C00
|
||||
#define GICD_IROUTER 0x6000
|
||||
#define GICD_PIDR2 0xFFE8
|
||||
|
||||
#define GICD_CTLR_RWP (1U << 31)
|
||||
#define GICD_CTLR_ARE_NS (1U << 4)
|
||||
#define GICD_CTLR_ENABLE_G1A (1U << 1)
|
||||
#define GICD_CTLR_ENABLE_G1 (1U << 0)
|
||||
|
||||
#define GICD_IROUTER_SPI_MODE_ONE (0U << 31)
|
||||
#define GICD_IROUTER_SPI_MODE_ANY (1U << 31)
|
||||
|
||||
#define GIC_PIDR2_ARCH_MASK 0xf0
|
||||
#define GIC_PIDR2_ARCH_GICv3 0x30
|
||||
#define GIC_PIDR2_ARCH_GICv4 0x40
|
||||
|
||||
/*
|
||||
* Re-Distributor registers, offsets from RD_base
|
||||
*/
|
||||
#define GICR_CTLR GICD_CTLR
|
||||
#define GICR_IIDR 0x0004
|
||||
#define GICR_TYPER 0x0008
|
||||
#define GICR_STATUSR GICD_STATUSR
|
||||
#define GICR_WAKER 0x0014
|
||||
#define GICR_SETLPIR 0x0040
|
||||
#define GICR_CLRLPIR 0x0048
|
||||
#define GICR_SEIR GICD_SEIR
|
||||
#define GICR_PROPBASER 0x0070
|
||||
#define GICR_PENDBASER 0x0078
|
||||
#define GICR_INVLPIR 0x00A0
|
||||
#define GICR_INVALLR 0x00B0
|
||||
#define GICR_SYNCR 0x00C0
|
||||
#define GICR_MOVLPIR 0x0100
|
||||
#define GICR_MOVALLR 0x0110
|
||||
#define GICR_PIDR2 GICD_PIDR2
|
||||
|
||||
#define GICR_WAKER_ProcessorSleep (1U << 1)
|
||||
#define GICR_WAKER_ChildrenAsleep (1U << 2)
|
||||
|
||||
/*
|
||||
* Re-Distributor registers, offsets from SGI_base
|
||||
*/
|
||||
#define GICR_ISENABLER0 GICD_ISENABLER
|
||||
#define GICR_ICENABLER0 GICD_ICENABLER
|
||||
#define GICR_ISPENDR0 GICD_ISPENDR
|
||||
#define GICR_ICPENDR0 GICD_ICPENDR
|
||||
#define GICR_ISACTIVER0 GICD_ISACTIVER
|
||||
#define GICR_ICACTIVER0 GICD_ICACTIVER
|
||||
#define GICR_IPRIORITYR0 GICD_IPRIORITYR
|
||||
#define GICR_ICFGR0 GICD_ICFGR
|
||||
|
||||
#define GICR_TYPER_VLPIS (1U << 1)
|
||||
#define GICR_TYPER_LAST (1U << 4)
|
||||
|
||||
/*
|
||||
* CPU interface registers
|
||||
*/
|
||||
#define ICC_CTLR_EL1_EOImode_drop_dir (0U << 1)
|
||||
#define ICC_CTLR_EL1_EOImode_drop (1U << 1)
|
||||
#define ICC_SRE_EL1_SRE (1U << 0)
|
||||
|
||||
/*
|
||||
* Hypervisor interface registers (SRE only)
|
||||
*/
|
||||
#define ICH_LR_VIRTUAL_ID_MASK ((1UL << 32) - 1)
|
||||
|
||||
#define ICH_LR_EOI (1UL << 41)
|
||||
#define ICH_LR_GROUP (1UL << 60)
|
||||
#define ICH_LR_STATE (3UL << 62)
|
||||
#define ICH_LR_PENDING_BIT (1UL << 62)
|
||||
#define ICH_LR_ACTIVE_BIT (1UL << 63)
|
||||
|
||||
#define ICH_MISR_EOI (1 << 0)
|
||||
#define ICH_MISR_U (1 << 1)
|
||||
|
||||
#define ICH_HCR_EN (1 << 0)
|
||||
#define ICH_HCR_UIE (1 << 1)
|
||||
|
||||
#define ICH_VMCR_CTLR_SHIFT 0
|
||||
#define ICH_VMCR_CTLR_MASK (0x21f << ICH_VMCR_CTLR_SHIFT)
|
||||
#define ICH_VMCR_BPR1_SHIFT 18
|
||||
#define ICH_VMCR_BPR1_MASK (7 << ICH_VMCR_BPR1_SHIFT)
|
||||
#define ICH_VMCR_BPR0_SHIFT 21
|
||||
#define ICH_VMCR_BPR0_MASK (7 << ICH_VMCR_BPR0_SHIFT)
|
||||
#define ICH_VMCR_PMR_SHIFT 24
|
||||
#define ICH_VMCR_PMR_MASK (0xffUL << ICH_VMCR_PMR_SHIFT)
|
||||
|
||||
#define ICC_EOIR1_EL1 S3_0_C12_C12_1
|
||||
#define ICC_IAR1_EL1 S3_0_C12_C12_0
|
||||
#define ICC_SGI1R_EL1 S3_0_C12_C11_5
|
||||
#define ICC_PMR_EL1 S3_0_C4_C6_0
|
||||
#define ICC_CTLR_EL1 S3_0_C12_C12_4
|
||||
#define ICC_SRE_EL1 S3_0_C12_C12_5
|
||||
#define ICC_GRPEN1_EL1 S3_0_C12_C12_7
|
||||
|
||||
#define ICC_IAR1_EL1_SPURIOUS 0x3ff
|
||||
|
||||
#define ICC_SRE_EL2 S3_4_C12_C9_5
|
||||
|
||||
#define ICC_SRE_EL2_SRE (1 << 0)
|
||||
#define ICC_SRE_EL2_ENABLE (1 << 3)
|
||||
|
||||
/*
|
||||
* System register definitions
|
||||
*/
|
||||
#define ICH_VSEIR_EL2 S3_4_C12_C9_4
|
||||
#define ICH_HCR_EL2 S3_4_C12_C11_0
|
||||
#define ICH_VTR_EL2 S3_4_C12_C11_1
|
||||
#define ICH_MISR_EL2 S3_4_C12_C11_2
|
||||
#define ICH_EISR_EL2 S3_4_C12_C11_3
|
||||
#define ICH_ELSR_EL2 S3_4_C12_C11_5
|
||||
#define ICH_VMCR_EL2 S3_4_C12_C11_7
|
||||
|
||||
#define __LR0_EL2(x) S3_4_C12_C12_ ## x
|
||||
#define __LR8_EL2(x) S3_4_C12_C13_ ## x
|
||||
|
||||
#define ICH_LR0_EL2 __LR0_EL2(0)
|
||||
#define ICH_LR1_EL2 __LR0_EL2(1)
|
||||
#define ICH_LR2_EL2 __LR0_EL2(2)
|
||||
#define ICH_LR3_EL2 __LR0_EL2(3)
|
||||
#define ICH_LR4_EL2 __LR0_EL2(4)
|
||||
#define ICH_LR5_EL2 __LR0_EL2(5)
|
||||
#define ICH_LR6_EL2 __LR0_EL2(6)
|
||||
#define ICH_LR7_EL2 __LR0_EL2(7)
|
||||
#define ICH_LR8_EL2 __LR8_EL2(0)
|
||||
#define ICH_LR9_EL2 __LR8_EL2(1)
|
||||
#define ICH_LR10_EL2 __LR8_EL2(2)
|
||||
#define ICH_LR11_EL2 __LR8_EL2(3)
|
||||
#define ICH_LR12_EL2 __LR8_EL2(4)
|
||||
#define ICH_LR13_EL2 __LR8_EL2(5)
|
||||
#define ICH_LR14_EL2 __LR8_EL2(6)
|
||||
#define ICH_LR15_EL2 __LR8_EL2(7)
|
||||
|
||||
#define __AP0Rx_EL2(x) S3_4_C12_C8_ ## x
|
||||
#define ICH_AP0R0_EL2 __AP0Rx_EL2(0)
|
||||
#define ICH_AP0R1_EL2 __AP0Rx_EL2(1)
|
||||
#define ICH_AP0R2_EL2 __AP0Rx_EL2(2)
|
||||
#define ICH_AP0R3_EL2 __AP0Rx_EL2(3)
|
||||
|
||||
#define __AP1Rx_EL2(x) S3_4_C12_C9_ ## x
|
||||
#define ICH_AP1R0_EL2 __AP1Rx_EL2(0)
|
||||
#define ICH_AP1R1_EL2 __AP1Rx_EL2(1)
|
||||
#define ICH_AP1R2_EL2 __AP1Rx_EL2(2)
|
||||
#define ICH_AP1R3_EL2 __AP1Rx_EL2(3)
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#include <linux/stringify.h>
|
||||
|
||||
static inline void gic_write_eoir(u64 irq)
|
||||
{
|
||||
asm volatile("msr " __stringify(ICC_EOIR1_EL1) ", %0" : : "r" (irq));
|
||||
isb();
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -341,8 +341,8 @@ static struct lock_class_key irq_nested_lock_class;
|
|||
/*
|
||||
* irq_map_generic_chip - Map a generic chip for an irq domain
|
||||
*/
|
||||
static int irq_map_generic_chip(struct irq_domain *d, unsigned int virq,
|
||||
irq_hw_number_t hw_irq)
|
||||
int irq_map_generic_chip(struct irq_domain *d, unsigned int virq,
|
||||
irq_hw_number_t hw_irq)
|
||||
{
|
||||
struct irq_data *data = irq_get_irq_data(virq);
|
||||
struct irq_domain_chip_generic *dgc = d->gc;
|
||||
|
|
@ -394,6 +394,7 @@ static int irq_map_generic_chip(struct irq_domain *d, unsigned int virq,
|
|||
irq_modify_status(virq, dgc->irq_flags_to_clear, dgc->irq_flags_to_set);
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(irq_map_generic_chip);
|
||||
|
||||
struct irq_domain_ops irq_generic_chip_ops = {
|
||||
.map = irq_map_generic_chip,
|
||||
|
|
|
|||
Loading…
Reference in New Issue