microblaze: Make intc driver endian aware
Detect endianess directly on the hardware and use ioread/iowrite functions. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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cff2ee046e
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1aa1243c33
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@ -32,6 +32,29 @@ static void __iomem *intc_baseaddr;
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#define MER_ME (1<<0)
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#define MER_ME (1<<0)
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#define MER_HIE (1<<1)
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#define MER_HIE (1<<1)
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static unsigned int (*read_fn)(void __iomem *);
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static void (*write_fn)(u32, void __iomem *);
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static void intc_write32(u32 val, void __iomem *addr)
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{
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iowrite32(val, addr);
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}
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static unsigned int intc_read32(void __iomem *addr)
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{
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return ioread32(addr);
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}
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static void intc_write32_be(u32 val, void __iomem *addr)
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{
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iowrite32be(val, addr);
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}
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static unsigned int intc_read32_be(void __iomem *addr)
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{
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return ioread32be(addr);
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}
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static void intc_enable_or_unmask(struct irq_data *d)
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static void intc_enable_or_unmask(struct irq_data *d)
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{
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{
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unsigned long mask = 1 << d->hwirq;
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unsigned long mask = 1 << d->hwirq;
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@ -43,21 +66,21 @@ static void intc_enable_or_unmask(struct irq_data *d)
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* acks the irq before calling the interrupt handler
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* acks the irq before calling the interrupt handler
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*/
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*/
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if (irqd_is_level_type(d))
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if (irqd_is_level_type(d))
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out_be32(intc_baseaddr + IAR, mask);
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write_fn(mask, intc_baseaddr + IAR);
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out_be32(intc_baseaddr + SIE, mask);
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write_fn(mask, intc_baseaddr + SIE);
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}
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}
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static void intc_disable_or_mask(struct irq_data *d)
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static void intc_disable_or_mask(struct irq_data *d)
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{
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{
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pr_debug("disable: %ld\n", d->hwirq);
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pr_debug("disable: %ld\n", d->hwirq);
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out_be32(intc_baseaddr + CIE, 1 << d->hwirq);
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write_fn(1 << d->hwirq, intc_baseaddr + CIE);
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}
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}
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static void intc_ack(struct irq_data *d)
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static void intc_ack(struct irq_data *d)
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{
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{
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pr_debug("ack: %ld\n", d->hwirq);
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pr_debug("ack: %ld\n", d->hwirq);
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out_be32(intc_baseaddr + IAR, 1 << d->hwirq);
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write_fn(1 << d->hwirq, intc_baseaddr + IAR);
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}
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}
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static void intc_mask_ack(struct irq_data *d)
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static void intc_mask_ack(struct irq_data *d)
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@ -65,8 +88,8 @@ static void intc_mask_ack(struct irq_data *d)
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unsigned long mask = 1 << d->hwirq;
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unsigned long mask = 1 << d->hwirq;
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pr_debug("disable_and_ack: %ld\n", d->hwirq);
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pr_debug("disable_and_ack: %ld\n", d->hwirq);
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out_be32(intc_baseaddr + CIE, mask);
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write_fn(mask, intc_baseaddr + CIE);
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out_be32(intc_baseaddr + IAR, mask);
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write_fn(mask, intc_baseaddr + IAR);
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}
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}
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static struct irq_chip intc_dev = {
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static struct irq_chip intc_dev = {
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@ -83,7 +106,7 @@ unsigned int get_irq(void)
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{
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{
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unsigned int hwirq, irq = -1;
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unsigned int hwirq, irq = -1;
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hwirq = in_be32(intc_baseaddr + IVR);
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hwirq = read_fn(intc_baseaddr + IVR);
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if (hwirq != -1U)
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if (hwirq != -1U)
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irq = irq_find_mapping(root_domain, hwirq);
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irq = irq_find_mapping(root_domain, hwirq);
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@ -140,17 +163,25 @@ static int __init xilinx_intc_of_init(struct device_node *intc,
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pr_info("%s: num_irq=%d, edge=0x%x\n",
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pr_info("%s: num_irq=%d, edge=0x%x\n",
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intc->full_name, nr_irq, intr_mask);
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intc->full_name, nr_irq, intr_mask);
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write_fn = intc_write32;
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read_fn = intc_read32;
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/*
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/*
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* Disable all external interrupts until they are
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* Disable all external interrupts until they are
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* explicity requested.
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* explicity requested.
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*/
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*/
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out_be32(intc_baseaddr + IER, 0);
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write_fn(0, intc_baseaddr + IER);
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/* Acknowledge any pending interrupts just in case. */
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/* Acknowledge any pending interrupts just in case. */
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out_be32(intc_baseaddr + IAR, 0xffffffff);
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write_fn(0xffffffff, intc_baseaddr + IAR);
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/* Turn on the Master Enable. */
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/* Turn on the Master Enable. */
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out_be32(intc_baseaddr + MER, MER_HIE | MER_ME);
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write_fn(MER_HIE | MER_ME, intc_baseaddr + MER);
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if (!(read_fn(intc_baseaddr + MER) & (MER_HIE | MER_ME))) {
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write_fn = intc_write32_be;
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read_fn = intc_read32_be;
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write_fn(MER_HIE | MER_ME, intc_baseaddr + MER);
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}
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/* Yeah, okay, casting the intr_mask to a void* is butt-ugly, but I'm
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/* Yeah, okay, casting the intr_mask to a void* is butt-ugly, but I'm
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* lazy and Michal can clean it up to something nicer when he tests
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* lazy and Michal can clean it up to something nicer when he tests
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