[ARM] 3142/1: OMAP 2/5: Update files common to omap1 and omap2
Patch from Tony Lindgren This patch syncs the mainline kernel with linux-omap tree. The highlights of the patch are: - Serial port and framebuffer init improvments by Imre Deak - Common omap pin mux framework by Tony Lindgren - Common omap clock framework by Tony Lindren Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Tony Lindgren
Russell King
parent
3179a01939
commit
1a8bfa1eb9
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@ -3,7 +3,7 @@
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#
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# Common support
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obj-y := common.o sram.o sram-fn.o clock.o dma.o mux.o gpio.o mcbsp.o usb.o
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obj-y := common.o sram.o sram-fn.o clock.o devices.o dma.o mux.o gpio.o mcbsp.o usb.o
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obj-m :=
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obj-n :=
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obj- :=
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File diff suppressed because it is too large
Load Diff
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@ -1,120 +0,0 @@
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/*
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* linux/arch/arm/plat-omap/clock.h
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*
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* Copyright (C) 2004 Nokia corporation
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* Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
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* Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ARCH_ARM_OMAP_CLOCK_H
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#define __ARCH_ARM_OMAP_CLOCK_H
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struct module;
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struct clk {
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struct list_head node;
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struct module *owner;
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const char *name;
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struct clk *parent;
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unsigned long rate;
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__s8 usecount;
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__u16 flags;
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__u32 enable_reg;
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__u8 enable_bit;
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__u8 rate_offset;
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void (*recalc)(struct clk *);
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int (*set_rate)(struct clk *, unsigned long);
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long (*round_rate)(struct clk *, unsigned long);
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void (*init)(struct clk *);
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};
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struct mpu_rate {
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unsigned long rate;
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unsigned long xtal;
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unsigned long pll_rate;
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__u16 ckctl_val;
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__u16 dpllctl_val;
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};
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/* Clock flags */
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#define RATE_CKCTL 1
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#define RATE_FIXED 2
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#define RATE_PROPAGATES 4
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#define VIRTUAL_CLOCK 8
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#define ALWAYS_ENABLED 16
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#define ENABLE_REG_32BIT 32
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#define CLOCK_IN_OMAP16XX 64
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#define CLOCK_IN_OMAP1510 128
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#define CLOCK_IN_OMAP730 256
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#define DSP_DOMAIN_CLOCK 512
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#define VIRTUAL_IO_ADDRESS 1024
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/* ARM_CKCTL bit shifts */
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#define CKCTL_PERDIV_OFFSET 0
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#define CKCTL_LCDDIV_OFFSET 2
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#define CKCTL_ARMDIV_OFFSET 4
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#define CKCTL_DSPDIV_OFFSET 6
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#define CKCTL_TCDIV_OFFSET 8
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#define CKCTL_DSPMMUDIV_OFFSET 10
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/*#define ARM_TIMXO 12*/
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#define EN_DSPCK 13
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/*#define ARM_INTHCK_SEL 14*/ /* Divide-by-2 for mpu inth_ck */
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/* DSP_CKCTL bit shifts */
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#define CKCTL_DSPPERDIV_OFFSET 0
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/* ARM_IDLECT1 bit shifts */
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/*#define IDLWDT_ARM 0*/
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/*#define IDLXORP_ARM 1*/
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/*#define IDLPER_ARM 2*/
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/*#define IDLLCD_ARM 3*/
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/*#define IDLLB_ARM 4*/
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/*#define IDLHSAB_ARM 5*/
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/*#define IDLIF_ARM 6*/
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/*#define IDLDPLL_ARM 7*/
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/*#define IDLAPI_ARM 8*/
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/*#define IDLTIM_ARM 9*/
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/*#define SETARM_IDLE 11*/
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/* ARM_IDLECT2 bit shifts */
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#define EN_WDTCK 0
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#define EN_XORPCK 1
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#define EN_PERCK 2
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#define EN_LCDCK 3
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#define EN_LBCK 4 /* Not on 1610/1710 */
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/*#define EN_HSABCK 5*/
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#define EN_APICK 6
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#define EN_TIMCK 7
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#define DMACK_REQ 8
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#define EN_GPIOCK 9 /* Not on 1610/1710 */
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/*#define EN_LBFREECK 10*/
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#define EN_CKOUT_ARM 11
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/* ARM_IDLECT3 bit shifts */
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#define EN_OCPI_CK 0
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#define EN_TC1_CK 2
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#define EN_TC2_CK 4
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/* DSP_IDLECT2 bit shifts (0,1,2 are same as for ARM_IDLECT2) */
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#define EN_DSPTIMCK 5
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/* Various register defines for clock controls scattered around OMAP chip */
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#define USB_MCLK_EN_BIT 4 /* In ULPD_CLKC_CTRL */
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#define USB_HOST_HHC_UHOST_EN 9 /* In MOD_CONF_CTRL_0 */
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#define SWD_ULPD_PLL_CLK_REQ 1 /* In SWD_CLK_DIV_CTRL_SEL */
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#define COM_ULPD_PLL_CLK_REQ 1 /* In COM_CLK_DIV_CTRL_SEL */
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#define SWD_CLK_DIV_CTRL_SEL 0xfffe0874
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#define COM_CLK_DIV_CTRL_SEL 0xfffe0878
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#define SOFT_REQ_REG 0xfffe0834
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#define SOFT_REQ_REG2 0xfffe0880
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int clk_register(struct clk *clk);
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void clk_unregister(struct clk *clk);
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int clk_init(void);
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#endif
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@ -31,7 +31,7 @@
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#include <asm/arch/mux.h>
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#include <asm/arch/fpga.h>
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#include "clock.h"
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#include <asm/arch/clock.h>
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#define NO_LENGTH_CHECK 0xffffffff
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@ -117,19 +117,43 @@ EXPORT_SYMBOL(omap_get_var_config);
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static int __init omap_add_serial_console(void)
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{
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const struct omap_serial_console_config *info;
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const struct omap_serial_console_config *con_info;
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const struct omap_uart_config *uart_info;
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static char speed[11], *opt = NULL;
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int line, i, uart_idx;
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info = omap_get_config(OMAP_TAG_SERIAL_CONSOLE,
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struct omap_serial_console_config);
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if (info != NULL && info->console_uart) {
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static char speed[11], *opt = NULL;
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uart_info = omap_get_config(OMAP_TAG_UART, struct omap_uart_config);
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con_info = omap_get_config(OMAP_TAG_SERIAL_CONSOLE,
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struct omap_serial_console_config);
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if (uart_info == NULL || con_info == NULL)
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return 0;
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if (info->console_speed) {
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snprintf(speed, sizeof(speed), "%u", info->console_speed);
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opt = speed;
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}
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return add_preferred_console("ttyS", info->console_uart - 1, opt);
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if (con_info->console_uart == 0)
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return 0;
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if (con_info->console_speed) {
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snprintf(speed, sizeof(speed), "%u", con_info->console_speed);
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opt = speed;
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}
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return 0;
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uart_idx = con_info->console_uart - 1;
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if (uart_idx >= OMAP_MAX_NR_PORTS) {
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printk(KERN_INFO "Console: external UART#%d. "
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"Not adding it as console this time.\n",
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uart_idx + 1);
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return 0;
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}
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if (!(uart_info->enabled_uarts & (1 << uart_idx))) {
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printk(KERN_ERR "Console: Selected UART#%d is "
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"not enabled for this platform\n",
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uart_idx + 1);
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return -1;
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}
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line = 0;
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for (i = 0; i < uart_idx; i++) {
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if (uart_info->enabled_uarts & (1 << i))
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line++;
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}
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return add_preferred_console("ttyS", line, opt);
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}
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console_initcall(omap_add_serial_console);
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@ -0,0 +1,381 @@
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/*
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* linux/arch/arm/plat-omap/devices.c
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*
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* Common platform device setup/initialization for OMAP1 and OMAP2
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include <linux/config.h>
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <asm/hardware.h>
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#include <asm/io.h>
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#include <asm/mach-types.h>
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#include <asm/mach/map.h>
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#include <asm/arch/tc.h>
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#include <asm/arch/board.h>
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#include <asm/arch/mux.h>
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#include <asm/arch/gpio.h>
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void omap_nop_release(struct device *dev)
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{
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/* Nothing */
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}
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/*-------------------------------------------------------------------------*/
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#if defined(CONFIG_I2C_OMAP) || defined(CONFIG_I2C_OMAP_MODULE)
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#define OMAP1_I2C_BASE 0xfffb3800
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#define OMAP2_I2C_BASE1 0x48070000
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#define OMAP_I2C_SIZE 0x3f
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#define OMAP1_I2C_INT INT_I2C
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#define OMAP2_I2C_INT1 56
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static struct resource i2c_resources1[] = {
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{
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.start = 0,
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.end = 0,
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.flags = IORESOURCE_MEM,
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},
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{
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.start = 0,
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.flags = IORESOURCE_IRQ,
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},
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};
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/* DMA not used; works around erratum writing to non-empty i2c fifo */
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static struct platform_device omap_i2c_device1 = {
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.name = "i2c_omap",
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.id = 1,
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.dev = {
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.release = omap_nop_release,
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},
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.num_resources = ARRAY_SIZE(i2c_resources1),
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.resource = i2c_resources1,
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};
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/* See also arch/arm/mach-omap2/devices.c for second I2C on 24xx */
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static void omap_init_i2c(void)
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{
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if (cpu_is_omap24xx()) {
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i2c_resources1[0].start = OMAP2_I2C_BASE1;
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i2c_resources1[0].end = OMAP2_I2C_BASE1 + OMAP_I2C_SIZE;
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i2c_resources1[1].start = OMAP2_I2C_INT1;
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} else {
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i2c_resources1[0].start = OMAP1_I2C_BASE;
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i2c_resources1[0].end = OMAP1_I2C_BASE + OMAP_I2C_SIZE;
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i2c_resources1[1].start = OMAP1_I2C_INT;
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}
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/* FIXME define and use a boot tag, in case of boards that
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* either don't wire up I2C, or chips that mux it differently...
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* it can include clocking and address info, maybe more.
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*/
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if (cpu_is_omap24xx()) {
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omap_cfg_reg(M19_24XX_I2C1_SCL);
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omap_cfg_reg(L15_24XX_I2C1_SDA);
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} else {
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omap_cfg_reg(I2C_SCL);
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omap_cfg_reg(I2C_SDA);
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}
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(void) platform_device_register(&omap_i2c_device1);
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}
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#else
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static inline void omap_init_i2c(void) {}
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#endif
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/*-------------------------------------------------------------------------*/
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#if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE)
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#ifdef CONFIG_ARCH_OMAP24XX
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#define OMAP_MMC1_BASE 0x4809c000
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#define OMAP_MMC1_INT 83
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#else
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#define OMAP_MMC1_BASE 0xfffb7800
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#define OMAP_MMC1_INT INT_MMC
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#endif
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#define OMAP_MMC2_BASE 0xfffb7c00 /* omap16xx only */
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static struct omap_mmc_conf mmc1_conf;
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static u64 mmc1_dmamask = 0xffffffff;
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static struct resource mmc1_resources[] = {
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{
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.start = IO_ADDRESS(OMAP_MMC1_BASE),
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.end = IO_ADDRESS(OMAP_MMC1_BASE) + 0x7f,
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.flags = IORESOURCE_MEM,
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},
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{
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.start = OMAP_MMC1_INT,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device mmc_omap_device1 = {
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.name = "mmci-omap",
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.id = 1,
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.dev = {
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.release = omap_nop_release,
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.dma_mask = &mmc1_dmamask,
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.platform_data = &mmc1_conf,
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},
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.num_resources = ARRAY_SIZE(mmc1_resources),
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.resource = mmc1_resources,
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};
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#ifdef CONFIG_ARCH_OMAP16XX
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static struct omap_mmc_conf mmc2_conf;
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static u64 mmc2_dmamask = 0xffffffff;
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static struct resource mmc2_resources[] = {
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{
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.start = IO_ADDRESS(OMAP_MMC2_BASE),
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.end = IO_ADDRESS(OMAP_MMC2_BASE) + 0x7f,
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.flags = IORESOURCE_MEM,
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},
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{
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.start = INT_1610_MMC2,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device mmc_omap_device2 = {
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.name = "mmci-omap",
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.id = 2,
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.dev = {
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.release = omap_nop_release,
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.dma_mask = &mmc2_dmamask,
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.platform_data = &mmc2_conf,
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},
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.num_resources = ARRAY_SIZE(mmc2_resources),
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.resource = mmc2_resources,
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};
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#endif
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static void __init omap_init_mmc(void)
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{
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const struct omap_mmc_config *mmc_conf;
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const struct omap_mmc_conf *mmc;
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/* NOTE: assumes MMC was never (wrongly) enabled */
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mmc_conf = omap_get_config(OMAP_TAG_MMC, struct omap_mmc_config);
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if (!mmc_conf)
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return;
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/* block 1 is always available and has just one pinout option */
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mmc = &mmc_conf->mmc[0];
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if (mmc->enabled) {
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if (!cpu_is_omap24xx()) {
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omap_cfg_reg(MMC_CMD);
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omap_cfg_reg(MMC_CLK);
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omap_cfg_reg(MMC_DAT0);
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if (cpu_is_omap1710()) {
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omap_cfg_reg(M15_1710_MMC_CLKI);
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omap_cfg_reg(P19_1710_MMC_CMDDIR);
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omap_cfg_reg(P20_1710_MMC_DATDIR0);
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}
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}
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if (mmc->wire4) {
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if (!cpu_is_omap24xx()) {
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omap_cfg_reg(MMC_DAT1);
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/* NOTE: DAT2 can be on W10 (here) or M15 */
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if (!mmc->nomux)
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omap_cfg_reg(MMC_DAT2);
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omap_cfg_reg(MMC_DAT3);
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}
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}
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mmc1_conf = *mmc;
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(void) platform_device_register(&mmc_omap_device1);
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}
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#ifdef CONFIG_ARCH_OMAP16XX
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/* block 2 is on newer chips, and has many pinout options */
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mmc = &mmc_conf->mmc[1];
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if (mmc->enabled) {
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if (!mmc->nomux) {
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omap_cfg_reg(Y8_1610_MMC2_CMD);
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omap_cfg_reg(Y10_1610_MMC2_CLK);
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omap_cfg_reg(R18_1610_MMC2_CLKIN);
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omap_cfg_reg(W8_1610_MMC2_DAT0);
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if (mmc->wire4) {
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omap_cfg_reg(V8_1610_MMC2_DAT1);
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omap_cfg_reg(W15_1610_MMC2_DAT2);
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omap_cfg_reg(R10_1610_MMC2_DAT3);
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}
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/* These are needed for the level shifter */
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omap_cfg_reg(V9_1610_MMC2_CMDDIR);
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omap_cfg_reg(V5_1610_MMC2_DATDIR0);
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omap_cfg_reg(W19_1610_MMC2_DATDIR1);
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}
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/* Feedback clock must be set on OMAP-1710 MMC2 */
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if (cpu_is_omap1710())
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omap_writel(omap_readl(MOD_CONF_CTRL_1) | (1 << 24),
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MOD_CONF_CTRL_1);
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mmc2_conf = *mmc;
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(void) platform_device_register(&mmc_omap_device2);
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}
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#endif
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return;
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}
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#else
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static inline void omap_init_mmc(void) {}
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#endif
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#if defined(CONFIG_OMAP_WATCHDOG) || defined(CONFIG_OMAP_WATCHDOG_MODULE)
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#ifdef CONFIG_ARCH_OMAP24XX
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#define OMAP_WDT_BASE 0x48022000
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#else
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#define OMAP_WDT_BASE 0xfffeb000
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#endif
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static struct resource wdt_resources[] = {
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{
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.start = OMAP_WDT_BASE,
|
||||
.end = OMAP_WDT_BASE + 0x4f,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device omap_wdt_device = {
|
||||
.name = "omap_wdt",
|
||||
.id = -1,
|
||||
.dev = {
|
||||
.release = omap_nop_release,
|
||||
},
|
||||
.num_resources = ARRAY_SIZE(wdt_resources),
|
||||
.resource = wdt_resources,
|
||||
};
|
||||
|
||||
static void omap_init_wdt(void)
|
||||
{
|
||||
(void) platform_device_register(&omap_wdt_device);
|
||||
}
|
||||
#else
|
||||
static inline void omap_init_wdt(void) {}
|
||||
#endif
|
||||
|
||||
/*-------------------------------------------------------------------------*/
|
||||
|
||||
#if defined(CONFIG_OMAP_RNG) || defined(CONFIG_OMAP_RNG_MODULE)
|
||||
|
||||
#ifdef CONFIG_ARCH_OMAP24XX
|
||||
#define OMAP_RNG_BASE 0x480A0000
|
||||
#else
|
||||
#define OMAP_RNG_BASE 0xfffe5000
|
||||
#endif
|
||||
|
||||
static struct resource rng_resources[] = {
|
||||
{
|
||||
.start = OMAP_RNG_BASE,
|
||||
.end = OMAP_RNG_BASE + 0x4f,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device omap_rng_device = {
|
||||
.name = "omap_rng",
|
||||
.id = -1,
|
||||
.dev = {
|
||||
.release = omap_nop_release,
|
||||
},
|
||||
.num_resources = ARRAY_SIZE(rng_resources),
|
||||
.resource = rng_resources,
|
||||
};
|
||||
|
||||
static void omap_init_rng(void)
|
||||
{
|
||||
(void) platform_device_register(&omap_rng_device);
|
||||
}
|
||||
#else
|
||||
static inline void omap_init_rng(void) {}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_FB_OMAP) || defined(CONFIG_FB_OMAP_MODULE)
|
||||
|
||||
static struct omap_lcd_config omap_fb_conf;
|
||||
|
||||
static u64 omap_fb_dma_mask = ~(u32)0;
|
||||
|
||||
static struct platform_device omap_fb_device = {
|
||||
.name = "omapfb",
|
||||
.id = -1,
|
||||
.dev = {
|
||||
.release = omap_nop_release,
|
||||
.dma_mask = &omap_fb_dma_mask,
|
||||
.coherent_dma_mask = ~(u32)0,
|
||||
.platform_data = &omap_fb_conf,
|
||||
},
|
||||
.num_resources = 0,
|
||||
};
|
||||
|
||||
static inline void omap_init_fb(void)
|
||||
{
|
||||
const struct omap_lcd_config *conf;
|
||||
|
||||
conf = omap_get_config(OMAP_TAG_LCD, struct omap_lcd_config);
|
||||
if (conf != NULL)
|
||||
omap_fb_conf = *conf;
|
||||
platform_device_register(&omap_fb_device);
|
||||
}
|
||||
|
||||
#else
|
||||
|
||||
static inline void omap_init_fb(void) {}
|
||||
|
||||
#endif
|
||||
|
||||
/*
|
||||
* This gets called after board-specific INIT_MACHINE, and initializes most
|
||||
* on-chip peripherals accessible on this board (except for few like USB):
|
||||
*
|
||||
* (a) Does any "standard config" pin muxing needed. Board-specific
|
||||
* code will have muxed GPIO pins and done "nonstandard" setup;
|
||||
* that code could live in the boot loader.
|
||||
* (b) Populating board-specific platform_data with the data drivers
|
||||
* rely on to handle wiring variations.
|
||||
* (c) Creating platform devices as meaningful on this board and
|
||||
* with this kernel configuration.
|
||||
*
|
||||
* Claiming GPIOs, and setting their direction and initial values, is the
|
||||
* responsibility of the device drivers. So is responding to probe().
|
||||
*
|
||||
* Board-specific knowlege like creating devices or pin setup is to be
|
||||
* kept out of drivers as much as possible. In particular, pin setup
|
||||
* may be handled by the boot loader, and drivers should expect it will
|
||||
* normally have been done by the time they're probed.
|
||||
*/
|
||||
static int __init omap_init_devices(void)
|
||||
{
|
||||
/* please keep these calls, and their implementations above,
|
||||
* in alphabetical order so they're easier to sort through.
|
||||
*/
|
||||
omap_init_fb();
|
||||
omap_init_i2c();
|
||||
omap_init_mmc();
|
||||
omap_init_wdt();
|
||||
omap_init_rng();
|
||||
|
||||
return 0;
|
||||
}
|
||||
arch_initcall(omap_init_devices);
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -140,7 +140,7 @@ static struct gpio_bank gpio_bank_1610[5] = {
|
|||
};
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARCH_OMAP1510
|
||||
#ifdef CONFIG_ARCH_OMAP15XX
|
||||
static struct gpio_bank gpio_bank_1510[2] = {
|
||||
{ OMAP_MPUIO_BASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
|
||||
{ OMAP1510_GPIO_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1510 }
|
||||
|
|
@ -173,7 +173,7 @@ static int gpio_bank_count;
|
|||
|
||||
static inline struct gpio_bank *get_gpio_bank(int gpio)
|
||||
{
|
||||
#ifdef CONFIG_ARCH_OMAP1510
|
||||
#ifdef CONFIG_ARCH_OMAP15XX
|
||||
if (cpu_is_omap1510()) {
|
||||
if (OMAP_GPIO_IS_MPUIO(gpio))
|
||||
return &gpio_bank[0];
|
||||
|
|
@ -222,7 +222,7 @@ static inline int gpio_valid(int gpio)
|
|||
return -1;
|
||||
return 0;
|
||||
}
|
||||
#ifdef CONFIG_ARCH_OMAP1510
|
||||
#ifdef CONFIG_ARCH_OMAP15XX
|
||||
if (cpu_is_omap1510() && gpio < 16)
|
||||
return 0;
|
||||
#endif
|
||||
|
|
@ -654,7 +654,7 @@ int omap_request_gpio(int gpio)
|
|||
/* Set trigger to none. You need to enable the trigger after request_irq */
|
||||
_set_gpio_triggering(bank, get_gpio_index(gpio), IRQT_NOEDGE);
|
||||
|
||||
#ifdef CONFIG_ARCH_OMAP1510
|
||||
#ifdef CONFIG_ARCH_OMAP15XX
|
||||
if (bank->method == METHOD_GPIO_1510) {
|
||||
void __iomem *reg;
|
||||
|
||||
|
|
@ -739,7 +739,7 @@ static void gpio_irq_handler(unsigned int irq, struct irqdesc *desc,
|
|||
bank = (struct gpio_bank *) desc->data;
|
||||
if (bank->method == METHOD_MPUIO)
|
||||
isr_reg = bank->base + OMAP_MPUIO_GPIO_INT;
|
||||
#ifdef CONFIG_ARCH_OMAP1510
|
||||
#ifdef CONFIG_ARCH_OMAP15XX
|
||||
if (bank->method == METHOD_GPIO_1510)
|
||||
isr_reg = bank->base + OMAP1510_GPIO_INT_STATUS;
|
||||
#endif
|
||||
|
|
@ -774,7 +774,7 @@ static void gpio_irq_handler(unsigned int irq, struct irqdesc *desc,
|
|||
d = irq_desc + gpio_irq;
|
||||
desc_handle_irq(gpio_irq, d, regs);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static void gpio_ack_irq(unsigned int irq)
|
||||
|
|
@ -837,8 +837,9 @@ static struct irqchip mpuio_irq_chip = {
|
|||
.unmask = mpuio_unmask_irq
|
||||
};
|
||||
|
||||
static int initialized = 0;
|
||||
static struct clk * gpio_ck = NULL;
|
||||
static int initialized;
|
||||
static struct clk * gpio_ick;
|
||||
static struct clk * gpio_fck;
|
||||
|
||||
static int __init _omap_gpio_init(void)
|
||||
{
|
||||
|
|
@ -848,14 +849,26 @@ static int __init _omap_gpio_init(void)
|
|||
initialized = 1;
|
||||
|
||||
if (cpu_is_omap1510()) {
|
||||
gpio_ck = clk_get(NULL, "arm_gpio_ck");
|
||||
if (IS_ERR(gpio_ck))
|
||||
gpio_ick = clk_get(NULL, "arm_gpio_ck");
|
||||
if (IS_ERR(gpio_ick))
|
||||
printk("Could not get arm_gpio_ck\n");
|
||||
else
|
||||
clk_use(gpio_ck);
|
||||
clk_use(gpio_ick);
|
||||
}
|
||||
if (cpu_is_omap24xx()) {
|
||||
gpio_ick = clk_get(NULL, "gpios_ick");
|
||||
if (IS_ERR(gpio_ick))
|
||||
printk("Could not get gpios_ick\n");
|
||||
else
|
||||
clk_use(gpio_ick);
|
||||
gpio_fck = clk_get(NULL, "gpios_fck");
|
||||
if (IS_ERR(gpio_ick))
|
||||
printk("Could not get gpios_fck\n");
|
||||
else
|
||||
clk_use(gpio_fck);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_ARCH_OMAP1510
|
||||
#ifdef CONFIG_ARCH_OMAP15XX
|
||||
if (cpu_is_omap1510()) {
|
||||
printk(KERN_INFO "OMAP1510 GPIO hardware\n");
|
||||
gpio_bank_count = 2;
|
||||
|
|
@ -901,7 +914,7 @@ static int __init _omap_gpio_init(void)
|
|||
if (bank->method == METHOD_MPUIO) {
|
||||
omap_writew(0xFFFF, OMAP_MPUIO_BASE + OMAP_MPUIO_GPIO_MASKIT);
|
||||
}
|
||||
#ifdef CONFIG_ARCH_OMAP1510
|
||||
#ifdef CONFIG_ARCH_OMAP15XX
|
||||
if (bank->method == METHOD_GPIO_1510) {
|
||||
__raw_writew(0xffff, bank->base + OMAP1510_GPIO_INT_MASK);
|
||||
__raw_writew(0x0000, bank->base + OMAP1510_GPIO_INT_STATUS);
|
||||
|
|
@ -1038,6 +1051,7 @@ static struct sys_device omap_gpio_device = {
|
|||
|
||||
/*
|
||||
* This may get called early from board specific init
|
||||
* for boards that have interrupts routed via FPGA.
|
||||
*/
|
||||
int omap_gpio_init(void)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -491,17 +491,20 @@ int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer, unsigned int leng
|
|||
omap_set_dma_transfer_params(mcbsp[id].dma_tx_lch,
|
||||
OMAP_DMA_DATA_TYPE_S16,
|
||||
length >> 1, 1,
|
||||
OMAP_DMA_SYNC_ELEMENT);
|
||||
OMAP_DMA_SYNC_ELEMENT,
|
||||
0, 0);
|
||||
|
||||
omap_set_dma_dest_params(mcbsp[id].dma_tx_lch,
|
||||
OMAP_DMA_PORT_TIPB,
|
||||
OMAP_DMA_AMODE_CONSTANT,
|
||||
mcbsp[id].io_base + OMAP_MCBSP_REG_DXR1);
|
||||
mcbsp[id].io_base + OMAP_MCBSP_REG_DXR1,
|
||||
0, 0);
|
||||
|
||||
omap_set_dma_src_params(mcbsp[id].dma_tx_lch,
|
||||
OMAP_DMA_PORT_EMIFF,
|
||||
OMAP_DMA_AMODE_POST_INC,
|
||||
buffer);
|
||||
buffer,
|
||||
0, 0);
|
||||
|
||||
omap_start_dma(mcbsp[id].dma_tx_lch);
|
||||
wait_for_completion(&(mcbsp[id].tx_dma_completion));
|
||||
|
|
@ -531,17 +534,20 @@ int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer, unsigned int leng
|
|||
omap_set_dma_transfer_params(mcbsp[id].dma_rx_lch,
|
||||
OMAP_DMA_DATA_TYPE_S16,
|
||||
length >> 1, 1,
|
||||
OMAP_DMA_SYNC_ELEMENT);
|
||||
OMAP_DMA_SYNC_ELEMENT,
|
||||
0, 0);
|
||||
|
||||
omap_set_dma_src_params(mcbsp[id].dma_rx_lch,
|
||||
OMAP_DMA_PORT_TIPB,
|
||||
OMAP_DMA_AMODE_CONSTANT,
|
||||
mcbsp[id].io_base + OMAP_MCBSP_REG_DRR1);
|
||||
mcbsp[id].io_base + OMAP_MCBSP_REG_DRR1,
|
||||
0, 0);
|
||||
|
||||
omap_set_dma_dest_params(mcbsp[id].dma_rx_lch,
|
||||
OMAP_DMA_PORT_EMIFF,
|
||||
OMAP_DMA_AMODE_POST_INC,
|
||||
buffer);
|
||||
buffer,
|
||||
0, 0);
|
||||
|
||||
omap_start_dma(mcbsp[id].dma_rx_lch);
|
||||
wait_for_completion(&(mcbsp[id].rx_dma_completion));
|
||||
|
|
@ -643,7 +649,7 @@ static const struct omap_mcbsp_info mcbsp_730[] = {
|
|||
};
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARCH_OMAP1510
|
||||
#ifdef CONFIG_ARCH_OMAP15XX
|
||||
static const struct omap_mcbsp_info mcbsp_1510[] = {
|
||||
[0] = { .virt_base = OMAP1510_MCBSP1_BASE,
|
||||
.dma_rx_sync = OMAP_DMA_MCBSP1_RX,
|
||||
|
|
@ -712,7 +718,7 @@ static int __init omap_mcbsp_init(void)
|
|||
mcbsp_count = ARRAY_SIZE(mcbsp_730);
|
||||
}
|
||||
#endif
|
||||
#ifdef CONFIG_ARCH_OMAP1510
|
||||
#ifdef CONFIG_ARCH_OMAP15XX
|
||||
if (cpu_is_omap1510()) {
|
||||
mcbsp_info = mcbsp_1510;
|
||||
mcbsp_count = ARRAY_SIZE(mcbsp_1510);
|
||||
|
|
|
|||
|
|
@ -3,7 +3,7 @@
|
|||
*
|
||||
* Utility to set the Omap MUX and PULL_DWN registers from a table in mux.h
|
||||
*
|
||||
* Copyright (C) 2003 Nokia Corporation
|
||||
* Copyright (C) 2003 - 2005 Nokia Corporation
|
||||
*
|
||||
* Written by Tony Lindgren <tony.lindgren@nokia.com>
|
||||
*
|
||||
|
|
@ -25,38 +25,74 @@
|
|||
#include <linux/config.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <asm/system.h>
|
||||
#include <asm/io.h>
|
||||
#include <linux/spinlock.h>
|
||||
|
||||
#define __MUX_C__
|
||||
#include <asm/arch/mux.h>
|
||||
|
||||
#ifdef CONFIG_OMAP_MUX
|
||||
|
||||
#define OMAP24XX_L4_BASE 0x48000000
|
||||
#define OMAP24XX_PULL_ENA (1 << 3)
|
||||
#define OMAP24XX_PULL_UP (1 << 4)
|
||||
|
||||
static struct pin_config * pin_table;
|
||||
static unsigned long pin_table_sz;
|
||||
|
||||
extern struct pin_config * omap730_pins;
|
||||
extern struct pin_config * omap1xxx_pins;
|
||||
extern struct pin_config * omap24xx_pins;
|
||||
|
||||
int __init omap_mux_register(struct pin_config * pins, unsigned long size)
|
||||
{
|
||||
pin_table = pins;
|
||||
pin_table_sz = size;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Sets the Omap MUX and PULL_DWN registers based on the table
|
||||
*/
|
||||
int __init_or_module
|
||||
omap_cfg_reg(const reg_cfg_t reg_cfg)
|
||||
int __init_or_module omap_cfg_reg(const unsigned long index)
|
||||
{
|
||||
static DEFINE_SPINLOCK(mux_spin_lock);
|
||||
|
||||
unsigned long flags;
|
||||
reg_cfg_set *cfg;
|
||||
struct pin_config *cfg;
|
||||
unsigned int reg_orig = 0, reg = 0, pu_pd_orig = 0, pu_pd = 0,
|
||||
pull_orig = 0, pull = 0;
|
||||
unsigned int mask, warn = 0;
|
||||
|
||||
if (cpu_is_omap7xx())
|
||||
return 0;
|
||||
if (!pin_table)
|
||||
BUG();
|
||||
|
||||
if (reg_cfg > ARRAY_SIZE(reg_cfg_table)) {
|
||||
printk(KERN_ERR "MUX: reg_cfg %d\n", reg_cfg);
|
||||
return -EINVAL;
|
||||
if (index >= pin_table_sz) {
|
||||
printk(KERN_ERR "Invalid pin mux index: %lu (%lu)\n",
|
||||
index, pin_table_sz);
|
||||
dump_stack();
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
cfg = (reg_cfg_set *)®_cfg_table[reg_cfg];
|
||||
cfg = (struct pin_config *)&pin_table[index];
|
||||
if (cpu_is_omap24xx()) {
|
||||
u8 reg = 0;
|
||||
|
||||
reg |= cfg->mask & 0x7;
|
||||
if (cfg->pull_val)
|
||||
reg |= OMAP24XX_PULL_ENA;
|
||||
if(cfg->pu_pd_val)
|
||||
reg |= OMAP24XX_PULL_UP;
|
||||
#ifdef CONFIG_OMAP_MUX_DEBUG
|
||||
printk("Muxing %s (0x%08x): 0x%02x -> 0x%02x\n",
|
||||
cfg->name, OMAP24XX_L4_BASE + cfg->mux_reg,
|
||||
omap_readb(OMAP24XX_L4_BASE + cfg->mux_reg), reg);
|
||||
#endif
|
||||
omap_writeb(reg, OMAP24XX_L4_BASE + cfg->mux_reg);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Check the mux register in question */
|
||||
if (cfg->mux_reg) {
|
||||
|
|
@ -157,7 +193,8 @@ omap_cfg_reg(const reg_cfg_t reg_cfg)
|
|||
return 0;
|
||||
#endif
|
||||
}
|
||||
|
||||
EXPORT_SYMBOL(omap_cfg_reg);
|
||||
|
||||
#else
|
||||
#define omap_mux_init() do {} while(0)
|
||||
#define omap_cfg_reg(x) do {} while(0)
|
||||
#endif /* CONFIG_OMAP_MUX */
|
||||
|
|
|
|||
|
|
@ -54,11 +54,12 @@
|
|||
#include <asm/arch/tps65010.h>
|
||||
#include <asm/arch/dsp_common.h>
|
||||
|
||||
#include "clock.h"
|
||||
#include "sram.h"
|
||||
#include <asm/arch/clock.h>
|
||||
#include <asm/arch/sram.h>
|
||||
|
||||
static unsigned int arm_sleep_save[ARM_SLEEP_SAVE_SIZE];
|
||||
static unsigned short ulpd_sleep_save[ULPD_SLEEP_SAVE_SIZE];
|
||||
static unsigned int mpui730_sleep_save[MPUI730_SLEEP_SAVE_SIZE];
|
||||
static unsigned int mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_SIZE];
|
||||
static unsigned int mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_SIZE];
|
||||
|
||||
|
|
@ -120,8 +121,8 @@ void omap_pm_idle(void)
|
|||
*/
|
||||
static void omap_pm_wakeup_setup(void)
|
||||
{
|
||||
u32 level1_wake = OMAP_IRQ_BIT(INT_IH2_IRQ);
|
||||
u32 level2_wake = OMAP_IRQ_BIT(INT_UART2) | OMAP_IRQ_BIT(INT_KEYBOARD);
|
||||
u32 level1_wake = 0;
|
||||
u32 level2_wake = OMAP_IRQ_BIT(INT_UART2);
|
||||
|
||||
/*
|
||||
* Turn off all interrupts except GPIO bank 1, L1-2nd level cascade,
|
||||
|
|
@ -129,19 +130,29 @@ static void omap_pm_wakeup_setup(void)
|
|||
* drivers must still separately call omap_set_gpio_wakeup() to
|
||||
* wake up to a GPIO interrupt.
|
||||
*/
|
||||
if (cpu_is_omap1510() || cpu_is_omap16xx())
|
||||
level1_wake |= OMAP_IRQ_BIT(INT_GPIO_BANK1);
|
||||
else if (cpu_is_omap730())
|
||||
level1_wake |= OMAP_IRQ_BIT(INT_730_GPIO_BANK1);
|
||||
if (cpu_is_omap730())
|
||||
level1_wake = OMAP_IRQ_BIT(INT_730_GPIO_BANK1) |
|
||||
OMAP_IRQ_BIT(INT_730_IH2_IRQ);
|
||||
else if (cpu_is_omap1510())
|
||||
level1_wake = OMAP_IRQ_BIT(INT_GPIO_BANK1) |
|
||||
OMAP_IRQ_BIT(INT_1510_IH2_IRQ);
|
||||
else if (cpu_is_omap16xx())
|
||||
level1_wake = OMAP_IRQ_BIT(INT_GPIO_BANK1) |
|
||||
OMAP_IRQ_BIT(INT_1610_IH2_IRQ);
|
||||
|
||||
omap_writel(~level1_wake, OMAP_IH1_MIR);
|
||||
|
||||
if (cpu_is_omap1510())
|
||||
omap_writel(~level2_wake, OMAP_IH2_MIR);
|
||||
|
||||
/* INT_1610_WAKE_UP_REQ is needed for GPIO wakeup... */
|
||||
if (cpu_is_omap16xx()) {
|
||||
if (cpu_is_omap730()) {
|
||||
omap_writel(~level2_wake, OMAP_IH2_0_MIR);
|
||||
omap_writel(~(OMAP_IRQ_BIT(INT_730_WAKE_UP_REQ) | OMAP_IRQ_BIT(INT_730_MPUIO_KEYPAD)), OMAP_IH2_1_MIR);
|
||||
} else if (cpu_is_omap1510()) {
|
||||
level2_wake |= OMAP_IRQ_BIT(INT_KEYBOARD);
|
||||
omap_writel(~level2_wake, OMAP_IH2_MIR);
|
||||
} else if (cpu_is_omap16xx()) {
|
||||
level2_wake |= OMAP_IRQ_BIT(INT_KEYBOARD);
|
||||
omap_writel(~level2_wake, OMAP_IH2_0_MIR);
|
||||
|
||||
/* INT_1610_WAKE_UP_REQ is needed for GPIO wakeup... */
|
||||
omap_writel(~OMAP_IRQ_BIT(INT_1610_WAKE_UP_REQ), OMAP_IH2_1_MIR);
|
||||
omap_writel(~0x0, OMAP_IH2_2_MIR);
|
||||
omap_writel(~0x0, OMAP_IH2_3_MIR);
|
||||
|
|
@ -185,7 +196,17 @@ void omap_pm_suspend(void)
|
|||
* Save interrupt, MPUI, ARM and UPLD control registers.
|
||||
*/
|
||||
|
||||
if (cpu_is_omap1510()) {
|
||||
if (cpu_is_omap730()) {
|
||||
MPUI730_SAVE(OMAP_IH1_MIR);
|
||||
MPUI730_SAVE(OMAP_IH2_0_MIR);
|
||||
MPUI730_SAVE(OMAP_IH2_1_MIR);
|
||||
MPUI730_SAVE(MPUI_CTRL);
|
||||
MPUI730_SAVE(MPUI_DSP_BOOT_CONFIG);
|
||||
MPUI730_SAVE(MPUI_DSP_API_CONFIG);
|
||||
MPUI730_SAVE(EMIFS_CONFIG);
|
||||
MPUI730_SAVE(EMIFF_SDRAM_CONFIG);
|
||||
|
||||
} else if (cpu_is_omap1510()) {
|
||||
MPUI1510_SAVE(OMAP_IH1_MIR);
|
||||
MPUI1510_SAVE(OMAP_IH2_MIR);
|
||||
MPUI1510_SAVE(MPUI_CTRL);
|
||||
|
|
@ -280,7 +301,13 @@ void omap_pm_suspend(void)
|
|||
ULPD_RESTORE(ULPD_CLOCK_CTRL);
|
||||
ULPD_RESTORE(ULPD_STATUS_REQ);
|
||||
|
||||
if (cpu_is_omap1510()) {
|
||||
if (cpu_is_omap730()) {
|
||||
MPUI730_RESTORE(EMIFS_CONFIG);
|
||||
MPUI730_RESTORE(EMIFF_SDRAM_CONFIG);
|
||||
MPUI730_RESTORE(OMAP_IH1_MIR);
|
||||
MPUI730_RESTORE(OMAP_IH2_0_MIR);
|
||||
MPUI730_RESTORE(OMAP_IH2_1_MIR);
|
||||
} else if (cpu_is_omap1510()) {
|
||||
MPUI1510_RESTORE(MPUI_CTRL);
|
||||
MPUI1510_RESTORE(MPUI_DSP_BOOT_CONFIG);
|
||||
MPUI1510_RESTORE(MPUI_DSP_API_CONFIG);
|
||||
|
|
@ -355,7 +382,14 @@ static int omap_pm_read_proc(
|
|||
ULPD_SAVE(ULPD_DPLL_CTRL);
|
||||
ULPD_SAVE(ULPD_POWER_CTRL);
|
||||
|
||||
if (cpu_is_omap1510()) {
|
||||
if (cpu_is_omap730()) {
|
||||
MPUI730_SAVE(MPUI_CTRL);
|
||||
MPUI730_SAVE(MPUI_DSP_STATUS);
|
||||
MPUI730_SAVE(MPUI_DSP_BOOT_CONFIG);
|
||||
MPUI730_SAVE(MPUI_DSP_API_CONFIG);
|
||||
MPUI730_SAVE(EMIFF_SDRAM_CONFIG);
|
||||
MPUI730_SAVE(EMIFS_CONFIG);
|
||||
} else if (cpu_is_omap1510()) {
|
||||
MPUI1510_SAVE(MPUI_CTRL);
|
||||
MPUI1510_SAVE(MPUI_DSP_STATUS);
|
||||
MPUI1510_SAVE(MPUI_DSP_BOOT_CONFIG);
|
||||
|
|
@ -404,7 +438,21 @@ static int omap_pm_read_proc(
|
|||
ULPD_SHOW(ULPD_STATUS_REQ),
|
||||
ULPD_SHOW(ULPD_POWER_CTRL));
|
||||
|
||||
if (cpu_is_omap1510()) {
|
||||
if (cpu_is_omap730()) {
|
||||
my_buffer_offset += sprintf(my_base + my_buffer_offset,
|
||||
"MPUI730_CTRL_REG 0x%-8x \n"
|
||||
"MPUI730_DSP_STATUS_REG: 0x%-8x \n"
|
||||
"MPUI730_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
|
||||
"MPUI730_DSP_API_CONFIG_REG: 0x%-8x \n"
|
||||
"MPUI730_SDRAM_CONFIG_REG: 0x%-8x \n"
|
||||
"MPUI730_EMIFS_CONFIG_REG: 0x%-8x \n",
|
||||
MPUI730_SHOW(MPUI_CTRL),
|
||||
MPUI730_SHOW(MPUI_DSP_STATUS),
|
||||
MPUI730_SHOW(MPUI_DSP_BOOT_CONFIG),
|
||||
MPUI730_SHOW(MPUI_DSP_API_CONFIG),
|
||||
MPUI730_SHOW(EMIFF_SDRAM_CONFIG),
|
||||
MPUI730_SHOW(EMIFS_CONFIG));
|
||||
} else if (cpu_is_omap1510()) {
|
||||
my_buffer_offset += sprintf(my_base + my_buffer_offset,
|
||||
"MPUI1510_CTRL_REG 0x%-8x \n"
|
||||
"MPUI1510_DSP_STATUS_REG: 0x%-8x \n"
|
||||
|
|
@ -553,7 +601,12 @@ static int __init omap_pm_init(void)
|
|||
* These routines need to be in SRAM as that's the only
|
||||
* memory the MPU can see when it wakes up.
|
||||
*/
|
||||
if (cpu_is_omap1510()) {
|
||||
if (cpu_is_omap730()) {
|
||||
omap_sram_idle = omap_sram_push(omap730_idle_loop_suspend,
|
||||
omap730_idle_loop_suspend_sz);
|
||||
omap_sram_suspend = omap_sram_push(omap730_cpu_suspend,
|
||||
omap730_cpu_suspend_sz);
|
||||
} else if (cpu_is_omap1510()) {
|
||||
omap_sram_idle = omap_sram_push(omap1510_idle_loop_suspend,
|
||||
omap1510_idle_loop_suspend_sz);
|
||||
omap_sram_suspend = omap_sram_push(omap1510_cpu_suspend,
|
||||
|
|
@ -572,7 +625,11 @@ static int __init omap_pm_init(void)
|
|||
|
||||
pm_idle = omap_pm_idle;
|
||||
|
||||
setup_irq(INT_1610_WAKE_UP_REQ, &omap_wakeup_irq);
|
||||
if (cpu_is_omap730())
|
||||
setup_irq(INT_730_WAKE_UP_REQ, &omap_wakeup_irq);
|
||||
else if (cpu_is_omap16xx())
|
||||
setup_irq(INT_1610_WAKE_UP_REQ, &omap_wakeup_irq);
|
||||
|
||||
#if 0
|
||||
/* --- BEGIN BOARD-DEPENDENT CODE --- */
|
||||
/* Sleepx mask direction */
|
||||
|
|
@ -591,7 +648,9 @@ static int __init omap_pm_init(void)
|
|||
omap_writew(ULPD_POWER_CTRL_REG_VAL, ULPD_POWER_CTRL);
|
||||
|
||||
/* Configure IDLECT3 */
|
||||
if (cpu_is_omap16xx())
|
||||
if (cpu_is_omap730())
|
||||
omap_writel(OMAP730_IDLECT3_VAL, OMAP730_IDLECT3);
|
||||
else if (cpu_is_omap16xx())
|
||||
omap_writel(OMAP1610_IDLECT3_VAL, OMAP1610_IDLECT3);
|
||||
|
||||
pm_set_ops(&omap_pm_ops);
|
||||
|
|
@ -600,8 +659,10 @@ static int __init omap_pm_init(void)
|
|||
omap_pm_init_proc();
|
||||
#endif
|
||||
|
||||
/* configure LOW_PWR pin */
|
||||
omap_cfg_reg(T20_1610_LOW_PWR);
|
||||
if (cpu_is_omap16xx()) {
|
||||
/* configure LOW_PWR pin */
|
||||
omap_cfg_reg(T20_1610_LOW_PWR);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* linux/arch/arm/plat-omap/sleep.S
|
||||
*
|
||||
* Low-level OMAP1510/1610 sleep/wakeUp support
|
||||
* Low-level OMAP730/1510/1610 sleep/wakeUp support
|
||||
*
|
||||
* Initial SA1110 code:
|
||||
* Copyright (c) 2001 Cliff Brake <cbrake@accelent.com>
|
||||
|
|
@ -52,7 +52,57 @@
|
|||
* processor specific functions here.
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_ARCH_OMAP1510
|
||||
#if defined(CONFIG_ARCH_OMAP730)
|
||||
ENTRY(omap730_idle_loop_suspend)
|
||||
|
||||
stmfd sp!, {r0 - r12, lr} @ save registers on stack
|
||||
|
||||
@ load base address of ARM_IDLECT1 and ARM_IDLECT2
|
||||
mov r4, #CLKGEN_REG_ASM_BASE & 0xff000000
|
||||
orr r4, r4, #CLKGEN_REG_ASM_BASE & 0x00ff0000
|
||||
orr r4, r4, #CLKGEN_REG_ASM_BASE & 0x0000ff00
|
||||
|
||||
@ turn off clock domains
|
||||
@ get ARM_IDLECT2 into r2
|
||||
ldrh r2, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff]
|
||||
mov r5, #OMAP730_IDLECT2_SLEEP_VAL & 0xff
|
||||
orr r5, r5, #OMAP730_IDLECT2_SLEEP_VAL & 0xff00
|
||||
strh r5, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff]
|
||||
|
||||
@ request ARM idle
|
||||
@ get ARM_IDLECT1 into r1
|
||||
ldrh r1, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff]
|
||||
orr r3, r1, #OMAP730_IDLE_LOOP_REQUEST & 0xffff
|
||||
strh r3, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff]
|
||||
|
||||
mov r5, #IDLE_WAIT_CYCLES & 0xff
|
||||
orr r5, r5, #IDLE_WAIT_CYCLES & 0xff00
|
||||
l_730: subs r5, r5, #1
|
||||
bne l_730
|
||||
/*
|
||||
* Let's wait for the next clock tick to wake us up.
|
||||
*/
|
||||
mov r0, #0
|
||||
mcr p15, 0, r0, c7, c0, 4 @ wait for interrupt
|
||||
/*
|
||||
* omap730_idle_loop_suspend()'s resume point.
|
||||
*
|
||||
* It will just start executing here, so we'll restore stuff from the
|
||||
* stack, reset the ARM_IDLECT1 and ARM_IDLECT2.
|
||||
*/
|
||||
|
||||
@ restore ARM_IDLECT1 and ARM_IDLECT2 and return
|
||||
@ r1 has ARM_IDLECT1 and r2 still has ARM_IDLECT2
|
||||
strh r2, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff]
|
||||
strh r1, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff]
|
||||
|
||||
ldmfd sp!, {r0 - r12, pc} @ restore regs and return
|
||||
|
||||
ENTRY(omap730_idle_loop_suspend_sz)
|
||||
.word . - omap730_idle_loop_suspend
|
||||
#endif /* CONFIG_ARCH_OMAP730 */
|
||||
|
||||
#ifdef CONFIG_ARCH_OMAP15XX
|
||||
ENTRY(omap1510_idle_loop_suspend)
|
||||
|
||||
stmfd sp!, {r0 - r12, lr} @ save registers on stack
|
||||
|
|
@ -100,7 +150,7 @@ l_1510: subs r5, r5, #1
|
|||
|
||||
ENTRY(omap1510_idle_loop_suspend_sz)
|
||||
.word . - omap1510_idle_loop_suspend
|
||||
#endif /* CONFIG_ARCH_OMAP1510 */
|
||||
#endif /* CONFIG_ARCH_OMAP15XX */
|
||||
|
||||
#if defined(CONFIG_ARCH_OMAP16XX)
|
||||
ENTRY(omap1610_idle_loop_suspend)
|
||||
|
|
@ -169,7 +219,86 @@ ENTRY(omap1610_idle_loop_suspend_sz)
|
|||
*
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_ARCH_OMAP1510
|
||||
#if defined(CONFIG_ARCH_OMAP730)
|
||||
ENTRY(omap730_cpu_suspend)
|
||||
|
||||
@ save registers on stack
|
||||
stmfd sp!, {r0 - r12, lr}
|
||||
|
||||
@ Drain write cache
|
||||
mov r4, #0
|
||||
mcr p15, 0, r0, c7, c10, 4
|
||||
nop
|
||||
|
||||
@ load base address of Traffic Controller
|
||||
mov r6, #TCMIF_ASM_BASE & 0xff000000
|
||||
orr r6, r6, #TCMIF_ASM_BASE & 0x00ff0000
|
||||
orr r6, r6, #TCMIF_ASM_BASE & 0x0000ff00
|
||||
|
||||
@ prepare to put SDRAM into self-refresh manually
|
||||
ldr r7, [r6, #EMIFF_SDRAM_CONFIG_ASM_OFFSET & 0xff]
|
||||
orr r9, r7, #SELF_REFRESH_MODE & 0xff000000
|
||||
orr r9, r9, #SELF_REFRESH_MODE & 0x000000ff
|
||||
str r9, [r6, #EMIFF_SDRAM_CONFIG_ASM_OFFSET & 0xff]
|
||||
|
||||
@ prepare to put EMIFS to Sleep
|
||||
ldr r8, [r6, #EMIFS_CONFIG_ASM_OFFSET & 0xff]
|
||||
orr r9, r8, #IDLE_EMIFS_REQUEST & 0xff
|
||||
str r9, [r6, #EMIFS_CONFIG_ASM_OFFSET & 0xff]
|
||||
|
||||
@ load base address of ARM_IDLECT1 and ARM_IDLECT2
|
||||
mov r4, #CLKGEN_REG_ASM_BASE & 0xff000000
|
||||
orr r4, r4, #CLKGEN_REG_ASM_BASE & 0x00ff0000
|
||||
orr r4, r4, #CLKGEN_REG_ASM_BASE & 0x0000ff00
|
||||
|
||||
@ turn off clock domains
|
||||
@ do not disable PERCK (0x04)
|
||||
mov r5, #OMAP730_IDLECT2_SLEEP_VAL & 0xff
|
||||
orr r5, r5, #OMAP730_IDLECT2_SLEEP_VAL & 0xff00
|
||||
strh r5, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff]
|
||||
|
||||
@ request ARM idle
|
||||
mov r3, #OMAP730_IDLECT1_SLEEP_VAL & 0xff
|
||||
orr r3, r3, #OMAP730_IDLECT1_SLEEP_VAL & 0xff00
|
||||
strh r3, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff]
|
||||
|
||||
@ disable instruction cache
|
||||
mrc p15, 0, r9, c1, c0, 0
|
||||
bic r2, r9, #0x1000
|
||||
mcr p15, 0, r2, c1, c0, 0
|
||||
nop
|
||||
|
||||
/*
|
||||
* Let's wait for the next wake up event to wake us up. r0 can't be
|
||||
* used here because r0 holds ARM_IDLECT1
|
||||
*/
|
||||
mov r2, #0
|
||||
mcr p15, 0, r2, c7, c0, 4 @ wait for interrupt
|
||||
/*
|
||||
* omap730_cpu_suspend()'s resume point.
|
||||
*
|
||||
* It will just start executing here, so we'll restore stuff from the
|
||||
* stack.
|
||||
*/
|
||||
@ re-enable Icache
|
||||
mcr p15, 0, r9, c1, c0, 0
|
||||
|
||||
@ reset the ARM_IDLECT1 and ARM_IDLECT2.
|
||||
strh r1, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff]
|
||||
strh r0, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff]
|
||||
|
||||
@ Restore EMIFF controls
|
||||
str r7, [r6, #EMIFF_SDRAM_CONFIG_ASM_OFFSET & 0xff]
|
||||
str r8, [r6, #EMIFS_CONFIG_ASM_OFFSET & 0xff]
|
||||
|
||||
@ restore regs and return
|
||||
ldmfd sp!, {r0 - r12, pc}
|
||||
|
||||
ENTRY(omap730_cpu_suspend_sz)
|
||||
.word . - omap730_cpu_suspend
|
||||
#endif /* CONFIG_ARCH_OMAP730 */
|
||||
|
||||
#ifdef CONFIG_ARCH_OMAP15XX
|
||||
ENTRY(omap1510_cpu_suspend)
|
||||
|
||||
@ save registers on stack
|
||||
|
|
@ -241,7 +370,7 @@ l_1510_2:
|
|||
|
||||
ENTRY(omap1510_cpu_suspend_sz)
|
||||
.word . - omap1510_cpu_suspend
|
||||
#endif /* CONFIG_ARCH_OMAP1510 */
|
||||
#endif /* CONFIG_ARCH_OMAP15XX */
|
||||
|
||||
#if defined(CONFIG_ARCH_OMAP16XX)
|
||||
ENTRY(omap1610_cpu_suspend)
|
||||
|
|
|
|||
|
|
@ -20,10 +20,13 @@
|
|||
#include <asm/io.h>
|
||||
#include <asm/cacheflush.h>
|
||||
|
||||
#include "sram.h"
|
||||
#include <asm/arch/sram.h>
|
||||
|
||||
#define OMAP1_SRAM_PA 0x20000000
|
||||
#define OMAP1_SRAM_VA 0xd0000000
|
||||
#define OMAP2_SRAM_PA 0x40200000
|
||||
#define OMAP2_SRAM_VA 0xd0000000
|
||||
|
||||
#define OMAP1_SRAM_BASE 0xd0000000
|
||||
#define OMAP1_SRAM_START 0x20000000
|
||||
#define SRAM_BOOTLOADER_SZ 0x80
|
||||
|
||||
static unsigned long omap_sram_base;
|
||||
|
|
@ -31,37 +34,40 @@ static unsigned long omap_sram_size;
|
|||
static unsigned long omap_sram_ceil;
|
||||
|
||||
/*
|
||||
* The amount of SRAM depends on the core type:
|
||||
* 730 = 200K, 1510 = 512K, 5912 = 256K, 1610 = 16K, 1710 = 16K
|
||||
* The amount of SRAM depends on the core type.
|
||||
* Note that we cannot try to test for SRAM here because writes
|
||||
* to secure SRAM will hang the system. Also the SRAM is not
|
||||
* yet mapped at this point.
|
||||
*/
|
||||
void __init omap_detect_sram(void)
|
||||
{
|
||||
omap_sram_base = OMAP1_SRAM_BASE;
|
||||
if (!cpu_is_omap24xx())
|
||||
omap_sram_base = OMAP1_SRAM_VA;
|
||||
else
|
||||
omap_sram_base = OMAP2_SRAM_VA;
|
||||
|
||||
if (cpu_is_omap730())
|
||||
omap_sram_size = 0x32000;
|
||||
else if (cpu_is_omap1510())
|
||||
omap_sram_size = 0x80000;
|
||||
omap_sram_size = 0x32000; /* 200K */
|
||||
else if (cpu_is_omap15xx())
|
||||
omap_sram_size = 0x30000; /* 192K */
|
||||
else if (cpu_is_omap1610() || cpu_is_omap1621() || cpu_is_omap1710())
|
||||
omap_sram_size = 0x4000;
|
||||
omap_sram_size = 0x4000; /* 16K */
|
||||
else if (cpu_is_omap1611())
|
||||
omap_sram_size = 0x3e800;
|
||||
omap_sram_size = 0x3e800; /* 250K */
|
||||
else if (cpu_is_omap2420())
|
||||
omap_sram_size = 0xa0014; /* 640K */
|
||||
else {
|
||||
printk(KERN_ERR "Could not detect SRAM size\n");
|
||||
omap_sram_size = 0x4000;
|
||||
}
|
||||
|
||||
printk(KERN_INFO "SRAM size: 0x%lx\n", omap_sram_size);
|
||||
omap_sram_ceil = omap_sram_base + omap_sram_size;
|
||||
}
|
||||
|
||||
static struct map_desc omap_sram_io_desc[] __initdata = {
|
||||
{ /* .length gets filled in at runtime */
|
||||
.virtual = OMAP1_SRAM_BASE,
|
||||
.pfn = __phys_to_pfn(OMAP1_SRAM_START),
|
||||
.virtual = OMAP1_SRAM_VA,
|
||||
.pfn = __phys_to_pfn(OMAP1_SRAM_PA),
|
||||
.type = MT_DEVICE
|
||||
}
|
||||
};
|
||||
|
|
@ -76,10 +82,19 @@ void __init omap_map_sram(void)
|
|||
if (omap_sram_size == 0)
|
||||
return;
|
||||
|
||||
if (cpu_is_omap24xx()) {
|
||||
omap_sram_io_desc[0].virtual = OMAP2_SRAM_VA;
|
||||
omap_sram_io_desc[0].pfn = __phys_to_pfn(OMAP2_SRAM_PA);
|
||||
}
|
||||
|
||||
omap_sram_io_desc[0].length = (omap_sram_size + PAGE_SIZE-1)/PAGE_SIZE;
|
||||
omap_sram_io_desc[0].length *= PAGE_SIZE;
|
||||
iotable_init(omap_sram_io_desc, ARRAY_SIZE(omap_sram_io_desc));
|
||||
|
||||
printk(KERN_INFO "SRAM: Mapped pa 0x%08lx to va 0x%08lx size: 0x%lx\n",
|
||||
omap_sram_io_desc[0].pfn, omap_sram_io_desc[0].virtual,
|
||||
omap_sram_io_desc[0].length);
|
||||
|
||||
/*
|
||||
* Looks like we need to preserve some bootloader code at the
|
||||
* beginning of SRAM for jumping to flash for reboot to work...
|
||||
|
|
@ -88,16 +103,6 @@ void __init omap_map_sram(void)
|
|||
omap_sram_size - SRAM_BOOTLOADER_SZ);
|
||||
}
|
||||
|
||||
static void (*_omap_sram_reprogram_clock)(u32 dpllctl, u32 ckctl) = NULL;
|
||||
|
||||
void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl)
|
||||
{
|
||||
if (_omap_sram_reprogram_clock == NULL)
|
||||
panic("Cannot use SRAM");
|
||||
|
||||
return _omap_sram_reprogram_clock(dpllctl, ckctl);
|
||||
}
|
||||
|
||||
void * omap_sram_push(void * start, unsigned long size)
|
||||
{
|
||||
if (size > (omap_sram_ceil - (omap_sram_base + SRAM_BOOTLOADER_SZ))) {
|
||||
|
|
@ -111,10 +116,94 @@ void * omap_sram_push(void * start, unsigned long size)
|
|||
return (void *)omap_sram_ceil;
|
||||
}
|
||||
|
||||
void __init omap_sram_init(void)
|
||||
static void omap_sram_error(void)
|
||||
{
|
||||
panic("Uninitialized SRAM function\n");
|
||||
}
|
||||
|
||||
#ifdef CONFIG_ARCH_OMAP1
|
||||
|
||||
static void (*_omap_sram_reprogram_clock)(u32 dpllctl, u32 ckctl);
|
||||
|
||||
void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl)
|
||||
{
|
||||
if (!_omap_sram_reprogram_clock)
|
||||
omap_sram_error();
|
||||
|
||||
return _omap_sram_reprogram_clock(dpllctl, ckctl);
|
||||
}
|
||||
|
||||
int __init omap1_sram_init(void)
|
||||
{
|
||||
_omap_sram_reprogram_clock = omap_sram_push(sram_reprogram_clock,
|
||||
sram_reprogram_clock_sz);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#else
|
||||
#define omap1_sram_init() do {} while (0)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARCH_OMAP2
|
||||
|
||||
static void (*_omap2_sram_ddr_init)(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
|
||||
u32 base_cs, u32 force_unlock);
|
||||
|
||||
void omap2_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
|
||||
u32 base_cs, u32 force_unlock)
|
||||
{
|
||||
if (!_omap2_sram_ddr_init)
|
||||
omap_sram_error();
|
||||
|
||||
return _omap2_sram_ddr_init(slow_dll_ctrl, fast_dll_ctrl,
|
||||
base_cs, force_unlock);
|
||||
}
|
||||
|
||||
static void (*_omap2_sram_reprogram_sdrc)(u32 perf_level, u32 dll_val,
|
||||
u32 mem_type);
|
||||
|
||||
void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val, u32 mem_type)
|
||||
{
|
||||
if (!_omap2_sram_reprogram_sdrc)
|
||||
omap_sram_error();
|
||||
|
||||
return _omap2_sram_reprogram_sdrc(perf_level, dll_val, mem_type);
|
||||
}
|
||||
|
||||
static u32 (*_omap2_set_prcm)(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
|
||||
|
||||
u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass)
|
||||
{
|
||||
if (!_omap2_set_prcm)
|
||||
omap_sram_error();
|
||||
|
||||
return _omap2_set_prcm(dpll_ctrl_val, sdrc_rfr_val, bypass);
|
||||
}
|
||||
|
||||
int __init omap2_sram_init(void)
|
||||
{
|
||||
_omap2_sram_ddr_init = omap_sram_push(sram_ddr_init, sram_ddr_init_sz);
|
||||
|
||||
_omap2_sram_reprogram_sdrc = omap_sram_push(sram_reprogram_sdrc,
|
||||
sram_reprogram_sdrc_sz);
|
||||
_omap2_set_prcm = omap_sram_push(sram_set_prcm, sram_set_prcm_sz);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#else
|
||||
#define omap2_sram_init() do {} while (0)
|
||||
#endif
|
||||
|
||||
int __init omap_sram_init(void)
|
||||
{
|
||||
omap_detect_sram();
|
||||
omap_map_sram();
|
||||
_omap_sram_reprogram_clock = omap_sram_push(sram_reprogram_clock,
|
||||
sram_reprogram_clock_sz);
|
||||
|
||||
if (!cpu_is_omap24xx())
|
||||
omap1_sram_init();
|
||||
else
|
||||
omap2_sram_init();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,21 +0,0 @@
|
|||
/*
|
||||
* linux/arch/arm/plat-omap/sram.h
|
||||
*
|
||||
* Interface for functions that need to be run in internal SRAM
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __ARCH_ARM_OMAP_SRAM_H
|
||||
#define __ARCH_ARM_OMAP_SRAM_H
|
||||
|
||||
extern void * omap_sram_push(void * start, unsigned long size);
|
||||
extern void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl);
|
||||
|
||||
/* Do not use these */
|
||||
extern void sram_reprogram_clock(u32 ckctl, u32 dpllctl);
|
||||
extern unsigned long sram_reprogram_clock_sz;
|
||||
|
||||
#endif
|
||||
|
|
@ -91,6 +91,8 @@ EXPORT_SYMBOL(otg_set_transceiver);
|
|||
|
||||
/*-------------------------------------------------------------------------*/
|
||||
|
||||
#if defined(CONFIG_ARCH_OMAP_OTG) || defined(CONFIG_ARCH_OMAP15XX)
|
||||
|
||||
static u32 __init omap_usb0_init(unsigned nwires, unsigned is_device)
|
||||
{
|
||||
u32 syscon1 = 0;
|
||||
|
|
@ -271,6 +273,8 @@ static u32 __init omap_usb2_init(unsigned nwires, unsigned alt_pingroup)
|
|||
return syscon1 << 24;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
/*-------------------------------------------------------------------------*/
|
||||
|
||||
#if defined(CONFIG_USB_GADGET_OMAP) || \
|
||||
|
|
@ -494,7 +498,7 @@ static inline void omap_otg_init(struct omap_usb_config *config) {}
|
|||
|
||||
/*-------------------------------------------------------------------------*/
|
||||
|
||||
#ifdef CONFIG_ARCH_OMAP1510
|
||||
#ifdef CONFIG_ARCH_OMAP15XX
|
||||
|
||||
#define ULPD_DPLL_CTRL_REG __REG16(ULPD_DPLL_CTRL)
|
||||
#define DPLL_IOB (1 << 13)
|
||||
|
|
@ -507,7 +511,6 @@ static inline void omap_otg_init(struct omap_usb_config *config) {}
|
|||
|
||||
static void __init omap_1510_usb_init(struct omap_usb_config *config)
|
||||
{
|
||||
int status;
|
||||
unsigned int val;
|
||||
|
||||
omap_usb0_init(config->pins[0], is_usb0_device(config));
|
||||
|
|
@ -539,6 +542,8 @@ static void __init omap_1510_usb_init(struct omap_usb_config *config)
|
|||
|
||||
#ifdef CONFIG_USB_GADGET_OMAP
|
||||
if (config->register_dev) {
|
||||
int status;
|
||||
|
||||
udc_device.dev.platform_data = config;
|
||||
status = platform_device_register(&udc_device);
|
||||
if (status)
|
||||
|
|
@ -549,6 +554,8 @@ static void __init omap_1510_usb_init(struct omap_usb_config *config)
|
|||
|
||||
#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
|
||||
if (config->register_host) {
|
||||
int status;
|
||||
|
||||
ohci_device.dev.platform_data = config;
|
||||
status = platform_device_register(&ohci_device);
|
||||
if (status)
|
||||
|
|
|
|||
Loading…
Reference in New Issue