MIPS: Octeon: Make interrupt controller work with threaded handlers.
For CIUv1 controllers, we were relying on all calls to the irq_chip functions to be done from the CPU that received the irq, and that they would all be done from interrupt contest. These assumptions do not hold for threaded handlers. We make all the masking actually mask the irq source, and use real raw_spin_locks instead of manually twiddling the Status[IE] bit. Signed-off-by: David Daney <david.daney@cavium.com>
This commit is contained in:
David Daney
parent
88fd85892a
commit
1a7e68f2c7
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@ -18,11 +18,9 @@
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#include <asm/octeon/octeon.h>
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#include <asm/octeon/cvmx-ciu2-defs.h>
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static DEFINE_RAW_SPINLOCK(octeon_irq_ciu0_lock);
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static DEFINE_RAW_SPINLOCK(octeon_irq_ciu1_lock);
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static DEFINE_PER_CPU(unsigned long, octeon_irq_ciu0_en_mirror);
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static DEFINE_PER_CPU(unsigned long, octeon_irq_ciu1_en_mirror);
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static DEFINE_PER_CPU(raw_spinlock_t, octeon_irq_ciu_spinlock);
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static __read_mostly u8 octeon_irq_ciu_to_irq[8][64];
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@ -234,22 +232,31 @@ static void octeon_irq_ciu_enable(struct irq_data *data)
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unsigned long *pen;
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unsigned long flags;
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union octeon_ciu_chip_data cd;
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raw_spinlock_t *lock = &per_cpu(octeon_irq_ciu_spinlock, cpu);
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cd.p = irq_data_get_irq_chip_data(data);
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raw_spin_lock_irqsave(lock, flags);
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if (cd.s.line == 0) {
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raw_spin_lock_irqsave(&octeon_irq_ciu0_lock, flags);
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pen = &per_cpu(octeon_irq_ciu0_en_mirror, cpu);
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set_bit(cd.s.bit, pen);
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__set_bit(cd.s.bit, pen);
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/*
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* Must be visible to octeon_irq_ip{2,3}_ciu() before
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* enabling the irq.
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*/
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wmb();
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cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), *pen);
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raw_spin_unlock_irqrestore(&octeon_irq_ciu0_lock, flags);
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} else {
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raw_spin_lock_irqsave(&octeon_irq_ciu1_lock, flags);
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pen = &per_cpu(octeon_irq_ciu1_en_mirror, cpu);
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set_bit(cd.s.bit, pen);
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__set_bit(cd.s.bit, pen);
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/*
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* Must be visible to octeon_irq_ip{2,3}_ciu() before
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* enabling the irq.
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*/
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wmb();
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cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), *pen);
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raw_spin_unlock_irqrestore(&octeon_irq_ciu1_lock, flags);
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}
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raw_spin_unlock_irqrestore(lock, flags);
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}
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static void octeon_irq_ciu_enable_local(struct irq_data *data)
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@ -257,22 +264,31 @@ static void octeon_irq_ciu_enable_local(struct irq_data *data)
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unsigned long *pen;
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unsigned long flags;
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union octeon_ciu_chip_data cd;
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raw_spinlock_t *lock = &__get_cpu_var(octeon_irq_ciu_spinlock);
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cd.p = irq_data_get_irq_chip_data(data);
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raw_spin_lock_irqsave(lock, flags);
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if (cd.s.line == 0) {
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raw_spin_lock_irqsave(&octeon_irq_ciu0_lock, flags);
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pen = &__get_cpu_var(octeon_irq_ciu0_en_mirror);
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set_bit(cd.s.bit, pen);
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__set_bit(cd.s.bit, pen);
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/*
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* Must be visible to octeon_irq_ip{2,3}_ciu() before
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* enabling the irq.
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*/
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wmb();
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cvmx_write_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num() * 2), *pen);
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raw_spin_unlock_irqrestore(&octeon_irq_ciu0_lock, flags);
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} else {
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raw_spin_lock_irqsave(&octeon_irq_ciu1_lock, flags);
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pen = &__get_cpu_var(octeon_irq_ciu1_en_mirror);
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set_bit(cd.s.bit, pen);
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__set_bit(cd.s.bit, pen);
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/*
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* Must be visible to octeon_irq_ip{2,3}_ciu() before
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* enabling the irq.
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*/
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wmb();
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cvmx_write_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num() * 2 + 1), *pen);
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raw_spin_unlock_irqrestore(&octeon_irq_ciu1_lock, flags);
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}
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raw_spin_unlock_irqrestore(lock, flags);
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}
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static void octeon_irq_ciu_disable_local(struct irq_data *data)
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@ -280,22 +296,31 @@ static void octeon_irq_ciu_disable_local(struct irq_data *data)
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unsigned long *pen;
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unsigned long flags;
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union octeon_ciu_chip_data cd;
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raw_spinlock_t *lock = &__get_cpu_var(octeon_irq_ciu_spinlock);
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cd.p = irq_data_get_irq_chip_data(data);
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raw_spin_lock_irqsave(lock, flags);
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if (cd.s.line == 0) {
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raw_spin_lock_irqsave(&octeon_irq_ciu0_lock, flags);
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pen = &__get_cpu_var(octeon_irq_ciu0_en_mirror);
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clear_bit(cd.s.bit, pen);
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__clear_bit(cd.s.bit, pen);
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/*
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* Must be visible to octeon_irq_ip{2,3}_ciu() before
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* enabling the irq.
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*/
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wmb();
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cvmx_write_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num() * 2), *pen);
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raw_spin_unlock_irqrestore(&octeon_irq_ciu0_lock, flags);
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} else {
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raw_spin_lock_irqsave(&octeon_irq_ciu1_lock, flags);
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pen = &__get_cpu_var(octeon_irq_ciu1_en_mirror);
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clear_bit(cd.s.bit, pen);
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__clear_bit(cd.s.bit, pen);
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/*
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* Must be visible to octeon_irq_ip{2,3}_ciu() before
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* enabling the irq.
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*/
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wmb();
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cvmx_write_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num() * 2 + 1), *pen);
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raw_spin_unlock_irqrestore(&octeon_irq_ciu1_lock, flags);
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}
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raw_spin_unlock_irqrestore(lock, flags);
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}
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static void octeon_irq_ciu_disable_all(struct irq_data *data)
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@ -304,29 +329,30 @@ static void octeon_irq_ciu_disable_all(struct irq_data *data)
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unsigned long *pen;
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int cpu;
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union octeon_ciu_chip_data cd;
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wmb(); /* Make sure flag changes arrive before register updates. */
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raw_spinlock_t *lock;
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cd.p = irq_data_get_irq_chip_data(data);
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if (cd.s.line == 0) {
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raw_spin_lock_irqsave(&octeon_irq_ciu0_lock, flags);
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for_each_online_cpu(cpu) {
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int coreid = octeon_coreid_for_cpu(cpu);
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lock = &per_cpu(octeon_irq_ciu_spinlock, cpu);
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if (cd.s.line == 0)
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pen = &per_cpu(octeon_irq_ciu0_en_mirror, cpu);
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clear_bit(cd.s.bit, pen);
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cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), *pen);
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}
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raw_spin_unlock_irqrestore(&octeon_irq_ciu0_lock, flags);
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} else {
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raw_spin_lock_irqsave(&octeon_irq_ciu1_lock, flags);
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for_each_online_cpu(cpu) {
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int coreid = octeon_coreid_for_cpu(cpu);
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else
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pen = &per_cpu(octeon_irq_ciu1_en_mirror, cpu);
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clear_bit(cd.s.bit, pen);
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raw_spin_lock_irqsave(lock, flags);
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__clear_bit(cd.s.bit, pen);
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/*
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* Must be visible to octeon_irq_ip{2,3}_ciu() before
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* enabling the irq.
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*/
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wmb();
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if (cd.s.line == 0)
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cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), *pen);
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else
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cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), *pen);
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}
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raw_spin_unlock_irqrestore(&octeon_irq_ciu1_lock, flags);
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raw_spin_unlock_irqrestore(lock, flags);
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}
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}
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@ -336,27 +362,30 @@ static void octeon_irq_ciu_enable_all(struct irq_data *data)
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unsigned long *pen;
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int cpu;
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union octeon_ciu_chip_data cd;
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raw_spinlock_t *lock;
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cd.p = irq_data_get_irq_chip_data(data);
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if (cd.s.line == 0) {
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raw_spin_lock_irqsave(&octeon_irq_ciu0_lock, flags);
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for_each_online_cpu(cpu) {
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int coreid = octeon_coreid_for_cpu(cpu);
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lock = &per_cpu(octeon_irq_ciu_spinlock, cpu);
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if (cd.s.line == 0)
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pen = &per_cpu(octeon_irq_ciu0_en_mirror, cpu);
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set_bit(cd.s.bit, pen);
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cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), *pen);
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}
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raw_spin_unlock_irqrestore(&octeon_irq_ciu0_lock, flags);
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} else {
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raw_spin_lock_irqsave(&octeon_irq_ciu1_lock, flags);
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for_each_online_cpu(cpu) {
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int coreid = octeon_coreid_for_cpu(cpu);
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else
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pen = &per_cpu(octeon_irq_ciu1_en_mirror, cpu);
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set_bit(cd.s.bit, pen);
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raw_spin_lock_irqsave(lock, flags);
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__set_bit(cd.s.bit, pen);
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/*
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* Must be visible to octeon_irq_ip{2,3}_ciu() before
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* enabling the irq.
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*/
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wmb();
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if (cd.s.line == 0)
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cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), *pen);
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else
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cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), *pen);
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}
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raw_spin_unlock_irqrestore(&octeon_irq_ciu1_lock, flags);
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raw_spin_unlock_irqrestore(lock, flags);
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}
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}
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@ -459,8 +488,6 @@ static void octeon_irq_ciu_disable_all_v2(struct irq_data *data)
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u64 mask;
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union octeon_ciu_chip_data cd;
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wmb(); /* Make sure flag changes arrive before register updates. */
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cd.p = irq_data_get_irq_chip_data(data);
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mask = 1ull << (cd.s.bit);
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@ -618,6 +645,8 @@ static int octeon_irq_ciu_set_affinity(struct irq_data *data,
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bool enable_one = !irqd_irq_disabled(data) && !irqd_irq_masked(data);
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unsigned long flags;
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union octeon_ciu_chip_data cd;
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unsigned long *pen;
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raw_spinlock_t *lock;
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cd.p = irq_data_get_irq_chip_data(data);
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@ -632,36 +661,36 @@ static int octeon_irq_ciu_set_affinity(struct irq_data *data,
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if (!enable_one)
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return 0;
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if (cd.s.line == 0) {
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raw_spin_lock_irqsave(&octeon_irq_ciu0_lock, flags);
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for_each_online_cpu(cpu) {
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int coreid = octeon_coreid_for_cpu(cpu);
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unsigned long *pen = &per_cpu(octeon_irq_ciu0_en_mirror, cpu);
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lock = &per_cpu(octeon_irq_ciu_spinlock, cpu);
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raw_spin_lock_irqsave(lock, flags);
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if (cd.s.line == 0)
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pen = &per_cpu(octeon_irq_ciu0_en_mirror, cpu);
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else
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pen = &per_cpu(octeon_irq_ciu1_en_mirror, cpu);
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if (cpumask_test_cpu(cpu, dest) && enable_one) {
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enable_one = false;
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set_bit(cd.s.bit, pen);
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enable_one = 0;
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__set_bit(cd.s.bit, pen);
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} else {
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clear_bit(cd.s.bit, pen);
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__clear_bit(cd.s.bit, pen);
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}
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/*
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* Must be visible to octeon_irq_ip{2,3}_ciu() before
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* enabling the irq.
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*/
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wmb();
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if (cd.s.line == 0)
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cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), *pen);
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}
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raw_spin_unlock_irqrestore(&octeon_irq_ciu0_lock, flags);
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} else {
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raw_spin_lock_irqsave(&octeon_irq_ciu1_lock, flags);
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for_each_online_cpu(cpu) {
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int coreid = octeon_coreid_for_cpu(cpu);
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unsigned long *pen = &per_cpu(octeon_irq_ciu1_en_mirror, cpu);
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if (cpumask_test_cpu(cpu, dest) && enable_one) {
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enable_one = false;
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set_bit(cd.s.bit, pen);
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} else {
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clear_bit(cd.s.bit, pen);
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}
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else
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cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), *pen);
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}
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raw_spin_unlock_irqrestore(&octeon_irq_ciu1_lock, flags);
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raw_spin_unlock_irqrestore(lock, flags);
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}
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return 0;
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}
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@ -716,14 +745,6 @@ static int octeon_irq_ciu_set_affinity_v2(struct irq_data *data,
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}
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#endif
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/*
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* The v1 CIU code already masks things, so supply a dummy version to
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* the core chip code.
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*/
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static void octeon_irq_dummy_mask(struct irq_data *data)
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{
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}
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/*
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* Newer octeon chips have support for lockless CIU operation.
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*/
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@ -745,7 +766,8 @@ static struct irq_chip octeon_irq_chip_ciu = {
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.irq_enable = octeon_irq_ciu_enable,
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.irq_disable = octeon_irq_ciu_disable_all,
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.irq_ack = octeon_irq_ciu_ack,
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.irq_mask = octeon_irq_dummy_mask,
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.irq_mask = octeon_irq_ciu_disable_local,
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.irq_unmask = octeon_irq_ciu_enable,
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#ifdef CONFIG_SMP
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.irq_set_affinity = octeon_irq_ciu_set_affinity,
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.irq_cpu_offline = octeon_irq_cpu_offline_ciu,
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@ -769,6 +791,8 @@ static struct irq_chip octeon_irq_chip_ciu_mbox = {
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.name = "CIU-M",
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.irq_enable = octeon_irq_ciu_enable_all,
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.irq_disable = octeon_irq_ciu_disable_all,
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.irq_ack = octeon_irq_ciu_disable_local,
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.irq_eoi = octeon_irq_ciu_enable_local,
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.irq_cpu_online = octeon_irq_ciu_enable_local,
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.irq_cpu_offline = octeon_irq_ciu_disable_local,
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@ -793,7 +817,8 @@ static struct irq_chip octeon_irq_chip_ciu_gpio = {
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.name = "CIU-GPIO",
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.irq_enable = octeon_irq_ciu_enable_gpio,
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.irq_disable = octeon_irq_ciu_disable_gpio,
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.irq_mask = octeon_irq_dummy_mask,
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.irq_mask = octeon_irq_ciu_disable_local,
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.irq_unmask = octeon_irq_ciu_enable,
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.irq_ack = octeon_irq_ciu_gpio_ack,
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.irq_set_type = octeon_irq_ciu_gpio_set_type,
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#ifdef CONFIG_SMP
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@ -812,12 +837,18 @@ static void octeon_irq_ciu_wd_enable(struct irq_data *data)
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unsigned long *pen;
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int coreid = data->irq - OCTEON_IRQ_WDOG0; /* Bit 0-63 of EN1 */
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int cpu = octeon_cpu_for_coreid(coreid);
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raw_spinlock_t *lock = &per_cpu(octeon_irq_ciu_spinlock, cpu);
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raw_spin_lock_irqsave(&octeon_irq_ciu1_lock, flags);
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raw_spin_lock_irqsave(lock, flags);
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pen = &per_cpu(octeon_irq_ciu1_en_mirror, cpu);
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set_bit(coreid, pen);
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__set_bit(coreid, pen);
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/*
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* Must be visible to octeon_irq_ip{2,3}_ciu() before enabling
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* the irq.
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*/
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wmb();
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cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), *pen);
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raw_spin_unlock_irqrestore(&octeon_irq_ciu1_lock, flags);
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raw_spin_unlock_irqrestore(lock, flags);
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}
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/*
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@ -846,7 +877,8 @@ static struct irq_chip octeon_irq_chip_ciu_wd = {
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.name = "CIU-W",
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.irq_enable = octeon_irq_ciu_wd_enable,
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.irq_disable = octeon_irq_ciu_disable_all,
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.irq_mask = octeon_irq_dummy_mask,
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.irq_mask = octeon_irq_ciu_disable_local,
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.irq_unmask = octeon_irq_ciu_enable_local,
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};
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static bool octeon_irq_ciu_is_edge(unsigned int line, unsigned int bit)
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@ -1027,27 +1059,7 @@ static struct irq_domain_ops octeon_irq_domain_gpio_ops = {
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.xlate = octeon_irq_gpio_xlat,
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};
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static void octeon_irq_ip2_v1(void)
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{
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const unsigned long core_id = cvmx_get_core_num();
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u64 ciu_sum = cvmx_read_csr(CVMX_CIU_INTX_SUM0(core_id * 2));
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ciu_sum &= __get_cpu_var(octeon_irq_ciu0_en_mirror);
|
||||
clear_c0_status(STATUSF_IP2);
|
||||
if (likely(ciu_sum)) {
|
||||
int bit = fls64(ciu_sum) - 1;
|
||||
int irq = octeon_irq_ciu_to_irq[0][bit];
|
||||
if (likely(irq))
|
||||
do_IRQ(irq);
|
||||
else
|
||||
spurious_interrupt();
|
||||
} else {
|
||||
spurious_interrupt();
|
||||
}
|
||||
set_c0_status(STATUSF_IP2);
|
||||
}
|
||||
|
||||
static void octeon_irq_ip2_v2(void)
|
||||
static void octeon_irq_ip2_ciu(void)
|
||||
{
|
||||
const unsigned long core_id = cvmx_get_core_num();
|
||||
u64 ciu_sum = cvmx_read_csr(CVMX_CIU_INTX_SUM0(core_id * 2));
|
||||
|
|
@ -1064,26 +1076,8 @@ static void octeon_irq_ip2_v2(void)
|
|||
spurious_interrupt();
|
||||
}
|
||||
}
|
||||
static void octeon_irq_ip3_v1(void)
|
||||
{
|
||||
u64 ciu_sum = cvmx_read_csr(CVMX_CIU_INT_SUM1);
|
||||
|
||||
ciu_sum &= __get_cpu_var(octeon_irq_ciu1_en_mirror);
|
||||
clear_c0_status(STATUSF_IP3);
|
||||
if (likely(ciu_sum)) {
|
||||
int bit = fls64(ciu_sum) - 1;
|
||||
int irq = octeon_irq_ciu_to_irq[1][bit];
|
||||
if (likely(irq))
|
||||
do_IRQ(irq);
|
||||
else
|
||||
spurious_interrupt();
|
||||
} else {
|
||||
spurious_interrupt();
|
||||
}
|
||||
set_c0_status(STATUSF_IP3);
|
||||
}
|
||||
|
||||
static void octeon_irq_ip3_v2(void)
|
||||
static void octeon_irq_ip3_ciu(void)
|
||||
{
|
||||
u64 ciu_sum = cvmx_read_csr(CVMX_CIU_INT_SUM1);
|
||||
|
||||
|
|
@ -1134,6 +1128,12 @@ static void __cpuinit octeon_irq_percpu_enable(void)
|
|||
static void __cpuinit octeon_irq_init_ciu_percpu(void)
|
||||
{
|
||||
int coreid = cvmx_get_core_num();
|
||||
|
||||
|
||||
__get_cpu_var(octeon_irq_ciu0_en_mirror) = 0;
|
||||
__get_cpu_var(octeon_irq_ciu1_en_mirror) = 0;
|
||||
wmb();
|
||||
raw_spin_lock_init(&__get_cpu_var(octeon_irq_ciu_spinlock));
|
||||
/*
|
||||
* Disable All CIU Interrupts. The ones we need will be
|
||||
* enabled later. Read the SUM register so we know the write
|
||||
|
|
@ -1170,10 +1170,6 @@ static void octeon_irq_init_ciu2_percpu(void)
|
|||
|
||||
static void __cpuinit octeon_irq_setup_secondary_ciu(void)
|
||||
{
|
||||
|
||||
__get_cpu_var(octeon_irq_ciu0_en_mirror) = 0;
|
||||
__get_cpu_var(octeon_irq_ciu1_en_mirror) = 0;
|
||||
|
||||
octeon_irq_init_ciu_percpu();
|
||||
octeon_irq_percpu_enable();
|
||||
|
||||
|
|
@ -1208,19 +1204,17 @@ static void __init octeon_irq_init_ciu(void)
|
|||
octeon_irq_init_ciu_percpu();
|
||||
octeon_irq_setup_secondary = octeon_irq_setup_secondary_ciu;
|
||||
|
||||
octeon_irq_ip2 = octeon_irq_ip2_ciu;
|
||||
octeon_irq_ip3 = octeon_irq_ip3_ciu;
|
||||
if (OCTEON_IS_MODEL(OCTEON_CN58XX_PASS2_X) ||
|
||||
OCTEON_IS_MODEL(OCTEON_CN56XX_PASS2_X) ||
|
||||
OCTEON_IS_MODEL(OCTEON_CN52XX_PASS2_X) ||
|
||||
OCTEON_IS_MODEL(OCTEON_CN6XXX)) {
|
||||
octeon_irq_ip2 = octeon_irq_ip2_v2;
|
||||
octeon_irq_ip3 = octeon_irq_ip3_v2;
|
||||
chip = &octeon_irq_chip_ciu_v2;
|
||||
chip_mbox = &octeon_irq_chip_ciu_mbox_v2;
|
||||
chip_wd = &octeon_irq_chip_ciu_wd_v2;
|
||||
octeon_irq_gpio_chip = &octeon_irq_chip_ciu_gpio_v2;
|
||||
} else {
|
||||
octeon_irq_ip2 = octeon_irq_ip2_v1;
|
||||
octeon_irq_ip3 = octeon_irq_ip3_v1;
|
||||
chip = &octeon_irq_chip_ciu;
|
||||
chip_mbox = &octeon_irq_chip_ciu_mbox;
|
||||
chip_wd = &octeon_irq_chip_ciu_wd;
|
||||
|
|
|
|||
Loading…
Reference in New Issue