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mlx5-dr-2021-01-29 

Add support for Connect-X6DX Software steering
 
 This series adds SW Steering support for Connect-X6DX.
 
 Since the STE and actions formats are different on this new HW,
 we implemented the HW specific STEv1 layer on the infrastructure
 implemented in previous mlx5 DR patchset to support all the
 functionalities as previous devices.
 
 Most of the code in this series very is low level HW specific, we
 implement the function pointers for the generic SW steering layer.
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Merge tag 'mlx5-dr-2021-01-29' of git://git.kernel.org/pub/scm/linux/kernel/git/saeed/linux

Saeed Mahameed says:

====================
mlx5-dr-2021-01-29

Add support for Connect-X6DX Software steering

This series adds SW Steering support for Connect-X6DX.

Since the STE and actions formats are different on this new HW,
we implemented the HW specific STEv1 layer on the infrastructure
implemented in previous mlx5 DR patchset to support all the
functionalities as previous devices.

Most of the code in this series very is low level HW specific, we
implement the function pointers for the generic SW steering layer.

* tag 'mlx5-dr-2021-01-29' of git://git.kernel.org/pub/scm/linux/kernel/git/saeed/linux:
  net/mlx5: DR, Allow SW steering for sw_owner_v2 devices
  net/mlx5: DR, Copy all 64B whenever replacing STE in the head of miss-list
  net/mlx5: DR, Use HW specific logic API when writing STE
  net/mlx5: DR, Use the right size when writing partial STE into HW
  net/mlx5: DR, Add STEv1 modify header logic
  net/mlx5: DR, Add STEv1 action apply logic
  net/mlx5: DR, Add STEv1 setters and getters
  net/mlx5: DR, Allow native protocol support for HW STEv1
  net/mlx5: DR, Add HW STEv1 match logic
  net/mlx5: DR, Add match STEv1 structs to ifc
  net/mlx5: DR, Fix potential shift wrapping of 32-bit value
====================

Link: https://lore.kernel.org/r/20210130022618.317351-1-saeed@kernel.org
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Jakub Kicinski 2021-02-01 18:50:12 -08:00
parent f222a99376 64f45c0fc4
commit 1a2b60f6f1
13 changed files with 2169 additions and 44 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/net/ethernet/mellanox/mlx5/core/Makefile
View File

@ -85,7 +85,7 @@ mlx5_core-$(CONFIG_MLX5_SW_STEERING) += steering/dr_domain.o steering/dr_table.o
steering/dr_matcher.o steering/dr_rule.o \
steering/dr_icm_pool.o steering/dr_buddy.o \
steering/dr_ste.o steering/dr_send.o \
steering/dr_ste_v0.o \
steering/dr_ste_v0.o steering/dr_ste_v1.o \
steering/dr_cmd.o steering/dr_fw.o \
steering/dr_action.o steering/fs_dr.o
#

17
drivers/net/ethernet/mellanox/mlx5/core/steering/dr_cmd.c
View File

@ -78,9 +78,9 @@ int mlx5dr_cmd_query_esw_caps(struct mlx5_core_dev *mdev,
caps->uplink_icm_address_tx =
MLX5_CAP64_ESW_FLOWTABLE(mdev,
sw_steering_uplink_icm_address_tx);
caps->sw_owner =
MLX5_CAP_ESW_FLOWTABLE_FDB(mdev,
sw_owner);
caps->sw_owner_v2 = MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, sw_owner_v2);
if (!caps->sw_owner_v2)
caps->sw_owner = MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, sw_owner);
return 0;
}
@ -113,10 +113,15 @@ int mlx5dr_cmd_query_device(struct mlx5_core_dev *mdev,
caps->nic_tx_allow_address =
MLX5_CAP64_FLOWTABLE(mdev, sw_steering_nic_tx_action_allow_icm_address);
caps->rx_sw_owner = MLX5_CAP_FLOWTABLE_NIC_RX(mdev, sw_owner);
caps->max_ft_level = MLX5_CAP_FLOWTABLE_NIC_RX(mdev, max_ft_level);
caps->rx_sw_owner_v2 = MLX5_CAP_FLOWTABLE_NIC_RX(mdev, sw_owner_v2);
caps->tx_sw_owner_v2 = MLX5_CAP_FLOWTABLE_NIC_TX(mdev, sw_owner_v2);
caps->tx_sw_owner = MLX5_CAP_FLOWTABLE_NIC_TX(mdev, sw_owner);
if (!caps->rx_sw_owner_v2)
caps->rx_sw_owner = MLX5_CAP_FLOWTABLE_NIC_RX(mdev, sw_owner);
if (!caps->tx_sw_owner_v2)
caps->tx_sw_owner = MLX5_CAP_FLOWTABLE_NIC_TX(mdev, sw_owner);
caps->max_ft_level = MLX5_CAP_FLOWTABLE_NIC_RX(mdev, max_ft_level);
caps->log_icm_size = MLX5_CAP_DEV_MEM(mdev, log_steering_sw_icm_size);
caps->hdr_modify_icm_addr =

17
drivers/net/ethernet/mellanox/mlx5/core/steering/dr_domain.c
View File

@ -4,6 +4,11 @@
#include <linux/mlx5/eswitch.h>
#include "dr_types.h"
#define DR_DOMAIN_SW_STEERING_SUPPORTED(dmn, dmn_type) \
((dmn)->info.caps.dmn_type##_sw_owner || \
((dmn)->info.caps.dmn_type##_sw_owner_v2 && \
(dmn)->info.caps.sw_format_ver <= MLX5_STEERING_FORMAT_CONNECTX_6DX))
static int dr_domain_init_cache(struct mlx5dr_domain *dmn)
{
/* Per vport cached FW FT for checksum recalculation, this
@ -187,6 +192,7 @@ static int dr_domain_query_fdb_caps(struct mlx5_core_dev *mdev,
return ret;
dmn->info.caps.fdb_sw_owner = dmn->info.caps.esw_caps.sw_owner;
dmn->info.caps.fdb_sw_owner_v2 = dmn->info.caps.esw_caps.sw_owner_v2;
dmn->info.caps.esw_rx_drop_address = dmn->info.caps.esw_caps.drop_icm_address_rx;
dmn->info.caps.esw_tx_drop_address = dmn->info.caps.esw_caps.drop_icm_address_tx;
@ -229,18 +235,13 @@ static int dr_domain_caps_init(struct mlx5_core_dev *mdev,
if (ret)
return ret;
if (dmn->info.caps.sw_format_ver != MLX5_STEERING_FORMAT_CONNECTX_5) {
mlx5dr_err(dmn, "SW steering is not supported on this device\n");
return -EOPNOTSUPP;
}
ret = dr_domain_query_fdb_caps(mdev, dmn);
if (ret)
return ret;
switch (dmn->type) {
case MLX5DR_DOMAIN_TYPE_NIC_RX:
if (!dmn->info.caps.rx_sw_owner)
if (!DR_DOMAIN_SW_STEERING_SUPPORTED(dmn, rx))
return -ENOTSUPP;
dmn->info.supp_sw_steering = true;
@ -249,7 +250,7 @@ static int dr_domain_caps_init(struct mlx5_core_dev *mdev,
dmn->info.rx.drop_icm_addr = dmn->info.caps.nic_rx_drop_address;
break;
case MLX5DR_DOMAIN_TYPE_NIC_TX:
if (!dmn->info.caps.tx_sw_owner)
if (!DR_DOMAIN_SW_STEERING_SUPPORTED(dmn, tx))
return -ENOTSUPP;
dmn->info.supp_sw_steering = true;
@ -261,7 +262,7 @@ static int dr_domain_caps_init(struct mlx5_core_dev *mdev,
if (!dmn->info.caps.eswitch_manager)
return -ENOTSUPP;
if (!dmn->info.caps.fdb_sw_owner)
if (!DR_DOMAIN_SW_STEERING_SUPPORTED(dmn, fdb))
return -ENOTSUPP;
dmn->info.rx.ste_type = MLX5DR_STE_TYPE_RX;

12
drivers/net/ethernet/mellanox/mlx5/core/steering/dr_matcher.c
View File

@ -113,7 +113,8 @@ dr_mask_is_vxlan_gpe_set(struct mlx5dr_match_misc3 *misc3)
static bool
dr_matcher_supp_vxlan_gpe(struct mlx5dr_cmd_caps *caps)
{
return caps->flex_protocols & MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED;
return (caps->sw_format_ver == MLX5_STEERING_FORMAT_CONNECTX_6DX) ||
(caps->flex_protocols & MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED);
}
static bool
@ -135,7 +136,8 @@ static bool dr_mask_is_tnl_geneve_set(struct mlx5dr_match_misc *misc)
static bool
dr_matcher_supp_tnl_geneve(struct mlx5dr_cmd_caps *caps)
{
return caps->flex_protocols & MLX5_FLEX_PARSER_GENEVE_ENABLED;
return (caps->sw_format_ver == MLX5_STEERING_FORMAT_CONNECTX_6DX) ||
(caps->flex_protocols & MLX5_FLEX_PARSER_GENEVE_ENABLED);
}
static bool
@ -148,12 +150,14 @@ dr_mask_is_tnl_geneve(struct mlx5dr_match_param *mask,
static int dr_matcher_supp_icmp_v4(struct mlx5dr_cmd_caps *caps)
{
return caps->flex_protocols & MLX5_FLEX_PARSER_ICMP_V4_ENABLED;
return (caps->sw_format_ver == MLX5_STEERING_FORMAT_CONNECTX_6DX) ||
(caps->flex_protocols & MLX5_FLEX_PARSER_ICMP_V4_ENABLED);
}
static int dr_matcher_supp_icmp_v6(struct mlx5dr_cmd_caps *caps)
{
return caps->flex_protocols & MLX5_FLEX_PARSER_ICMP_V6_ENABLED;
return (caps->sw_format_ver == MLX5_STEERING_FORMAT_CONNECTX_6DX) ||
(caps->flex_protocols & MLX5_FLEX_PARSER_ICMP_V6_ENABLED);
}
static bool dr_mask_is_icmpv6_set(struct mlx5dr_match_misc3 *misc3)

17
drivers/net/ethernet/mellanox/mlx5/core/steering/dr_rule.c
View File

@ -30,7 +30,7 @@ static int dr_rule_append_to_miss_list(struct mlx5dr_ste_ctx *ste_ctx,
mlx5dr_ste_get_icm_addr(new_last_ste));
list_add_tail(&new_last_ste->miss_list_node, miss_list);
mlx5dr_send_fill_and_append_ste_send_info(last_ste, DR_STE_SIZE_REDUCED,
mlx5dr_send_fill_and_append_ste_send_info(last_ste, DR_STE_SIZE_CTRL,
0, last_ste->hw_ste,
ste_info_last, send_list, true);
@ -106,14 +106,19 @@ dr_rule_handle_one_ste_in_update_list(struct mlx5dr_ste_send_info *ste_info,
int ret;
list_del(&ste_info->send_list);
/* Copy data to ste, only reduced size or control, the last 16B (mask)
* is already written to the hw.
*/
if (ste_info->size == DR_STE_SIZE_CTRL)
memcpy(ste_info->ste->hw_ste, ste_info->data, DR_STE_SIZE_CTRL);
else
memcpy(ste_info->ste->hw_ste, ste_info->data, DR_STE_SIZE_REDUCED);
ret = mlx5dr_send_postsend_ste(dmn, ste_info->ste, ste_info->data,
ste_info->size, ste_info->offset);
if (ret)
goto out;
/* Copy data to ste, only reduced size, the last 16B (mask)
* is already written to the hw.
*/
memcpy(ste_info->ste->hw_ste, ste_info->data, DR_STE_SIZE_REDUCED);
out:
kfree(ste_info);
@ -456,7 +461,7 @@ dr_rule_rehash_htbl(struct mlx5dr_rule *rule,
ste_to_update = cur_htbl->pointing_ste;
}
mlx5dr_send_fill_and_append_ste_send_info(ste_to_update, DR_STE_SIZE_REDUCED,
mlx5dr_send_fill_and_append_ste_send_info(ste_to_update, DR_STE_SIZE_CTRL,
0, ste_to_update->hw_ste, ste_info,
update_list, false);

29
drivers/net/ethernet/mellanox/mlx5/core/steering/dr_send.c
View File

@ -431,6 +431,8 @@ int mlx5dr_send_postsend_ste(struct mlx5dr_domain *dmn, struct mlx5dr_ste *ste,
{
struct postsend_info send_info = {};
mlx5dr_ste_prepare_for_postsend(dmn->ste_ctx, data, size);
send_info.write.addr = (uintptr_t)data;
send_info.write.length = size;
send_info.write.lkey = 0;
@ -457,6 +459,8 @@ int mlx5dr_send_postsend_htbl(struct mlx5dr_domain *dmn,
if (ret)
return ret;
mlx5dr_ste_prepare_for_postsend(dmn->ste_ctx, formatted_ste, DR_STE_SIZE);
/* Send the data iteration times */
for (i = 0; i < iterations; i++) {
u32 ste_index = i * (byte_size / DR_STE_SIZE);
@ -480,6 +484,10 @@ int mlx5dr_send_postsend_htbl(struct mlx5dr_domain *dmn,
/* Copy bit_mask */
memcpy(data + ste_off + DR_STE_SIZE_REDUCED,
mask, DR_STE_SIZE_MASK);
/* Only when we have mask we need to re-arrange the STE */
mlx5dr_ste_prepare_for_postsend(dmn->ste_ctx,
data + (j * DR_STE_SIZE),
DR_STE_SIZE);
}
}
@ -509,6 +517,7 @@ int mlx5dr_send_postsend_formatted_htbl(struct mlx5dr_domain *dmn,
u32 byte_size = htbl->chunk->byte_size;
int iterations;
int num_stes;
u8 *copy_dst;
u8 *data;
int ret;
int i;
@ -518,20 +527,22 @@ int mlx5dr_send_postsend_formatted_htbl(struct mlx5dr_domain *dmn,
if (ret)
return ret;
for (i = 0; i < num_stes; i++) {
u8 *copy_dst;
/* Copy the same ste on the data buffer */
copy_dst = data + i * DR_STE_SIZE;
memcpy(copy_dst, ste_init_data, DR_STE_SIZE);
if (update_hw_ste) {
/* Copy the reduced ste to hash table ste_arr */
if (update_hw_ste) {
/* Copy the reduced STE to hash table ste_arr */
for (i = 0; i < num_stes; i++) {
copy_dst = htbl->hw_ste_arr + i * DR_STE_SIZE_REDUCED;
memcpy(copy_dst, ste_init_data, DR_STE_SIZE_REDUCED);
}
}
mlx5dr_ste_prepare_for_postsend(dmn->ste_ctx, ste_init_data, DR_STE_SIZE);
/* Copy the same STE on the data buffer */
for (i = 0; i < num_stes; i++) {
copy_dst = data + i * DR_STE_SIZE;
memcpy(copy_dst, ste_init_data, DR_STE_SIZE);
}
/* Send the data iteration times */
for (i = 0; i < iterations; i++) {
u8 ste_index = i * (byte_size / DR_STE_SIZE);

30
drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c
View File

@ -211,13 +211,17 @@ dr_ste_remove_head_ste(struct mlx5dr_ste_ctx *ste_ctx,
* |_ste_| --> |_next_ste_| -->|__| -->|__| -->/0
*/
static void
dr_ste_replace_head_ste(struct mlx5dr_ste *ste, struct mlx5dr_ste *next_ste,
dr_ste_replace_head_ste(struct mlx5dr_matcher_rx_tx *nic_matcher,
struct mlx5dr_ste *ste,
struct mlx5dr_ste *next_ste,
struct mlx5dr_ste_send_info *ste_info_head,
struct list_head *send_ste_list,
struct mlx5dr_ste_htbl *stats_tbl)
{
struct mlx5dr_ste_htbl *next_miss_htbl;
u8 hw_ste[DR_STE_SIZE] = {};
int sb_idx;
next_miss_htbl = next_ste->htbl;
@ -230,13 +234,19 @@ dr_ste_replace_head_ste(struct mlx5dr_ste *ste, struct mlx5dr_ste *next_ste,
/* Move data from next into ste */
dr_ste_replace(ste, next_ste);
/* Copy all 64 hw_ste bytes */
memcpy(hw_ste, ste->hw_ste, DR_STE_SIZE_REDUCED);
sb_idx = ste->ste_chain_location - 1;
mlx5dr_ste_set_bit_mask(hw_ste,
nic_matcher->ste_builder[sb_idx].bit_mask);
/* Del the htbl that contains the next_ste.
* The origin htbl stay with the same number of entries.
*/
mlx5dr_htbl_put(next_miss_htbl);
mlx5dr_send_fill_and_append_ste_send_info(ste, DR_STE_SIZE_REDUCED,
0, ste->hw_ste,
mlx5dr_send_fill_and_append_ste_send_info(ste, DR_STE_SIZE,
0, hw_ste,
ste_info_head,
send_ste_list,
true /* Copy data */);
@ -264,7 +274,7 @@ static void dr_ste_remove_middle_ste(struct mlx5dr_ste_ctx *ste_ctx,
miss_addr = ste_ctx->get_miss_addr(ste->hw_ste);
ste_ctx->set_miss_addr(prev_ste->hw_ste, miss_addr);
mlx5dr_send_fill_and_append_ste_send_info(prev_ste, DR_STE_SIZE_REDUCED, 0,
mlx5dr_send_fill_and_append_ste_send_info(prev_ste, DR_STE_SIZE_CTRL, 0,
prev_ste->hw_ste, ste_info,
send_ste_list, true /* Copy data*/);
@ -316,7 +326,8 @@ void mlx5dr_ste_free(struct mlx5dr_ste *ste,
stats_tbl);
} else {
/* First but not only entry in the list */
dr_ste_replace_head_ste(ste, next_ste, &ste_info_head,
dr_ste_replace_head_ste(nic_matcher, ste,
next_ste, &ste_info_head,
&send_ste_list, stats_tbl);
put_on_origin_table = false;
}
@ -356,6 +367,13 @@ void mlx5dr_ste_set_hit_addr_by_next_htbl(struct mlx5dr_ste_ctx *ste_ctx,
ste_ctx->set_hit_addr(hw_ste, chunk->icm_addr, chunk->num_of_entries);
}
void mlx5dr_ste_prepare_for_postsend(struct mlx5dr_ste_ctx *ste_ctx,
u8 *hw_ste_p, u32 ste_size)
{
if (ste_ctx->prepare_for_postsend)
ste_ctx->prepare_for_postsend(hw_ste_p, ste_size);
}
/* Init one ste as a pattern for ste data array */
void mlx5dr_ste_set_formatted_ste(struct mlx5dr_ste_ctx *ste_ctx,
u16 gvmi,
@ -1127,7 +1145,7 @@ void mlx5dr_ste_build_src_gvmi_qpn(struct mlx5dr_ste_ctx *ste_ctx,
static struct mlx5dr_ste_ctx *mlx5dr_ste_ctx_arr[] = {
[MLX5_STEERING_FORMAT_CONNECTX_5] = &ste_ctx_v0,
[MLX5_STEERING_FORMAT_CONNECTX_6DX] = NULL,
[MLX5_STEERING_FORMAT_CONNECTX_6DX] = &ste_ctx_v1,
};
struct mlx5dr_ste_ctx *mlx5dr_ste_get_ctx(u8 version)

4
drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.h
View File

@ -160,8 +160,12 @@ struct mlx5dr_ste_ctx {
u8 *hw_action,
u32 hw_action_sz,
u16 *used_hw_action_num);
/* Send */
void (*prepare_for_postsend)(u8 *hw_ste_p, u32 ste_size);
};
extern struct mlx5dr_ste_ctx ste_ctx_v0;
extern struct mlx5dr_ste_ctx ste_ctx_v1;
#endif /* _DR_STE_ */

4
drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste_v0.c
View File

@ -248,8 +248,8 @@ static void dr_ste_v0_set_miss_addr(u8 *hw_ste_p, u64 miss_addr)
static u64 dr_ste_v0_get_miss_addr(u8 *hw_ste_p)
{
u64 index =
(MLX5_GET(ste_rx_steering_mult, hw_ste_p, miss_address_31_6) |
MLX5_GET(ste_rx_steering_mult, hw_ste_p, miss_address_39_32) << 26);
((u64)MLX5_GET(ste_rx_steering_mult, hw_ste_p, miss_address_31_6) |
((u64)MLX5_GET(ste_rx_steering_mult, hw_ste_p, miss_address_39_32)) << 26);
return index << 6;
}

1633
drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste_v1.c Normal file
View File

File diff suppressed because it is too large Load Diff

9
drivers/net/ethernet/mellanox/mlx5/core/steering/dr_types.h
View File

@ -666,7 +666,8 @@ struct mlx5dr_esw_caps {
u64 drop_icm_address_tx;
u64 uplink_icm_address_rx;
u64 uplink_icm_address_tx;
bool sw_owner;
u8 sw_owner:1;
u8 sw_owner_v2:1;
};
struct mlx5dr_cmd_vport_cap {
@ -699,6 +700,9 @@ struct mlx5dr_cmd_caps {
bool rx_sw_owner;
bool tx_sw_owner;
bool fdb_sw_owner;
u8 rx_sw_owner_v2:1;
u8 tx_sw_owner_v2:1;
u8 fdb_sw_owner_v2:1;
u32 num_vports;
struct mlx5dr_esw_caps esw_caps;
struct mlx5dr_cmd_vport_cap *vports_caps;
@ -1072,6 +1076,9 @@ struct mlx5dr_icm_chunk *
mlx5dr_icm_alloc_chunk(struct mlx5dr_icm_pool *pool,
enum mlx5dr_icm_chunk_size chunk_size);
void mlx5dr_icm_free_chunk(struct mlx5dr_icm_chunk *chunk);
void mlx5dr_ste_prepare_for_postsend(struct mlx5dr_ste_ctx *ste_ctx,
u8 *hw_ste_p, u32 ste_size);
int mlx5dr_ste_htbl_init_and_postsend(struct mlx5dr_domain *dmn,
struct mlx5dr_domain_rx_tx *nic_dmn,
struct mlx5dr_ste_htbl *htbl,

434
drivers/net/ethernet/mellanox/mlx5/core/steering/mlx5_ifc_dr_ste_v1.h Normal file
View File

@ -0,0 +1,434 @@
/* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */
/* Copyright (c) 2020 NVIDIA CORPORATION. All rights reserved. */
#ifndef MLX5_IFC_DR_STE_V1_H
#define MLX5_IFC_DR_STE_V1_H
enum mlx5_ifc_ste_v1_modify_hdr_offset {
MLX5_MODIFY_HEADER_V1_QW_OFFSET = 0x20,
};
struct mlx5_ifc_ste_single_action_flow_tag_v1_bits {
u8 action_id[0x8];
u8 flow_tag[0x18];
};
struct mlx5_ifc_ste_single_action_modify_list_v1_bits {
u8 action_id[0x8];
u8 num_of_modify_actions[0x8];
u8 modify_actions_ptr[0x10];
};
struct mlx5_ifc_ste_single_action_remove_header_v1_bits {
u8 action_id[0x8];
u8 reserved_at_8[0x2];
u8 start_anchor[0x6];
u8 reserved_at_10[0x2];
u8 end_anchor[0x6];
u8 reserved_at_18[0x4];
u8 decap[0x1];
u8 vni_to_cqe[0x1];
u8 qos_profile[0x2];
};
struct mlx5_ifc_ste_single_action_remove_header_size_v1_bits {
u8 action_id[0x8];
u8 reserved_at_8[0x2];
u8 start_anchor[0x6];
u8 outer_l4_remove[0x1];
u8 reserved_at_11[0x1];
u8 start_offset[0x7];
u8 reserved_at_18[0x1];
u8 remove_size[0x6];
};
struct mlx5_ifc_ste_double_action_copy_v1_bits {
u8 action_id[0x8];
u8 destination_dw_offset[0x8];
u8 reserved_at_10[0x2];
u8 destination_left_shifter[0x6];
u8 reserved_at_17[0x2];
u8 destination_length[0x6];
u8 reserved_at_20[0x8];
u8 source_dw_offset[0x8];
u8 reserved_at_30[0x2];
u8 source_right_shifter[0x6];
u8 reserved_at_38[0x8];
};
struct mlx5_ifc_ste_double_action_set_v1_bits {
u8 action_id[0x8];
u8 destination_dw_offset[0x8];
u8 reserved_at_10[0x2];
u8 destination_left_shifter[0x6];
u8 reserved_at_18[0x2];
u8 destination_length[0x6];
u8 inline_data[0x20];
};
struct mlx5_ifc_ste_double_action_add_v1_bits {
u8 action_id[0x8];
u8 destination_dw_offset[0x8];
u8 reserved_at_10[0x2];
u8 destination_left_shifter[0x6];
u8 reserved_at_18[0x2];
u8 destination_length[0x6];
u8 add_value[0x20];
};
struct mlx5_ifc_ste_double_action_insert_with_inline_v1_bits {
u8 action_id[0x8];
u8 reserved_at_8[0x2];
u8 start_anchor[0x6];
u8 start_offset[0x7];
u8 reserved_at_17[0x9];
u8 inline_data[0x20];
};
struct mlx5_ifc_ste_double_action_insert_with_ptr_v1_bits {
u8 action_id[0x8];
u8 reserved_at_8[0x2];
u8 start_anchor[0x6];
u8 start_offset[0x7];
u8 size[0x6];
u8 attributes[0x3];
u8 pointer[0x20];
};
struct mlx5_ifc_ste_double_action_modify_action_list_v1_bits {
u8 action_id[0x8];
u8 modify_actions_pattern_pointer[0x18];
u8 number_of_modify_actions[0x8];
u8 modify_actions_argument_pointer[0x18];
};
struct mlx5_ifc_ste_match_bwc_v1_bits {
u8 entry_format[0x8];
u8 counter_id[0x18];
u8 miss_address_63_48[0x10];
u8 match_definer_ctx_idx[0x8];
u8 miss_address_39_32[0x8];
u8 miss_address_31_6[0x1a];
u8 reserved_at_5a[0x1];
u8 match_polarity[0x1];
u8 reparse[0x1];
u8 reserved_at_5d[0x3];
u8 next_table_base_63_48[0x10];
u8 hash_definer_ctx_idx[0x8];
u8 next_table_base_39_32_size[0x8];
u8 next_table_base_31_5_size[0x1b];
u8 hash_type[0x2];
u8 hash_after_actions[0x1];
u8 reserved_at_9e[0x2];
u8 byte_mask[0x10];
u8 next_entry_format[0x1];
u8 mask_mode[0x1];
u8 gvmi[0xe];
u8 action[0x40];
};
struct mlx5_ifc_ste_mask_and_match_v1_bits {
u8 entry_format[0x8];
u8 counter_id[0x18];
u8 miss_address_63_48[0x10];
u8 match_definer_ctx_idx[0x8];
u8 miss_address_39_32[0x8];
u8 miss_address_31_6[0x1a];
u8 reserved_at_5a[0x1];
u8 match_polarity[0x1];
u8 reparse[0x1];
u8 reserved_at_5d[0x3];
u8 next_table_base_63_48[0x10];
u8 hash_definer_ctx_idx[0x8];
u8 next_table_base_39_32_size[0x8];
u8 next_table_base_31_5_size[0x1b];
u8 hash_type[0x2];
u8 hash_after_actions[0x1];
u8 reserved_at_9e[0x2];
u8 action[0x60];
};
struct mlx5_ifc_ste_eth_l2_src_v1_bits {
u8 reserved_at_0[0x1];
u8 sx_sniffer[0x1];
u8 functional_loopback[0x1];
u8 ip_fragmented[0x1];
u8 qp_type[0x2];
u8 encapsulation_type[0x2];
u8 port[0x2];
u8 l3_type[0x2];
u8 l4_type[0x2];
u8 first_vlan_qualifier[0x2];
u8 first_priority[0x3];
u8 first_cfi[0x1];
u8 first_vlan_id[0xc];
u8 smac_47_16[0x20];
u8 smac_15_0[0x10];
u8 l3_ethertype[0x10];
u8 reserved_at_60[0x6];
u8 tcp_syn[0x1];
u8 reserved_at_67[0x3];
u8 force_loopback[0x1];
u8 l2_ok[0x1];
u8 l3_ok[0x1];
u8 l4_ok[0x1];
u8 second_vlan_qualifier[0x2];
u8 second_priority[0x3];
u8 second_cfi[0x1];
u8 second_vlan_id[0xc];
};
struct mlx5_ifc_ste_eth_l2_dst_v1_bits {
u8 reserved_at_0[0x1];
u8 sx_sniffer[0x1];
u8 functional_lb[0x1];
u8 ip_fragmented[0x1];
u8 qp_type[0x2];
u8 encapsulation_type[0x2];
u8 port[0x2];
u8 l3_type[0x2];
u8 l4_type[0x2];
u8 first_vlan_qualifier[0x2];
u8 first_priority[0x3];
u8 first_cfi[0x1];
u8 first_vlan_id[0xc];
u8 dmac_47_16[0x20];
u8 dmac_15_0[0x10];
u8 l3_ethertype[0x10];
u8 reserved_at_60[0x6];
u8 tcp_syn[0x1];
u8 reserved_at_67[0x3];
u8 force_lb[0x1];
u8 l2_ok[0x1];
u8 l3_ok[0x1];
u8 l4_ok[0x1];
u8 second_vlan_qualifier[0x2];
u8 second_priority[0x3];
u8 second_cfi[0x1];
u8 second_vlan_id[0xc];
};
struct mlx5_ifc_ste_eth_l2_src_dst_v1_bits {
u8 dmac_47_16[0x20];
u8 smac_47_16[0x20];
u8 dmac_15_0[0x10];
u8 reserved_at_50[0x2];
u8 functional_lb[0x1];
u8 reserved_at_53[0x5];
u8 port[0x2];
u8 l3_type[0x2];
u8 reserved_at_5c[0x2];
u8 first_vlan_qualifier[0x2];
u8 first_priority[0x3];
u8 first_cfi[0x1];
u8 first_vlan_id[0xc];
u8 smac_15_0[0x10];
};
struct mlx5_ifc_ste_eth_l3_ipv4_5_tuple_v1_bits {
u8 source_address[0x20];
u8 destination_address[0x20];
u8 source_port[0x10];
u8 destination_port[0x10];
u8 reserved_at_60[0x4];
u8 l4_ok[0x1];
u8 l3_ok[0x1];
u8 fragmented[0x1];
u8 tcp_ns[0x1];
u8 tcp_cwr[0x1];
u8 tcp_ece[0x1];
u8 tcp_urg[0x1];
u8 tcp_ack[0x1];
u8 tcp_psh[0x1];
u8 tcp_rst[0x1];
u8 tcp_syn[0x1];
u8 tcp_fin[0x1];
u8 dscp[0x6];
u8 ecn[0x2];
u8 protocol[0x8];
};
struct mlx5_ifc_ste_eth_l2_tnl_v1_bits {
u8 l2_tunneling_network_id[0x20];
u8 dmac_47_16[0x20];
u8 dmac_15_0[0x10];
u8 l3_ethertype[0x10];
u8 reserved_at_60[0x3];
u8 ip_fragmented[0x1];
u8 reserved_at_64[0x2];
u8 encp_type[0x2];
u8 reserved_at_68[0x2];
u8 l3_type[0x2];
u8 l4_type[0x2];
u8 first_vlan_qualifier[0x2];
u8 first_priority[0x3];
u8 first_cfi[0x1];
u8 first_vlan_id[0xc];
};
struct mlx5_ifc_ste_eth_l3_ipv4_misc_v1_bits {
u8 identification[0x10];
u8 flags[0x3];
u8 fragment_offset[0xd];
u8 total_length[0x10];
u8 checksum[0x10];
u8 version[0x4];
u8 ihl[0x4];
u8 time_to_live[0x8];
u8 reserved_at_50[0x10];
u8 reserved_at_60[0x1c];
u8 voq_internal_prio[0x4];
};
struct mlx5_ifc_ste_eth_l4_v1_bits {
u8 ipv6_version[0x4];
u8 reserved_at_4[0x4];
u8 dscp[0x6];
u8 ecn[0x2];
u8 ipv6_hop_limit[0x8];
u8 protocol[0x8];
u8 src_port[0x10];
u8 dst_port[0x10];
u8 first_fragment[0x1];
u8 reserved_at_41[0xb];
u8 flow_label[0x14];
u8 tcp_data_offset[0x4];
u8 l4_ok[0x1];
u8 l3_ok[0x1];
u8 fragmented[0x1];
u8 tcp_ns[0x1];
u8 tcp_cwr[0x1];
u8 tcp_ece[0x1];
u8 tcp_urg[0x1];
u8 tcp_ack[0x1];
u8 tcp_psh[0x1];
u8 tcp_rst[0x1];
u8 tcp_syn[0x1];
u8 tcp_fin[0x1];
u8 ipv6_paylen[0x10];
};
struct mlx5_ifc_ste_eth_l4_misc_v1_bits {
u8 window_size[0x10];
u8 urgent_pointer[0x10];
u8 ack_num[0x20];
u8 seq_num[0x20];
u8 length[0x10];
u8 checksum[0x10];
};
struct mlx5_ifc_ste_mpls_v1_bits {
u8 reserved_at_0[0x15];
u8 mpls_ok[0x1];
u8 mpls4_s_bit[0x1];
u8 mpls4_qualifier[0x1];
u8 mpls3_s_bit[0x1];
u8 mpls3_qualifier[0x1];
u8 mpls2_s_bit[0x1];
u8 mpls2_qualifier[0x1];
u8 mpls1_s_bit[0x1];
u8 mpls1_qualifier[0x1];
u8 mpls0_s_bit[0x1];
u8 mpls0_qualifier[0x1];
u8 mpls0_label[0x14];
u8 mpls0_exp[0x3];
u8 mpls0_s_bos[0x1];
u8 mpls0_ttl[0x8];
u8 mpls1_label[0x20];
u8 mpls2_label[0x20];
};
struct mlx5_ifc_ste_gre_v1_bits {
u8 gre_c_present[0x1];
u8 reserved_at_1[0x1];
u8 gre_k_present[0x1];
u8 gre_s_present[0x1];
u8 strict_src_route[0x1];
u8 recur[0x3];
u8 flags[0x5];
u8 version[0x3];
u8 gre_protocol[0x10];
u8 reserved_at_20[0x20];
u8 gre_key_h[0x18];
u8 gre_key_l[0x8];
u8 reserved_at_60[0x20];
};
struct mlx5_ifc_ste_src_gvmi_qp_v1_bits {
u8 loopback_synd[0x8];
u8 reserved_at_8[0x7];
u8 functional_lb[0x1];
u8 source_gvmi[0x10];
u8 force_lb[0x1];
u8 reserved_at_21[0x1];
u8 source_is_requestor[0x1];
u8 reserved_at_23[0x5];
u8 source_qp[0x18];
u8 reserved_at_40[0x20];
u8 reserved_at_60[0x20];
};
struct mlx5_ifc_ste_icmp_v1_bits {
u8 icmp_payload_data[0x20];
u8 icmp_header_data[0x20];
u8 icmp_type[0x8];
u8 icmp_code[0x8];
u8 reserved_at_50[0x10];
u8 reserved_at_60[0x20];
};
#endif /* MLX5_IFC_DR_STE_V1_H */

5
drivers/net/ethernet/mellanox/mlx5/core/steering/mlx5dr.h
View File

@ -124,7 +124,10 @@ int mlx5dr_action_destroy(struct mlx5dr_action *action);
static inline bool
mlx5dr_is_supported(struct mlx5_core_dev *dev)
{
return MLX5_CAP_ESW_FLOWTABLE_FDB(dev, sw_owner);
return MLX5_CAP_ESW_FLOWTABLE_FDB(dev, sw_owner) ||
(MLX5_CAP_ESW_FLOWTABLE_FDB(dev, sw_owner_v2) &&
(MLX5_CAP_GEN(dev, steering_format_version) <=
MLX5_STEERING_FORMAT_CONNECTX_6DX));
}
/* buddy functions & structure */