arm64: Remove pgprot_dmacoherent()
Since this macro is identical to pgprot_writecombine() and is only used in a single place, remove it completely to avoid confusion. On ARMv7+ processors, the coherent DMA mapping must be Normal NonCacheable (a.k.a. writecombine) to avoid mismatched hardware attribute aliases (with the kernel linear mapping as Normal Cacheable). Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
This commit is contained in:
parent
214fdbe74a
commit
196adf2f30
|
@ -280,8 +280,6 @@ static inline int has_transparent_hugepage(void)
|
|||
__pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRnE) | PTE_PXN | PTE_UXN)
|
||||
#define pgprot_writecombine(prot) \
|
||||
__pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN)
|
||||
#define pgprot_dmacoherent(prot) \
|
||||
__pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN)
|
||||
#define __HAVE_PHYS_MEM_ACCESS_PROT
|
||||
struct file;
|
||||
extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
|
||||
|
|
|
@ -33,10 +33,8 @@ EXPORT_SYMBOL(dma_ops);
|
|||
static pgprot_t __get_dma_pgprot(struct dma_attrs *attrs, pgprot_t prot,
|
||||
bool coherent)
|
||||
{
|
||||
if (dma_get_attr(DMA_ATTR_WRITE_COMBINE, attrs))
|
||||
if (!coherent || dma_get_attr(DMA_ATTR_WRITE_COMBINE, attrs))
|
||||
return pgprot_writecombine(prot);
|
||||
else if (!coherent)
|
||||
return pgprot_dmacoherent(prot);
|
||||
return prot;
|
||||
}
|
||||
|
||||
|
|
Loading…
Reference in New Issue