pch_dma: Support I2S for ML7213 IOH
Support I2S device for ML7213 IOH Signed-off-by: Tomoya MORINAGA <tomoya-linux@dsn.okisemi.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
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60092d0bde
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@ -77,10 +77,10 @@ struct pch_dma_regs {
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u32 dma_ctl0;
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u32 dma_ctl1;
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u32 dma_ctl2;
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u32 reserved1;
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u32 dma_ctl3;
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u32 dma_sts0;
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u32 dma_sts1;
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u32 reserved2;
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u32 dma_sts2;
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u32 reserved3;
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struct pch_dma_desc_regs desc[MAX_CHAN_NR];
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};
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@ -130,6 +130,7 @@ struct pch_dma {
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#define PCH_DMA_CTL0 0x00
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#define PCH_DMA_CTL1 0x04
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#define PCH_DMA_CTL2 0x08
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#define PCH_DMA_CTL3 0x0C
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#define PCH_DMA_STS0 0x10
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#define PCH_DMA_STS1 0x14
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@ -202,16 +203,30 @@ static void pdc_set_dir(struct dma_chan *chan)
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struct pch_dma *pd = to_pd(chan->device);
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u32 val;
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val = dma_readl(pd, CTL0);
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if (chan->chan_id < 8) {
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val = dma_readl(pd, CTL0);
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if (pd_chan->dir == DMA_TO_DEVICE)
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val |= 0x1 << (DMA_CTL0_BITS_PER_CH * chan->chan_id +
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DMA_CTL0_DIR_SHIFT_BITS);
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else
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val &= ~(0x1 << (DMA_CTL0_BITS_PER_CH * chan->chan_id +
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DMA_CTL0_DIR_SHIFT_BITS));
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if (pd_chan->dir == DMA_TO_DEVICE)
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val |= 0x1 << (DMA_CTL0_BITS_PER_CH * chan->chan_id +
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DMA_CTL0_DIR_SHIFT_BITS);
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else
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val &= ~(0x1 << (DMA_CTL0_BITS_PER_CH * chan->chan_id +
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DMA_CTL0_DIR_SHIFT_BITS));
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dma_writel(pd, CTL0, val);
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dma_writel(pd, CTL0, val);
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} else {
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int ch = chan->chan_id - 8; /* ch8-->0 ch9-->1 ... ch11->3 */
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val = dma_readl(pd, CTL3);
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if (pd_chan->dir == DMA_TO_DEVICE)
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val |= 0x1 << (DMA_CTL0_BITS_PER_CH * ch +
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DMA_CTL0_DIR_SHIFT_BITS);
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else
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val &= ~(0x1 << (DMA_CTL0_BITS_PER_CH * ch +
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DMA_CTL0_DIR_SHIFT_BITS));
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dma_writel(pd, CTL3, val);
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}
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dev_dbg(chan2dev(chan), "pdc_set_dir: chan %d -> %x\n",
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chan->chan_id, val);
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@ -222,13 +237,26 @@ static void pdc_set_mode(struct dma_chan *chan, u32 mode)
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struct pch_dma *pd = to_pd(chan->device);
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u32 val;
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val = dma_readl(pd, CTL0);
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if (chan->chan_id < 8) {
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val = dma_readl(pd, CTL0);
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val &= ~(DMA_CTL0_MODE_MASK_BITS <<
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(DMA_CTL0_BITS_PER_CH * chan->chan_id));
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val |= mode << (DMA_CTL0_BITS_PER_CH * chan->chan_id);
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val &= ~(DMA_CTL0_MODE_MASK_BITS <<
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(DMA_CTL0_BITS_PER_CH * chan->chan_id));
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val |= mode << (DMA_CTL0_BITS_PER_CH * chan->chan_id);
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dma_writel(pd, CTL0, val);
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dma_writel(pd, CTL0, val);
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} else {
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int ch = chan->chan_id - 8; /* ch8-->0 ch9-->1 ... ch11->3 */
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val = dma_readl(pd, CTL3);
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val &= ~(DMA_CTL0_MODE_MASK_BITS <<
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(DMA_CTL0_BITS_PER_CH * ch));
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val |= mode << (DMA_CTL0_BITS_PER_CH * ch);
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dma_writel(pd, CTL3, val);
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}
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dev_dbg(chan2dev(chan), "pdc_set_mode: chan %d -> %x\n",
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chan->chan_id, val);
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@ -701,6 +729,7 @@ static void pch_dma_save_regs(struct pch_dma *pd)
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pd->regs.dma_ctl0 = dma_readl(pd, CTL0);
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pd->regs.dma_ctl1 = dma_readl(pd, CTL1);
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pd->regs.dma_ctl2 = dma_readl(pd, CTL2);
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pd->regs.dma_ctl3 = dma_readl(pd, CTL3);
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list_for_each_entry_safe(chan, _c, &pd->dma.channels, device_node) {
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pd_chan = to_pd_chan(chan);
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@ -723,6 +752,7 @@ static void pch_dma_restore_regs(struct pch_dma *pd)
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dma_writel(pd, CTL0, pd->regs.dma_ctl0);
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dma_writel(pd, CTL1, pd->regs.dma_ctl1);
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dma_writel(pd, CTL2, pd->regs.dma_ctl2);
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dma_writel(pd, CTL3, pd->regs.dma_ctl3);
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list_for_each_entry_safe(chan, _c, &pd->dma.channels, device_node) {
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pd_chan = to_pd_chan(chan);
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@ -925,6 +955,7 @@ static void __devexit pch_dma_remove(struct pci_dev *pdev)
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#define PCI_DEVICE_ID_ML7213_DMA1_8CH 0x8026
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#define PCI_DEVICE_ID_ML7213_DMA2_8CH 0x802B
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#define PCI_DEVICE_ID_ML7213_DMA3_4CH 0x8034
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#define PCI_DEVICE_ID_ML7213_DMA4_12CH 0x8032
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static const struct pci_device_id pch_dma_id_table[] = {
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{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_EG20T_PCH_DMA_8CH), 8 },
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@ -932,6 +963,7 @@ static const struct pci_device_id pch_dma_id_table[] = {
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{ PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7213_DMA1_8CH), 8}, /* UART Video */
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{ PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7213_DMA2_8CH), 8}, /* PCMIF SPI */
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{ PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7213_DMA3_4CH), 4}, /* FPGA */
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{ PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7213_DMA4_12CH), 12}, /* I2S */
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{ 0, },
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};
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