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gma500: Final polish 

This completes the clean up all the non Medfield C files to the point where
checkpatch approves of them barring some silly 80 column whining.

The Medfield stuff is still in a lot of flux but the rest is now ready for
general tidy and review.

Signed-off-by: Alan Cox <alan@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
This commit is contained in:
Alan Cox 2011-07-11 19:39:43 +01:00 committed by Greg Kroah-Hartman
parent 78f23926df
commit 18a4ca2a11
5 changed files with 14 additions and 14 deletions

8
drivers/staging/gma500/framebuffer.c
View File

@ -756,10 +756,10 @@ static void psb_setup_outputs(struct drm_device *dev)
clone_mask = (1 << INTEL_OUTPUT_MIPI2); clone_mask = (1 << INTEL_OUTPUT_MIPI2);
break; break;
case INTEL_OUTPUT_HDMI: case INTEL_OUTPUT_HDMI:
if (IS_MFLD(dev)) if (IS_MFLD(dev))
crtc_mask = (1 << 1); crtc_mask = (1 << 1);
else /* FIXME: review Oaktrail */ else /* FIXME: review Oaktrail */
crtc_mask = (1 << 0); /* Cedarview */ crtc_mask = (1 << 0); /* Cedarview */
clone_mask = (1 << INTEL_OUTPUT_HDMI); clone_mask = (1 << INTEL_OUTPUT_HDMI);
break; break;
} }

2
drivers/staging/gma500/gtt.c
View File

@ -398,7 +398,7 @@ int psb_gtt_init(struct drm_device *dev, int resume)
dev_priv->gtt_initialized = 1; dev_priv->gtt_initialized = 1;
pg->gtt_phys_start = dev_priv->pge_ctl & PAGE_MASK; pg->gtt_phys_start = dev_priv->pge_ctl & PAGE_MASK;
/* /*
* FIXME: video mmu has hw bug to access 0x0D0000000, * FIXME: video mmu has hw bug to access 0x0D0000000,
* then make gatt start at 0x0e000,0000 * then make gatt start at 0x0e000,0000

2
drivers/staging/gma500/psb_device.c
View File

@ -347,6 +347,6 @@ const struct psb_ops psb_chip_ops = {
.save_regs = psb_save_display_registers, .save_regs = psb_save_display_registers,
.restore_regs = psb_restore_display_registers, .restore_regs = psb_restore_display_registers,
.power_down = psb_power_down, .power_down = psb_power_down,
.power_up = psb_power_up, .power_up = psb_power_up,
}; };

8
drivers/staging/gma500/psb_drv.c
View File

@ -52,7 +52,7 @@ module_param_named(trap_pagefaults, drm_psb_trap_pagefaults, int, 0600);
static DEFINE_PCI_DEVICE_TABLE(pciidlist) = { static DEFINE_PCI_DEVICE_TABLE(pciidlist) = {
{ 0x8086, 0x8108, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &psb_chip_ops }, { 0x8086, 0x8108, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &psb_chip_ops },
{ 0x8086, 0x8109, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &psb_chip_ops }, { 0x8086, 0x8109, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &psb_chip_ops },
#if defined(CONFIG_DRM_PSB_MRST) #if defined(CONFIG_DRM_PSB_MRST)
{ 0x8086, 0x4100, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &mrst_chip_ops}, { 0x8086, 0x4100, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &mrst_chip_ops},
{ 0x8086, 0x4101, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &mrst_chip_ops}, { 0x8086, 0x4101, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &mrst_chip_ops},
{ 0x8086, 0x4102, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &mrst_chip_ops}, { 0x8086, 0x4102, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &mrst_chip_ops},
@ -72,7 +72,7 @@ static DEFINE_PCI_DEVICE_TABLE(pciidlist) = {
{ 0x8086, 0x0136, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &mdfld_chip_ops}, { 0x8086, 0x0136, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &mdfld_chip_ops},
{ 0x8086, 0x0137, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &mdfld_chip_ops}, { 0x8086, 0x0137, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &mdfld_chip_ops},
#endif #endif
#if defined(CONFIG_DRM_PSB_CDV) #if defined(CONFIG_DRM_PSB_CDV)
{ 0x8086, 0x0be0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &cdv_chip_ops}, { 0x8086, 0x0be0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &cdv_chip_ops},
{ 0x8086, 0x0be1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &cdv_chip_ops}, { 0x8086, 0x0be1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &cdv_chip_ops},
{ 0x8086, 0x0be2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &cdv_chip_ops}, { 0x8086, 0x0be2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &cdv_chip_ops},
@ -81,7 +81,7 @@ static DEFINE_PCI_DEVICE_TABLE(pciidlist) = {
{ 0x8086, 0x0be5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &cdv_chip_ops}, { 0x8086, 0x0be5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &cdv_chip_ops},
{ 0x8086, 0x0be6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &cdv_chip_ops}, { 0x8086, 0x0be6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &cdv_chip_ops},
{ 0x8086, 0x0be7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &cdv_chip_ops}, { 0x8086, 0x0be7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &cdv_chip_ops},
#endif #endif
{ 0, 0, 0} { 0, 0, 0}
}; };
MODULE_DEVICE_TABLE(pci, pciidlist); MODULE_DEVICE_TABLE(pci, pciidlist);
@ -409,7 +409,7 @@ static int psb_driver_load(struct drm_device *dev, unsigned long chipset)
#ifdef CONFIG_MDFLD_DSI_DPU #ifdef CONFIG_MDFLD_DSI_DPU
/*init dpu info*/ /*init dpu info*/
mdfld_dbi_dpu_init(dev); mdfld_dbi_dpu_init(dev);
#else #else
mdfld_dbi_dsr_init(dev); mdfld_dbi_dsr_init(dev);
#endif /*CONFIG_MDFLD_DSI_DPU*/ #endif /*CONFIG_MDFLD_DSI_DPU*/
/* INIT_WORK(&dev_priv->te_work, mdfld_te_handler_work);*/ /* INIT_WORK(&dev_priv->te_work, mdfld_te_handler_work);*/

8
drivers/staging/gma500/psb_intel_display.c
View File

@ -1284,9 +1284,9 @@ const struct drm_crtc_funcs psb_intel_crtc_funcs = {
*/ */
static void psb_intel_cursor_init(struct drm_device *dev, int pipe) static void psb_intel_cursor_init(struct drm_device *dev, int pipe)
{ {
u32 control[3] = { CURACNTR, CURBCNTR, CURCCNTR }; u32 control[3] = { CURACNTR, CURBCNTR, CURCCNTR };
u32 base[3] = { CURABASE, CURBBASE, CURCBASE }; u32 base[3] = { CURABASE, CURBBASE, CURCBASE };
REG_WRITE(control[pipe], 0); REG_WRITE(control[pipe], 0);
REG_WRITE(base[pipe], 0); REG_WRITE(base[pipe], 0);
} }
@ -1341,7 +1341,7 @@ void psb_intel_crtc_init(struct drm_device *dev, int pipe,
psb_intel_crtc->cursor_addr = 0; psb_intel_crtc->cursor_addr = 0;
drm_crtc_helper_add(&psb_intel_crtc->base, drm_crtc_helper_add(&psb_intel_crtc->base,
dev_priv->ops->crtc_helper); dev_priv->ops->crtc_helper);
/* Setup the array of drm_connector pointer array */ /* Setup the array of drm_connector pointer array */
psb_intel_crtc->mode_set.crtc = &psb_intel_crtc->base; psb_intel_crtc->mode_set.crtc = &psb_intel_crtc->base;