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Reset controller fixes for v4.14 

- Remove misleading HSDK v1 suffix, as there is no v2 planned
 - Add missing DT binding documentation for HSDK reset driver
 - Fix HSDK reset driver dependencies
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Merge tag 'reset-fixes-for-4.14' of git://git.pengutronix.de/git/pza/linux into fixes

Reset controller fixes for v4.14

- Remove misleading HSDK v1 suffix, as there is no v2 planned
- Add missing DT binding documentation for HSDK reset driver
- Fix HSDK reset driver dependencies

* tag 'reset-fixes-for-4.14' of git://git.pengutronix.de/git/pza/linux:
  reset: Restrict RESET_HSDK to ARC_SOC_HSDK or COMPILE_TEST
  ARC: reset: remove the misleading v1 suffix all over
  ARC: reset: add missing DT binding documentation for HSDKv1 reset driver
  ARC: reset: Only build on archs that have IOMEM

Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson 2017-10-03 18:10:12 -07:00
parent 5f3daa2393 544e3bf4f0
commit 180eb4f17e
7 changed files with 76 additions and 47 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

28
Documentation/devicetree/bindings/reset/snps,hsdk-reset.txt Normal file
View File

@ -0,0 +1,28 @@
Binding for the Synopsys HSDK reset controller
This binding uses the common reset binding[1].
[1] Documentation/devicetree/bindings/reset/reset.txt
Required properties:
- compatible: should be "snps,hsdk-reset".
- reg: should always contain 2 pairs address - length: first for reset
configuration register and second for corresponding SW reset and status bits
register.
- #reset-cells: from common reset binding; Should always be set to 1.
Example:
reset: reset@880 {
compatible = "snps,hsdk-reset";
#reset-cells = <1>;
reg = <0x8A0 0x4>, <0xFF0 0x4>;
};
Specifying reset lines connected to IP modules:
ethernet@.... {
....
resets = <&reset HSDK_V1_ETH_RESET>;
....
};
The index could be found in <dt-bindings/reset/snps,hsdk-reset.h>

6
MAINTAINERS
View File

@ -12931,9 +12931,9 @@ F: drivers/mmc/host/dw_mmc*
SYNOPSYS HSDK RESET CONTROLLER DRIVER
M: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
S: Supported
F: drivers/reset/reset-hsdk-v1.c
F: include/dt-bindings/reset/snps,hsdk-v1-reset.h
F: Documentation/devicetree/bindings/reset/snps,hsdk-v1-reset.txt
F: drivers/reset/reset-hsdk.c
F: include/dt-bindings/reset/snps,hsdk-reset.h
F: Documentation/devicetree/bindings/reset/snps,hsdk-reset.txt
SYSTEM CONFIGURATION (SYSCON)
M: Lee Jones <lee.jones@linaro.org>

9
drivers/reset/Kconfig
View File

@ -34,11 +34,12 @@ config RESET_BERLIN
help
This enables the reset controller driver for Marvell Berlin SoCs.
config RESET_HSDK_V1
bool "HSDK v1 Reset Driver"
default n
config RESET_HSDK
bool "Synopsys HSDK Reset Driver"
depends on HAS_IOMEM
depends on ARC_SOC_HSDK || COMPILE_TEST
help
This enables the reset controller driver for HSDK v1.
This enables the reset controller driver for HSDK board.
config RESET_IMX7
bool "i.MX7 Reset Driver" if COMPILE_TEST

2
drivers/reset/Makefile
View File

@ -5,7 +5,7 @@ obj-$(CONFIG_ARCH_TEGRA) += tegra/
obj-$(CONFIG_RESET_A10SR) += reset-a10sr.o
obj-$(CONFIG_RESET_ATH79) += reset-ath79.o
obj-$(CONFIG_RESET_BERLIN) += reset-berlin.o
obj-$(CONFIG_RESET_HSDK_V1) += reset-hsdk-v1.o
obj-$(CONFIG_RESET_HSDK) += reset-hsdk.o
obj-$(CONFIG_RESET_IMX7) += reset-imx7.o
obj-$(CONFIG_RESET_LANTIQ) += reset-lantiq.o
obj-$(CONFIG_RESET_LPC18XX) += reset-lpc18xx.o

44
drivers/reset/reset-hsdk-v1.c → drivers/reset/reset-hsdk.c
View File

@ -1,7 +1,7 @@
/*
* Copyright (C) 2017 Synopsys.
*
* Synopsys HSDKv1 SDP reset driver.
* Synopsys HSDK Development platform reset driver.
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
@ -18,9 +18,9 @@
#include <linux/slab.h>
#include <linux/types.h>
#define to_hsdkv1_rst(p) container_of((p), struct hsdkv1_rst, rcdev)
#define to_hsdk_rst(p) container_of((p), struct hsdk_rst, rcdev)
struct hsdkv1_rst {
struct hsdk_rst {
void __iomem *regs_ctl;
void __iomem *regs_rst;
spinlock_t lock;
@ -49,12 +49,12 @@ static const u32 rst_map[] = {
#define CGU_IP_SW_RESET_RESET BIT(0)
#define SW_RESET_TIMEOUT 10000
static void hsdkv1_reset_config(struct hsdkv1_rst *rst, unsigned long id)
static void hsdk_reset_config(struct hsdk_rst *rst, unsigned long id)
{
writel(rst_map[id], rst->regs_ctl + CGU_SYS_RST_CTRL);
}
static int hsdkv1_reset_do(struct hsdkv1_rst *rst)
static int hsdk_reset_do(struct hsdk_rst *rst)
{
u32 reg;
@ -69,28 +69,28 @@ static int hsdkv1_reset_do(struct hsdkv1_rst *rst)
!(reg & CGU_IP_SW_RESET_RESET), 5, SW_RESET_TIMEOUT);
}
static int hsdkv1_reset_reset(struct reset_controller_dev *rcdev,
static int hsdk_reset_reset(struct reset_controller_dev *rcdev,
unsigned long id)
{
struct hsdkv1_rst *rst = to_hsdkv1_rst(rcdev);
struct hsdk_rst *rst = to_hsdk_rst(rcdev);
unsigned long flags;
int ret;
spin_lock_irqsave(&rst->lock, flags);
hsdkv1_reset_config(rst, id);
ret = hsdkv1_reset_do(rst);
hsdk_reset_config(rst, id);
ret = hsdk_reset_do(rst);
spin_unlock_irqrestore(&rst->lock, flags);
return ret;
}
static const struct reset_control_ops hsdkv1_reset_ops = {
.reset = hsdkv1_reset_reset,
static const struct reset_control_ops hsdk_reset_ops = {
.reset = hsdk_reset_reset,
};
static int hsdkv1_reset_probe(struct platform_device *pdev)
static int hsdk_reset_probe(struct platform_device *pdev)
{
struct hsdkv1_rst *rst;
struct hsdk_rst *rst;
struct resource *mem;
rst = devm_kzalloc(&pdev->dev, sizeof(*rst), GFP_KERNEL);
@ -110,7 +110,7 @@ static int hsdkv1_reset_probe(struct platform_device *pdev)
spin_lock_init(&rst->lock);
rst->rcdev.owner = THIS_MODULE;
rst->rcdev.ops = &hsdkv1_reset_ops;
rst->rcdev.ops = &hsdk_reset_ops;
rst->rcdev.of_node = pdev->dev.of_node;
rst->rcdev.nr_resets = HSDK_MAX_RESETS;
rst->rcdev.of_reset_n_cells = 1;
@ -118,20 +118,20 @@ static int hsdkv1_reset_probe(struct platform_device *pdev)
return reset_controller_register(&rst->rcdev);
}
static const struct of_device_id hsdkv1_reset_dt_match[] = {
{ .compatible = "snps,hsdk-v1.0-reset" },
static const struct of_device_id hsdk_reset_dt_match[] = {
{ .compatible = "snps,hsdk-reset" },
{ },
};
static struct platform_driver hsdkv1_reset_driver = {
.probe = hsdkv1_reset_probe,
static struct platform_driver hsdk_reset_driver = {
.probe = hsdk_reset_probe,
.driver = {
.name = "hsdk-v1.0-reset",
.of_match_table = hsdkv1_reset_dt_match,
.name = "hsdk-reset",
.of_match_table = hsdk_reset_dt_match,
},
};
builtin_platform_driver(hsdkv1_reset_driver);
builtin_platform_driver(hsdk_reset_driver);
MODULE_AUTHOR("Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>");
MODULE_DESCRIPTION("Synopsys HSDKv1 SDP reset driver");
MODULE_DESCRIPTION("Synopsys HSDK SDP reset driver");
MODULE_LICENSE("GPL v2");

17
include/dt-bindings/reset/snps,hsdk-reset.h Normal file
View File

@ -0,0 +1,17 @@
/**
* This header provides index for the HSDK reset controller.
*/
#ifndef _DT_BINDINGS_RESET_CONTROLLER_SNPS_HSDK
#define _DT_BINDINGS_RESET_CONTROLLER_SNPS_HSDK
#define HSDK_APB_RESET 0
#define HSDK_AXI_RESET 1
#define HSDK_ETH_RESET 2
#define HSDK_USB_RESET 3
#define HSDK_SDIO_RESET 4
#define HSDK_HDMI_RESET 5
#define HSDK_GFX_RESET 6
#define HSDK_DMAC_RESET 7
#define HSDK_EBI_RESET 8
#endif /*_DT_BINDINGS_RESET_CONTROLLER_SNPS_HSDK*/

17
include/dt-bindings/reset/snps,hsdk-v1-reset.h
View File

@ -1,17 +0,0 @@
/**
* This header provides index for the HSDK v1 reset controller.
*/
#ifndef _DT_BINDINGS_RESET_CONTROLLER_HSDK_V1
#define _DT_BINDINGS_RESET_CONTROLLER_HSDK_V1
#define HSDK_V1_APB_RESET 0
#define HSDK_V1_AXI_RESET 1
#define HSDK_V1_ETH_RESET 2
#define HSDK_V1_USB_RESET 3
#define HSDK_V1_SDIO_RESET 4
#define HSDK_V1_HDMI_RESET 5
#define HSDK_V1_GFX_RESET 6
#define HSDK_V1_DMAC_RESET 7
#define HSDK_V1_EBI_RESET 8
#endif /*_DT_BINDINGS_RESET_CONTROLLER_HSDK_V1*/