Merge branch 'mv88e6060-fixes'
Neil Armstrong says: ==================== net: dsa: mv88e6060: cleanup and fix setup This patchset introduces some fixes and a registers addressing cleanup for the mv88e6060 DSA driver. The first patch removes the poll_link as mv88e6xxx. The 3 following patches fixes the setup in regards of the datasheet. The 2 last patches introduces a clean header and replaces all magic values. v2: cleanup InitReady patch, add missing Acked-by and fix header copyright notice ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller
commit
17c790a60d
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@ -15,9 +15,7 @@
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#include <linux/netdevice.h>
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#include <linux/phy.h>
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#include <net/dsa.h>
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#define REG_PORT(p) (8 + (p))
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#define REG_GLOBAL 0x0f
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#include "mv88e6060.h"
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static int reg_read(struct dsa_switch *ds, int addr, int reg)
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{
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@ -67,13 +65,14 @@ static char *mv88e6060_probe(struct device *host_dev, int sw_addr)
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if (bus == NULL)
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return NULL;
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ret = mdiobus_read(bus, sw_addr + REG_PORT(0), 0x03);
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ret = mdiobus_read(bus, sw_addr + REG_PORT(0), PORT_SWITCH_ID);
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if (ret >= 0) {
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if (ret == 0x0600)
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if (ret == PORT_SWITCH_ID_6060)
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return "Marvell 88E6060 (A0)";
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if (ret == 0x0601 || ret == 0x0602)
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if (ret == PORT_SWITCH_ID_6060_R1 ||
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ret == PORT_SWITCH_ID_6060_R2)
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return "Marvell 88E6060 (B0)";
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if ((ret & 0xfff0) == 0x0600)
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if ((ret & PORT_SWITCH_ID_6060_MASK) == PORT_SWITCH_ID_6060)
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return "Marvell 88E6060";
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}
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@ -87,22 +86,26 @@ static int mv88e6060_switch_reset(struct dsa_switch *ds)
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unsigned long timeout;
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/* Set all ports to the disabled state. */
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for (i = 0; i < 6; i++) {
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ret = REG_READ(REG_PORT(i), 0x04);
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REG_WRITE(REG_PORT(i), 0x04, ret & 0xfffc);
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for (i = 0; i < MV88E6060_PORTS; i++) {
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ret = REG_READ(REG_PORT(i), PORT_CONTROL);
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REG_WRITE(REG_PORT(i), PORT_CONTROL,
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ret & ~PORT_CONTROL_STATE_MASK);
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}
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/* Wait for transmit queues to drain. */
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usleep_range(2000, 4000);
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/* Reset the switch. */
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REG_WRITE(REG_GLOBAL, 0x0a, 0xa130);
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REG_WRITE(REG_GLOBAL, GLOBAL_ATU_CONTROL,
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GLOBAL_ATU_CONTROL_SWRESET |
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GLOBAL_ATU_CONTROL_ATUSIZE_1024 |
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GLOBAL_ATU_CONTROL_ATE_AGE_5MIN);
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/* Wait up to one second for reset to complete. */
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timeout = jiffies + 1 * HZ;
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while (time_before(jiffies, timeout)) {
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ret = REG_READ(REG_GLOBAL, 0x00);
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if ((ret & 0x8000) == 0x0000)
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ret = REG_READ(REG_GLOBAL, GLOBAL_STATUS);
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if (ret & GLOBAL_STATUS_INIT_READY)
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break;
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usleep_range(1000, 2000);
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@ -119,13 +122,15 @@ static int mv88e6060_setup_global(struct dsa_switch *ds)
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* set the maximum frame size to 1536 bytes, and mask all
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* interrupt sources.
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*/
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REG_WRITE(REG_GLOBAL, 0x04, 0x0800);
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REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL, GLOBAL_CONTROL_MAX_FRAME_1536);
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/* Enable automatic address learning, set the address
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* database size to 1024 entries, and set the default aging
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* time to 5 minutes.
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*/
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REG_WRITE(REG_GLOBAL, 0x0a, 0x2130);
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REG_WRITE(REG_GLOBAL, GLOBAL_ATU_CONTROL,
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GLOBAL_ATU_CONTROL_ATUSIZE_1024 |
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GLOBAL_ATU_CONTROL_ATE_AGE_5MIN);
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return 0;
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}
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@ -139,25 +144,30 @@ static int mv88e6060_setup_port(struct dsa_switch *ds, int p)
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* state to Forwarding. Additionally, if this is the CPU
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* port, enable Ingress and Egress Trailer tagging mode.
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*/
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REG_WRITE(addr, 0x04, dsa_is_cpu_port(ds, p) ? 0x4103 : 0x0003);
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REG_WRITE(addr, PORT_CONTROL,
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dsa_is_cpu_port(ds, p) ?
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PORT_CONTROL_TRAILER |
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PORT_CONTROL_INGRESS_MODE |
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PORT_CONTROL_STATE_FORWARDING :
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PORT_CONTROL_STATE_FORWARDING);
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/* Port based VLAN map: give each port its own address
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* database, allow the CPU port to talk to each of the 'real'
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* ports, and allow each of the 'real' ports to only talk to
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* the CPU port.
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*/
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REG_WRITE(addr, 0x06,
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((p & 0xf) << 12) |
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(dsa_is_cpu_port(ds, p) ?
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ds->phys_port_mask :
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(1 << ds->dst->cpu_port)));
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REG_WRITE(addr, PORT_VLAN_MAP,
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((p & 0xf) << PORT_VLAN_MAP_DBNUM_SHIFT) |
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(dsa_is_cpu_port(ds, p) ?
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ds->phys_port_mask :
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BIT(ds->dst->cpu_port)));
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/* Port Association Vector: when learning source addresses
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* of packets, add the address to the address database using
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* a port bitmap that has only the bit for this port set and
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* the other bits clear.
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*/
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REG_WRITE(addr, 0x0b, 1 << p);
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REG_WRITE(addr, PORT_ASSOC_VECTOR, BIT(p));
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return 0;
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}
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@ -177,7 +187,7 @@ static int mv88e6060_setup(struct dsa_switch *ds)
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if (ret < 0)
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return ret;
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for (i = 0; i < 6; i++) {
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for (i = 0; i < MV88E6060_PORTS; i++) {
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ret = mv88e6060_setup_port(ds, i);
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if (ret < 0)
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return ret;
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@ -188,16 +198,17 @@ static int mv88e6060_setup(struct dsa_switch *ds)
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static int mv88e6060_set_addr(struct dsa_switch *ds, u8 *addr)
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{
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REG_WRITE(REG_GLOBAL, 0x01, (addr[0] << 8) | addr[1]);
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REG_WRITE(REG_GLOBAL, 0x02, (addr[2] << 8) | addr[3]);
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REG_WRITE(REG_GLOBAL, 0x03, (addr[4] << 8) | addr[5]);
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/* Use the same MAC Address as FD Pause frames for all ports */
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REG_WRITE(REG_GLOBAL, GLOBAL_MAC_01, (addr[0] << 9) | addr[1]);
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REG_WRITE(REG_GLOBAL, GLOBAL_MAC_23, (addr[2] << 8) | addr[3]);
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REG_WRITE(REG_GLOBAL, GLOBAL_MAC_45, (addr[4] << 8) | addr[5]);
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return 0;
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}
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static int mv88e6060_port_to_phy_addr(int port)
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{
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if (port >= 0 && port <= 5)
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if (port >= 0 && port < MV88E6060_PORTS)
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return port;
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return -1;
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}
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@ -225,54 +236,6 @@ mv88e6060_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val)
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return reg_write(ds, addr, regnum, val);
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}
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static void mv88e6060_poll_link(struct dsa_switch *ds)
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{
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int i;
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for (i = 0; i < DSA_MAX_PORTS; i++) {
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struct net_device *dev;
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int uninitialized_var(port_status);
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int link;
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int speed;
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int duplex;
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int fc;
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dev = ds->ports[i];
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if (dev == NULL)
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continue;
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link = 0;
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if (dev->flags & IFF_UP) {
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port_status = reg_read(ds, REG_PORT(i), 0x00);
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if (port_status < 0)
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continue;
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link = !!(port_status & 0x1000);
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}
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if (!link) {
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if (netif_carrier_ok(dev)) {
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netdev_info(dev, "link down\n");
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netif_carrier_off(dev);
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}
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continue;
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}
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speed = (port_status & 0x0100) ? 100 : 10;
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duplex = (port_status & 0x0200) ? 1 : 0;
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fc = ((port_status & 0xc000) == 0xc000) ? 1 : 0;
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if (!netif_carrier_ok(dev)) {
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netdev_info(dev,
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"link up, %d Mb/s, %s duplex, flow control %sabled\n",
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speed,
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duplex ? "full" : "half",
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fc ? "en" : "dis");
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netif_carrier_on(dev);
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}
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}
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}
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static struct dsa_switch_driver mv88e6060_switch_driver = {
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.tag_protocol = DSA_TAG_PROTO_TRAILER,
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.probe = mv88e6060_probe,
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@ -280,7 +243,6 @@ static struct dsa_switch_driver mv88e6060_switch_driver = {
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.set_addr = mv88e6060_set_addr,
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.phy_read = mv88e6060_phy_read,
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.phy_write = mv88e6060_phy_write,
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.poll_link = mv88e6060_poll_link,
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};
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static int __init mv88e6060_init(void)
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@ -0,0 +1,111 @@
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/*
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* drivers/net/dsa/mv88e6060.h - Marvell 88e6060 switch chip support
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* Copyright (c) 2015 Neil Armstrong
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*
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* Based on mv88e6xxx.h
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* Copyright (c) 2008 Marvell Semiconductor
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#ifndef __MV88E6060_H
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#define __MV88E6060_H
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#define MV88E6060_PORTS 6
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#define REG_PORT(p) (0x8 + (p))
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#define PORT_STATUS 0x00
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#define PORT_STATUS_PAUSE_EN BIT(15)
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#define PORT_STATUS_MY_PAUSE BIT(14)
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#define PORT_STATUS_FC (PORT_STATUS_MY_PAUSE | PORT_STATUS_PAUSE_EN)
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#define PORT_STATUS_RESOLVED BIT(13)
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#define PORT_STATUS_LINK BIT(12)
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#define PORT_STATUS_PORTMODE BIT(11)
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#define PORT_STATUS_PHYMODE BIT(10)
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#define PORT_STATUS_DUPLEX BIT(9)
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#define PORT_STATUS_SPEED BIT(8)
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#define PORT_SWITCH_ID 0x03
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#define PORT_SWITCH_ID_6060 0x0600
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#define PORT_SWITCH_ID_6060_MASK 0xfff0
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#define PORT_SWITCH_ID_6060_R1 0x0601
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#define PORT_SWITCH_ID_6060_R2 0x0602
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#define PORT_CONTROL 0x04
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#define PORT_CONTROL_FORCE_FLOW_CTRL BIT(15)
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#define PORT_CONTROL_TRAILER BIT(14)
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#define PORT_CONTROL_HEADER BIT(11)
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#define PORT_CONTROL_INGRESS_MODE BIT(8)
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#define PORT_CONTROL_VLAN_TUNNEL BIT(7)
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#define PORT_CONTROL_STATE_MASK 0x03
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#define PORT_CONTROL_STATE_DISABLED 0x00
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#define PORT_CONTROL_STATE_BLOCKING 0x01
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#define PORT_CONTROL_STATE_LEARNING 0x02
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#define PORT_CONTROL_STATE_FORWARDING 0x03
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#define PORT_VLAN_MAP 0x06
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#define PORT_VLAN_MAP_DBNUM_SHIFT 12
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#define PORT_VLAN_MAP_TABLE_MASK 0x1f
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#define PORT_ASSOC_VECTOR 0x0b
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#define PORT_ASSOC_VECTOR_MONITOR BIT(15)
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#define PORT_ASSOC_VECTOR_PAV_MASK 0x1f
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#define PORT_RX_CNTR 0x10
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#define PORT_TX_CNTR 0x11
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#define REG_GLOBAL 0x0f
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#define GLOBAL_STATUS 0x00
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#define GLOBAL_STATUS_SW_MODE_MASK (0x3 << 12)
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#define GLOBAL_STATUS_SW_MODE_0 (0x0 << 12)
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#define GLOBAL_STATUS_SW_MODE_1 (0x1 << 12)
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#define GLOBAL_STATUS_SW_MODE_2 (0x2 << 12)
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#define GLOBAL_STATUS_SW_MODE_3 (0x3 << 12)
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#define GLOBAL_STATUS_INIT_READY BIT(11)
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#define GLOBAL_STATUS_ATU_FULL BIT(3)
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#define GLOBAL_STATUS_ATU_DONE BIT(2)
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#define GLOBAL_STATUS_PHY_INT BIT(1)
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#define GLOBAL_STATUS_EEINT BIT(0)
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#define GLOBAL_MAC_01 0x01
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#define GLOBAL_MAC_01_DIFF_ADDR BIT(8)
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#define GLOBAL_MAC_23 0x02
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#define GLOBAL_MAC_45 0x03
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#define GLOBAL_CONTROL 0x04
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#define GLOBAL_CONTROL_DISCARD_EXCESS BIT(13)
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#define GLOBAL_CONTROL_MAX_FRAME_1536 BIT(10)
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#define GLOBAL_CONTROL_RELOAD_EEPROM BIT(9)
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#define GLOBAL_CONTROL_CTRMODE BIT(8)
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#define GLOBAL_CONTROL_ATU_FULL_EN BIT(3)
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#define GLOBAL_CONTROL_ATU_DONE_EN BIT(2)
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#define GLOBAL_CONTROL_PHYINT_EN BIT(1)
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#define GLOBAL_CONTROL_EEPROM_DONE_EN BIT(0)
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#define GLOBAL_ATU_CONTROL 0x0a
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#define GLOBAL_ATU_CONTROL_SWRESET BIT(15)
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#define GLOBAL_ATU_CONTROL_LEARNDIS BIT(14)
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#define GLOBAL_ATU_CONTROL_ATUSIZE_256 (0x0 << 12)
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#define GLOBAL_ATU_CONTROL_ATUSIZE_512 (0x1 << 12)
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#define GLOBAL_ATU_CONTROL_ATUSIZE_1024 (0x2 << 12)
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#define GLOBAL_ATU_CONTROL_ATE_AGE_SHIFT 4
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#define GLOBAL_ATU_CONTROL_ATE_AGE_MASK (0xff << 4)
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#define GLOBAL_ATU_CONTROL_ATE_AGE_5MIN (0x13 << 4)
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#define GLOBAL_ATU_OP 0x0b
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#define GLOBAL_ATU_OP_BUSY BIT(15)
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#define GLOBAL_ATU_OP_NOP (0 << 12)
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#define GLOBAL_ATU_OP_FLUSH_ALL ((1 << 12) | GLOBAL_ATU_OP_BUSY)
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#define GLOBAL_ATU_OP_FLUSH_UNLOCKED ((2 << 12) | GLOBAL_ATU_OP_BUSY)
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#define GLOBAL_ATU_OP_LOAD_DB ((3 << 12) | GLOBAL_ATU_OP_BUSY)
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#define GLOBAL_ATU_OP_GET_NEXT_DB ((4 << 12) | GLOBAL_ATU_OP_BUSY)
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#define GLOBAL_ATU_OP_FLUSH_DB ((5 << 12) | GLOBAL_ATU_OP_BUSY)
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#define GLOBAL_ATU_OP_FLUSH_UNLOCKED_DB ((6 << 12) | GLOBAL_ATU_OP_BUSY)
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#define GLOBAL_ATU_DATA 0x0c
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#define GLOBAL_ATU_DATA_PORT_VECTOR_MASK 0x3f0
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#define GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT 4
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#define GLOBAL_ATU_DATA_STATE_MASK 0x0f
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#define GLOBAL_ATU_DATA_STATE_UNUSED 0x00
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#define GLOBAL_ATU_DATA_STATE_UC_STATIC 0x0e
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#define GLOBAL_ATU_DATA_STATE_UC_LOCKED 0x0f
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#define GLOBAL_ATU_DATA_STATE_MC_STATIC 0x07
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#define GLOBAL_ATU_DATA_STATE_MC_LOCKED 0x0e
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#define GLOBAL_ATU_MAC_01 0x0d
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#define GLOBAL_ATU_MAC_23 0x0e
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#define GLOBAL_ATU_MAC_45 0x0f
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#endif
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