staging: comedi: s626: move encoder functions part 2
Move some more functions to help avoid the forward declaration of `s626_enc_chan_info[]`. Signed-off-by: Ian Abbott <abbotti@mev.co.uk> Reviewed-by: H Hartley Sweeten <hsweeten@visionengravers.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Ian Abbott
Greg Kroah-Hartman
parent
010be96fb6
commit
17afeac2fd
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@ -793,6 +793,245 @@ static uint16_t get_mode_b(struct comedi_device *dev,
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return setup;
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}
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/*
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* Set the operating mode for the specified counter. The setup
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* parameter is treated as a COUNTER_SETUP data type. The following
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* parameters are programmable (all other parms are ignored): ClkMult,
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* ClkPol, ClkEnab, IndexSrc, IndexPol, LoadSrc.
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*/
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static void set_mode_a(struct comedi_device *dev, const struct s626_enc_info *k,
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uint16_t setup, uint16_t disable_int_src)
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{
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struct s626_private *devpriv = dev->private;
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uint16_t cra;
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uint16_t crb;
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/* Initialize CRA and CRB images. */
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/* Preload trigger is passed through. */
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cra = setup & CRAMSK_LOADSRC_A;
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/* IndexSrc is restricted to ENC_X or IndxPol. */
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cra |= ((setup & STDMSK_INDXSRC) >>
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(STDBIT_INDXSRC - (CRABIT_INDXSRC_A + 1)));
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/* Reset any pending CounterA event captures. */
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crb = CRBMSK_INTRESETCMD | CRBMSK_INTRESET_A;
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/* Clock enable is passed through. */
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crb |= (setup & STDMSK_CLKENAB) << (CRBBIT_CLKENAB_A - STDBIT_CLKENAB);
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/* Force IntSrc to Disabled if disable_int_src is asserted. */
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if (!disable_int_src)
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cra |= ((setup & STDMSK_INTSRC) >> (STDBIT_INTSRC -
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CRABIT_INTSRC_A));
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/* Populate all mode-dependent attributes of CRA & CRB images. */
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switch ((setup & STDMSK_CLKSRC) >> STDBIT_CLKSRC) {
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case CLKSRC_EXTENDER: /* Extender Mode: Force to Timer mode
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* (Extender valid only for B counters). */
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/* Fall through to case CLKSRC_TIMER: */
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case CLKSRC_TIMER: /* Timer Mode: */
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/* ClkSrcA<1> selects system clock */
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cra |= 2 << CRABIT_CLKSRC_A;
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/* Count direction (ClkSrcA<0>) obtained from ClkPol. */
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cra |= (setup & STDMSK_CLKPOL) >>
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(STDBIT_CLKPOL - CRABIT_CLKSRC_A);
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/* ClkPolA behaves as always-on clock enable. */
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cra |= 1 << CRABIT_CLKPOL_A;
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/* ClkMult must be 1x. */
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cra |= MULT_X1 << CRABIT_CLKMULT_A;
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break;
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default: /* Counter Mode: */
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/* Select ENC_C and ENC_D as clock/direction inputs. */
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cra |= CLKSRC_COUNTER;
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/* Clock polarity is passed through. */
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cra |= (setup & STDMSK_CLKPOL) <<
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(CRABIT_CLKPOL_A - STDBIT_CLKPOL);
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/* Force multiplier to x1 if not legal, else pass through. */
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if ((setup & STDMSK_CLKMULT) == (MULT_X0 << STDBIT_CLKMULT))
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cra |= MULT_X1 << CRABIT_CLKMULT_A;
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else
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cra |= (setup & STDMSK_CLKMULT) <<
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(CRABIT_CLKMULT_A - STDBIT_CLKMULT);
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break;
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}
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/*
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* Force positive index polarity if IndxSrc is software-driven only,
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* otherwise pass it through.
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*/
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if (~setup & STDMSK_INDXSRC)
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cra |= (setup & STDMSK_INDXPOL) <<
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(CRABIT_INDXPOL_A - STDBIT_INDXPOL);
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/*
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* If IntSrc has been forced to Disabled, update the MISC2 interrupt
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* enable mask to indicate the counter interrupt is disabled.
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*/
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if (disable_int_src)
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devpriv->counter_int_enabs &= ~k->my_event_bits[3];
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/*
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* While retaining CounterB and LatchSrc configurations, program the
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* new counter operating mode.
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*/
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debi_replace(dev, k->my_cra, CRAMSK_INDXSRC_B | CRAMSK_CLKSRC_B, cra);
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debi_replace(dev, k->my_crb, ~(CRBMSK_INTCTRL | CRBMSK_CLKENAB_A), crb);
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}
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static void set_mode_b(struct comedi_device *dev, const struct s626_enc_info *k,
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uint16_t setup, uint16_t disable_int_src)
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{
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struct s626_private *devpriv = dev->private;
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uint16_t cra;
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uint16_t crb;
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/* Initialize CRA and CRB images. */
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/* IndexSrc field is restricted to ENC_X or IndxPol. */
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cra = (setup & STDMSK_INDXSRC) <<
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(CRABIT_INDXSRC_B + 1 - STDBIT_INDXSRC);
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/* Reset event captures and disable interrupts. */
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crb = CRBMSK_INTRESETCMD | CRBMSK_INTRESET_B;
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/* Clock enable is passed through. */
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crb |= (setup & STDMSK_CLKENAB) << (CRBBIT_CLKENAB_B - STDBIT_CLKENAB);
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/* Preload trigger source is passed through. */
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crb |= (setup & STDMSK_LOADSRC) >> (STDBIT_LOADSRC - CRBBIT_LOADSRC_B);
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/* Force IntSrc to Disabled if disable_int_src is asserted. */
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if (!disable_int_src)
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crb |= (setup & STDMSK_INTSRC) >>
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(STDBIT_INTSRC - CRBBIT_INTSRC_B);
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/* Populate all mode-dependent attributes of CRA & CRB images. */
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switch ((setup & STDMSK_CLKSRC) >> STDBIT_CLKSRC) {
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case CLKSRC_TIMER: /* Timer Mode: */
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/* ClkSrcB<1> selects system clock */
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cra |= 2 << CRABIT_CLKSRC_B;
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/* with direction (ClkSrcB<0>) obtained from ClkPol. */
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cra |= (setup & STDMSK_CLKPOL) <<
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(CRABIT_CLKSRC_B - STDBIT_CLKPOL);
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/* ClkPolB behaves as always-on clock enable. */
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crb |= 1 << CRBBIT_CLKPOL_B;
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/* ClkMultB must be 1x. */
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crb |= MULT_X1 << CRBBIT_CLKMULT_B;
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break;
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case CLKSRC_EXTENDER: /* Extender Mode: */
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/* ClkSrcB source is OverflowA (same as "timer") */
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cra |= 2 << CRABIT_CLKSRC_B;
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/* with direction obtained from ClkPol. */
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cra |= (setup & STDMSK_CLKPOL) <<
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(CRABIT_CLKSRC_B - STDBIT_CLKPOL);
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/* ClkPolB controls IndexB -- always set to active. */
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crb |= 1 << CRBBIT_CLKPOL_B;
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/* ClkMultB selects OverflowA as the clock source. */
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crb |= MULT_X0 << CRBBIT_CLKMULT_B;
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break;
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default: /* Counter Mode: */
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/* Select ENC_C and ENC_D as clock/direction inputs. */
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cra |= CLKSRC_COUNTER << CRABIT_CLKSRC_B;
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/* ClkPol is passed through. */
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crb |= (setup & STDMSK_CLKPOL) >>
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(STDBIT_CLKPOL - CRBBIT_CLKPOL_B);
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/* Force ClkMult to x1 if not legal, otherwise pass through. */
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if ((setup & STDMSK_CLKMULT) == (MULT_X0 << STDBIT_CLKMULT))
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crb |= MULT_X1 << CRBBIT_CLKMULT_B;
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else
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crb |= (setup & STDMSK_CLKMULT) <<
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(CRBBIT_CLKMULT_B - STDBIT_CLKMULT);
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break;
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}
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/*
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* Force positive index polarity if IndxSrc is software-driven only,
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* otherwise pass it through.
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*/
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if (~setup & STDMSK_INDXSRC)
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crb |= (setup & STDMSK_INDXPOL) >>
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(STDBIT_INDXPOL - CRBBIT_INDXPOL_B);
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/*
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* If IntSrc has been forced to Disabled, update the MISC2 interrupt
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* enable mask to indicate the counter interrupt is disabled.
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*/
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if (disable_int_src)
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devpriv->counter_int_enabs &= ~k->my_event_bits[3];
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/*
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* While retaining CounterA and LatchSrc configurations, program the
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* new counter operating mode.
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*/
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debi_replace(dev, k->my_cra, ~(CRAMSK_INDXSRC_B | CRAMSK_CLKSRC_B),
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cra);
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debi_replace(dev, k->my_crb, CRBMSK_CLKENAB_A | CRBMSK_LATCHSRC, crb);
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}
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/*
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* Return/set a counter's enable. enab: 0=always enabled, 1=enabled by index.
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*/
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static void set_enable_a(struct comedi_device *dev,
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const struct s626_enc_info *k, uint16_t enab)
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{
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debi_replace(dev, k->my_crb, ~(CRBMSK_INTCTRL | CRBMSK_CLKENAB_A),
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enab << CRBBIT_CLKENAB_A);
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}
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static void set_enable_b(struct comedi_device *dev,
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const struct s626_enc_info *k, uint16_t enab)
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{
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debi_replace(dev, k->my_crb, ~(CRBMSK_INTCTRL | CRBMSK_CLKENAB_B),
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enab << CRBBIT_CLKENAB_B);
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}
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static uint16_t get_enable_a(struct comedi_device *dev,
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const struct s626_enc_info *k)
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{
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return (debi_read(dev, k->my_crb) >> CRBBIT_CLKENAB_A) & 1;
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}
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static uint16_t get_enable_b(struct comedi_device *dev,
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const struct s626_enc_info *k)
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{
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return (debi_read(dev, k->my_crb) >> CRBBIT_CLKENAB_B) & 1;
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}
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#ifdef unused
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static uint16_t get_latch_source(struct comedi_device *dev,
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const struct s626_enc_info *k)
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{
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return (debi_read(dev, k->my_crb) >> CRBBIT_LATCHSRC) & 3;
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}
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#endif
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/*
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* Return/set the event that will trigger transfer of the preload
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* register into the counter. 0=ThisCntr_Index, 1=ThisCntr_Overflow,
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* 2=OverflowA (B counters only), 3=disabled.
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*/
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static void set_load_trig_a(struct comedi_device *dev,
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const struct s626_enc_info *k, uint16_t trig)
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{
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debi_replace(dev, k->my_cra, ~CRAMSK_LOADSRC_A,
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trig << CRABIT_LOADSRC_A);
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}
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static void set_load_trig_b(struct comedi_device *dev,
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const struct s626_enc_info *k, uint16_t trig)
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{
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debi_replace(dev, k->my_crb, ~(CRBMSK_LOADSRC_B | CRBMSK_INTCTRL),
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trig << CRBBIT_LOADSRC_B);
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}
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static uint16_t get_load_trig_a(struct comedi_device *dev,
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const struct s626_enc_info *k)
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{
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return (debi_read(dev, k->my_cra) >> CRABIT_LOADSRC_A) & 3;
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}
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static uint16_t get_load_trig_b(struct comedi_device *dev,
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const struct s626_enc_info *k)
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{
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return (debi_read(dev, k->my_crb) >> CRBBIT_LOADSRC_B) & 3;
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}
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static unsigned int s626_ai_reg_to_uint(int data)
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{
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unsigned int tempdata;
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@ -1964,245 +2203,6 @@ static void close_dma_b(struct comedi_device *dev, struct buffer_dma *pdma,
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}
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}
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/*
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* Set the operating mode for the specified counter. The setup
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* parameter is treated as a COUNTER_SETUP data type. The following
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* parameters are programmable (all other parms are ignored): ClkMult,
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* ClkPol, ClkEnab, IndexSrc, IndexPol, LoadSrc.
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*/
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static void set_mode_a(struct comedi_device *dev, const struct s626_enc_info *k,
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uint16_t setup, uint16_t disable_int_src)
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{
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struct s626_private *devpriv = dev->private;
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uint16_t cra;
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uint16_t crb;
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/* Initialize CRA and CRB images. */
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/* Preload trigger is passed through. */
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cra = setup & CRAMSK_LOADSRC_A;
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/* IndexSrc is restricted to ENC_X or IndxPol. */
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cra |= ((setup & STDMSK_INDXSRC) >>
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(STDBIT_INDXSRC - (CRABIT_INDXSRC_A + 1)));
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/* Reset any pending CounterA event captures. */
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crb = CRBMSK_INTRESETCMD | CRBMSK_INTRESET_A;
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/* Clock enable is passed through. */
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crb |= (setup & STDMSK_CLKENAB) << (CRBBIT_CLKENAB_A - STDBIT_CLKENAB);
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/* Force IntSrc to Disabled if disable_int_src is asserted. */
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if (!disable_int_src)
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cra |= ((setup & STDMSK_INTSRC) >> (STDBIT_INTSRC -
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CRABIT_INTSRC_A));
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/* Populate all mode-dependent attributes of CRA & CRB images. */
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switch ((setup & STDMSK_CLKSRC) >> STDBIT_CLKSRC) {
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case CLKSRC_EXTENDER: /* Extender Mode: Force to Timer mode
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* (Extender valid only for B counters). */
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/* Fall through to case CLKSRC_TIMER: */
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case CLKSRC_TIMER: /* Timer Mode: */
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/* ClkSrcA<1> selects system clock */
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cra |= 2 << CRABIT_CLKSRC_A;
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/* Count direction (ClkSrcA<0>) obtained from ClkPol. */
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cra |= (setup & STDMSK_CLKPOL) >>
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(STDBIT_CLKPOL - CRABIT_CLKSRC_A);
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/* ClkPolA behaves as always-on clock enable. */
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cra |= 1 << CRABIT_CLKPOL_A;
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/* ClkMult must be 1x. */
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cra |= MULT_X1 << CRABIT_CLKMULT_A;
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break;
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default: /* Counter Mode: */
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/* Select ENC_C and ENC_D as clock/direction inputs. */
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cra |= CLKSRC_COUNTER;
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/* Clock polarity is passed through. */
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cra |= (setup & STDMSK_CLKPOL) <<
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(CRABIT_CLKPOL_A - STDBIT_CLKPOL);
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/* Force multiplier to x1 if not legal, else pass through. */
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if ((setup & STDMSK_CLKMULT) == (MULT_X0 << STDBIT_CLKMULT))
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cra |= MULT_X1 << CRABIT_CLKMULT_A;
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else
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cra |= (setup & STDMSK_CLKMULT) <<
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(CRABIT_CLKMULT_A - STDBIT_CLKMULT);
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break;
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}
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/*
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* Force positive index polarity if IndxSrc is software-driven only,
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* otherwise pass it through.
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*/
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if (~setup & STDMSK_INDXSRC)
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cra |= (setup & STDMSK_INDXPOL) <<
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(CRABIT_INDXPOL_A - STDBIT_INDXPOL);
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/*
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* If IntSrc has been forced to Disabled, update the MISC2 interrupt
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* enable mask to indicate the counter interrupt is disabled.
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*/
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if (disable_int_src)
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devpriv->counter_int_enabs &= ~k->my_event_bits[3];
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/*
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* While retaining CounterB and LatchSrc configurations, program the
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* new counter operating mode.
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*/
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debi_replace(dev, k->my_cra, CRAMSK_INDXSRC_B | CRAMSK_CLKSRC_B, cra);
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debi_replace(dev, k->my_crb, ~(CRBMSK_INTCTRL | CRBMSK_CLKENAB_A), crb);
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}
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static void set_mode_b(struct comedi_device *dev, const struct s626_enc_info *k,
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uint16_t setup, uint16_t disable_int_src)
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{
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struct s626_private *devpriv = dev->private;
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uint16_t cra;
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uint16_t crb;
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/* Initialize CRA and CRB images. */
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/* IndexSrc field is restricted to ENC_X or IndxPol. */
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cra = (setup & STDMSK_INDXSRC) <<
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(CRABIT_INDXSRC_B + 1 - STDBIT_INDXSRC);
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/* Reset event captures and disable interrupts. */
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crb = CRBMSK_INTRESETCMD | CRBMSK_INTRESET_B;
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/* Clock enable is passed through. */
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crb |= (setup & STDMSK_CLKENAB) << (CRBBIT_CLKENAB_B - STDBIT_CLKENAB);
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/* Preload trigger source is passed through. */
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crb |= (setup & STDMSK_LOADSRC) >> (STDBIT_LOADSRC - CRBBIT_LOADSRC_B);
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/* Force IntSrc to Disabled if disable_int_src is asserted. */
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if (!disable_int_src)
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crb |= (setup & STDMSK_INTSRC) >>
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(STDBIT_INTSRC - CRBBIT_INTSRC_B);
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/* Populate all mode-dependent attributes of CRA & CRB images. */
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switch ((setup & STDMSK_CLKSRC) >> STDBIT_CLKSRC) {
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case CLKSRC_TIMER: /* Timer Mode: */
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/* ClkSrcB<1> selects system clock */
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cra |= 2 << CRABIT_CLKSRC_B;
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/* with direction (ClkSrcB<0>) obtained from ClkPol. */
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cra |= (setup & STDMSK_CLKPOL) <<
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(CRABIT_CLKSRC_B - STDBIT_CLKPOL);
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/* ClkPolB behaves as always-on clock enable. */
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crb |= 1 << CRBBIT_CLKPOL_B;
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/* ClkMultB must be 1x. */
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crb |= MULT_X1 << CRBBIT_CLKMULT_B;
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break;
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case CLKSRC_EXTENDER: /* Extender Mode: */
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/* ClkSrcB source is OverflowA (same as "timer") */
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cra |= 2 << CRABIT_CLKSRC_B;
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/* with direction obtained from ClkPol. */
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cra |= (setup & STDMSK_CLKPOL) <<
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(CRABIT_CLKSRC_B - STDBIT_CLKPOL);
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/* ClkPolB controls IndexB -- always set to active. */
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crb |= 1 << CRBBIT_CLKPOL_B;
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/* ClkMultB selects OverflowA as the clock source. */
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crb |= MULT_X0 << CRBBIT_CLKMULT_B;
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break;
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default: /* Counter Mode: */
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/* Select ENC_C and ENC_D as clock/direction inputs. */
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cra |= CLKSRC_COUNTER << CRABIT_CLKSRC_B;
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/* ClkPol is passed through. */
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crb |= (setup & STDMSK_CLKPOL) >>
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(STDBIT_CLKPOL - CRBBIT_CLKPOL_B);
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/* Force ClkMult to x1 if not legal, otherwise pass through. */
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if ((setup & STDMSK_CLKMULT) == (MULT_X0 << STDBIT_CLKMULT))
|
||||
crb |= MULT_X1 << CRBBIT_CLKMULT_B;
|
||||
else
|
||||
crb |= (setup & STDMSK_CLKMULT) <<
|
||||
(CRBBIT_CLKMULT_B - STDBIT_CLKMULT);
|
||||
break;
|
||||
}
|
||||
|
||||
/*
|
||||
* Force positive index polarity if IndxSrc is software-driven only,
|
||||
* otherwise pass it through.
|
||||
*/
|
||||
if (~setup & STDMSK_INDXSRC)
|
||||
crb |= (setup & STDMSK_INDXPOL) >>
|
||||
(STDBIT_INDXPOL - CRBBIT_INDXPOL_B);
|
||||
|
||||
/*
|
||||
* If IntSrc has been forced to Disabled, update the MISC2 interrupt
|
||||
* enable mask to indicate the counter interrupt is disabled.
|
||||
*/
|
||||
if (disable_int_src)
|
||||
devpriv->counter_int_enabs &= ~k->my_event_bits[3];
|
||||
|
||||
/*
|
||||
* While retaining CounterA and LatchSrc configurations, program the
|
||||
* new counter operating mode.
|
||||
*/
|
||||
debi_replace(dev, k->my_cra, ~(CRAMSK_INDXSRC_B | CRAMSK_CLKSRC_B),
|
||||
cra);
|
||||
debi_replace(dev, k->my_crb, CRBMSK_CLKENAB_A | CRBMSK_LATCHSRC, crb);
|
||||
}
|
||||
|
||||
/*
|
||||
* Return/set a counter's enable. enab: 0=always enabled, 1=enabled by index.
|
||||
*/
|
||||
static void set_enable_a(struct comedi_device *dev,
|
||||
const struct s626_enc_info *k, uint16_t enab)
|
||||
{
|
||||
debi_replace(dev, k->my_crb, ~(CRBMSK_INTCTRL | CRBMSK_CLKENAB_A),
|
||||
enab << CRBBIT_CLKENAB_A);
|
||||
}
|
||||
|
||||
static void set_enable_b(struct comedi_device *dev, const
|
||||
struct s626_enc_info *k, uint16_t enab)
|
||||
{
|
||||
debi_replace(dev, k->my_crb, ~(CRBMSK_INTCTRL | CRBMSK_CLKENAB_B),
|
||||
enab << CRBBIT_CLKENAB_B);
|
||||
}
|
||||
|
||||
static uint16_t get_enable_a(struct comedi_device *dev,
|
||||
const struct s626_enc_info *k)
|
||||
{
|
||||
return (debi_read(dev, k->my_crb) >> CRBBIT_CLKENAB_A) & 1;
|
||||
}
|
||||
|
||||
static uint16_t get_enable_b(struct comedi_device *dev,
|
||||
const struct s626_enc_info *k)
|
||||
{
|
||||
return (debi_read(dev, k->my_crb) >> CRBBIT_CLKENAB_B) & 1;
|
||||
}
|
||||
|
||||
#ifdef unused
|
||||
static uint16_t get_latch_source(struct comedi_device *dev,
|
||||
const struct s626_enc_info *k)
|
||||
{
|
||||
return (debi_read(dev, k->my_crb) >> CRBBIT_LATCHSRC) & 3;
|
||||
}
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Return/set the event that will trigger transfer of the preload
|
||||
* register into the counter. 0=ThisCntr_Index, 1=ThisCntr_Overflow,
|
||||
* 2=OverflowA (B counters only), 3=disabled.
|
||||
*/
|
||||
static void set_load_trig_a(struct comedi_device *dev,
|
||||
const struct s626_enc_info *k, uint16_t trig)
|
||||
{
|
||||
debi_replace(dev, k->my_cra, ~CRAMSK_LOADSRC_A,
|
||||
trig << CRABIT_LOADSRC_A);
|
||||
}
|
||||
|
||||
static void set_load_trig_b(struct comedi_device *dev,
|
||||
const struct s626_enc_info *k, uint16_t trig)
|
||||
{
|
||||
debi_replace(dev, k->my_crb, ~(CRBMSK_LOADSRC_B | CRBMSK_INTCTRL),
|
||||
trig << CRBBIT_LOADSRC_B);
|
||||
}
|
||||
|
||||
static uint16_t get_load_trig_a(struct comedi_device *dev,
|
||||
const struct s626_enc_info *k)
|
||||
{
|
||||
return (debi_read(dev, k->my_cra) >> CRABIT_LOADSRC_A) & 3;
|
||||
}
|
||||
|
||||
static uint16_t get_load_trig_b(struct comedi_device *dev,
|
||||
const struct s626_enc_info *k)
|
||||
{
|
||||
return (debi_read(dev, k->my_crb) >> CRBBIT_LOADSRC_B) & 3;
|
||||
}
|
||||
|
||||
/*
|
||||
* Return/set counter interrupt source and clear any captured
|
||||
* index/overflow events. int_source: 0=Disabled, 1=OverflowOnly,
|
||||
|
|
|
|||
Loading…
Reference in New Issue