x86, msr: Rewrite AMD rd/wrmsr variants
Switch them to native_{rd,wr}msr_safe_regs and remove pv_cpu_ops.read_msr_amd. Signed-off-by: Borislav Petkov <petkovbb@gmail.com> LKML-Reference: <1251705011-18636-2-git-send-email-petkovbb@gmail.com> Signed-off-by: H. Peter Anvin <hpa@zytor.com>
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@ -71,22 +71,6 @@ static inline unsigned long long native_read_msr_safe(unsigned int msr,
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return EAX_EDX_VAL(val, low, high);
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}
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static inline unsigned long long native_read_msr_amd_safe(unsigned int msr,
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int *err)
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{
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DECLARE_ARGS(val, low, high);
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asm volatile("2: rdmsr ; xor %0,%0\n"
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"1:\n\t"
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".section .fixup,\"ax\"\n\t"
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"3: mov %3,%0 ; jmp 1b\n\t"
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".previous\n\t"
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_ASM_EXTABLE(2b, 3b)
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: "=r" (*err), EAX_EDX_RET(val, low, high)
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: "c" (msr), "D" (0x9c5a203a), "i" (-EFAULT));
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return EAX_EDX_VAL(val, low, high);
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}
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static inline void native_write_msr(unsigned int msr,
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unsigned low, unsigned high)
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{
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@ -184,14 +168,34 @@ static inline int rdmsrl_safe(unsigned msr, unsigned long long *p)
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*p = native_read_msr_safe(msr, &err);
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return err;
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}
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static inline int rdmsrl_amd_safe(unsigned msr, unsigned long long *p)
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{
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u32 gprs[8] = { 0 };
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int err;
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*p = native_read_msr_amd_safe(msr, &err);
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gprs[1] = msr;
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gprs[7] = 0x9c5a203a;
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err = native_rdmsr_safe_regs(gprs);
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*p = gprs[0] | ((u64)gprs[2] << 32);
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return err;
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}
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static inline int wrmsrl_amd_safe(unsigned msr, unsigned long long val)
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{
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u32 gprs[8] = { 0 };
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gprs[0] = (u32)val;
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gprs[1] = msr;
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gprs[2] = val >> 32;
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gprs[7] = 0x9c5a203a;
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return native_wrmsr_safe_regs(gprs);
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}
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static inline int rdmsr_safe_regs(u32 *regs)
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{
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return native_rdmsr_safe_regs(regs);
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@ -166,7 +166,6 @@ struct pv_cpu_ops {
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/* MSR, PMC and TSR operations.
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err = 0/-EFAULT. wrmsr returns 0/-EFAULT. */
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u64 (*read_msr_amd)(unsigned int msr, int *err);
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u64 (*read_msr)(unsigned int msr, int *err);
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int (*rdmsr_regs)(u32 *regs);
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int (*write_msr)(unsigned int msr, unsigned low, unsigned high);
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@ -828,10 +827,6 @@ static inline int paravirt_rdmsr_regs(u32 *regs)
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return PVOP_CALL1(int, pv_cpu_ops.rdmsr_regs, regs);
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}
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static inline u64 paravirt_read_msr_amd(unsigned msr, int *err)
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{
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return PVOP_CALL2(u64, pv_cpu_ops.read_msr_amd, msr, err);
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}
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static inline int paravirt_write_msr(unsigned msr, unsigned low, unsigned high)
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{
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return PVOP_CALL3(int, pv_cpu_ops.write_msr, msr, low, high);
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@ -887,12 +882,31 @@ static inline int rdmsrl_safe(unsigned msr, unsigned long long *p)
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}
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static inline int rdmsrl_amd_safe(unsigned msr, unsigned long long *p)
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{
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u32 gprs[8] = { 0 };
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int err;
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*p = paravirt_read_msr_amd(msr, &err);
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gprs[1] = msr;
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gprs[7] = 0x9c5a203a;
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err = paravirt_rdmsr_regs(gprs);
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*p = gprs[0] | ((u64)gprs[2] << 32);
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return err;
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}
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static inline int wrmsrl_amd_safe(unsigned msr, unsigned long long val)
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{
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u32 gprs[8] = { 0 };
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gprs[0] = (u32)val;
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gprs[1] = msr;
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gprs[2] = val >> 32;
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gprs[7] = 0x9c5a203a;
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return paravirt_wrmsr_regs(gprs);
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}
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static inline u64 paravirt_read_tsc(void)
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{
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return PVOP_CALL0(u64, pv_cpu_ops.read_tsc);
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@ -363,7 +363,6 @@ struct pv_cpu_ops pv_cpu_ops = {
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.wbinvd = native_wbinvd,
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.read_msr = native_read_msr_safe,
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.rdmsr_regs = native_rdmsr_safe_regs,
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.read_msr_amd = native_read_msr_amd_safe,
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.write_msr = native_write_msr_safe,
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.wrmsr_regs = native_wrmsr_safe_regs,
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.read_tsc = native_read_tsc,
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