ARM: pxa: remove platform dma code
As the last pxa related driver was converted to dmaengine, it's time to kill the legacy dma code, which is not used anymore. This finishes the pxa dmaengine transition. Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
This commit is contained in:
Robert Jarzmik
parent
976e509c2d
commit
1761b1076a
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@ -54,3 +54,4 @@ extern struct platform_device pxa3xx_device_gpio;
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extern struct platform_device pxa93x_device_gpio;
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void __init pxa_register_device(struct platform_device *dev, void *data);
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void __init pxa2xx_set_dmac_info(int nb_channels, int nb_requestors);
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@ -17,5 +17,4 @@
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/* DMA Controller Registers Definitions */
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#define DMAC_REGS_VIRT io_p2v(0x40000000)
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#include <plat/dma.h>
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#endif /* _ASM_ARCH_DMA_H */
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@ -198,9 +198,6 @@ static int __init pxa25x_init(void)
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reset_status = RCSR;
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if ((ret = pxa_init_dma(IRQ_DMA, 16)))
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return ret;
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pxa25x_init_pm();
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register_syscore_ops(&pxa_irq_syscore_ops);
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@ -300,9 +300,6 @@ static int __init pxa27x_init(void)
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reset_status = RCSR;
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if ((ret = pxa_init_dma(IRQ_DMA, 32)))
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return ret;
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pxa27x_init_pm();
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register_syscore_ops(&pxa_irq_syscore_ops);
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@ -438,9 +438,6 @@ static int __init pxa3xx_init(void)
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*/
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NDCR = (NDCR & ~NDCR_ND_ARB_EN) | NDCR_ND_ARB_CNTL;
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if ((ret = pxa_init_dma(IRQ_DMA, 32)))
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return ret;
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pxa3xx_init_pm();
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register_syscore_ops(&pxa_irq_syscore_ops);
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@ -3,8 +3,6 @@
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#
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ccflags-$(CONFIG_ARCH_MMP) := -I$(srctree)/$(src)/include
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obj-$(CONFIG_ARCH_PXA) := dma.o
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obj-$(CONFIG_PXA3xx) += mfp.o
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obj-$(CONFIG_ARCH_MMP) += mfp.o
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@ -1,386 +0,0 @@
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/*
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* linux/arch/arm/plat-pxa/dma.c
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*
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* PXA DMA registration and IRQ dispatching
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*
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* Author: Nicolas Pitre
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* Created: Nov 15, 2001
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* Copyright: MontaVista Software Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/slab.h>
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#include <linux/kernel.h>
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#include <linux/interrupt.h>
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#include <linux/errno.h>
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#include <linux/dma-mapping.h>
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#include <asm/irq.h>
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#include <asm/memory.h>
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#include <mach/hardware.h>
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#include <mach/dma.h>
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#define DMA_DEBUG_NAME "pxa_dma"
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#define DMA_MAX_REQUESTERS 64
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struct dma_channel {
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char *name;
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pxa_dma_prio prio;
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void (*irq_handler)(int, void *);
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void *data;
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spinlock_t lock;
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};
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static struct dma_channel *dma_channels;
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static int num_dma_channels;
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/*
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* Debug fs
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*/
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#ifdef CONFIG_DEBUG_FS
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#include <linux/debugfs.h>
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#include <linux/uaccess.h>
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#include <linux/seq_file.h>
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static struct dentry *dbgfs_root, *dbgfs_state, **dbgfs_chan;
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static int dbg_show_requester_chan(struct seq_file *s, void *p)
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{
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int chan = (int)s->private;
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int i;
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u32 drcmr;
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seq_printf(s, "DMA channel %d requesters list :\n", chan);
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for (i = 0; i < DMA_MAX_REQUESTERS; i++) {
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drcmr = DRCMR(i);
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if ((drcmr & DRCMR_CHLNUM) == chan)
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seq_printf(s, "\tRequester %d (MAPVLD=%d)\n",
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i, !!(drcmr & DRCMR_MAPVLD));
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}
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return 0;
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}
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static inline int dbg_burst_from_dcmd(u32 dcmd)
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{
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int burst = (dcmd >> 16) & 0x3;
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return burst ? 4 << burst : 0;
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}
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static int is_phys_valid(unsigned long addr)
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{
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return pfn_valid(__phys_to_pfn(addr));
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}
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#define DCSR_STR(flag) (dcsr & DCSR_##flag ? #flag" " : "")
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#define DCMD_STR(flag) (dcmd & DCMD_##flag ? #flag" " : "")
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static int dbg_show_descriptors(struct seq_file *s, void *p)
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{
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int chan = (int)s->private;
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int i, max_show = 20, burst, width;
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u32 dcmd;
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unsigned long phys_desc;
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struct pxa_dma_desc *desc;
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unsigned long flags;
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spin_lock_irqsave(&dma_channels[chan].lock, flags);
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phys_desc = DDADR(chan);
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seq_printf(s, "DMA channel %d descriptors :\n", chan);
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seq_printf(s, "[%03d] First descriptor unknown\n", 0);
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for (i = 1; i < max_show && is_phys_valid(phys_desc); i++) {
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desc = phys_to_virt(phys_desc);
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dcmd = desc->dcmd;
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burst = dbg_burst_from_dcmd(dcmd);
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width = (1 << ((dcmd >> 14) & 0x3)) >> 1;
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seq_printf(s, "[%03d] Desc at %08lx(virt %p)\n",
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i, phys_desc, desc);
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seq_printf(s, "\tDDADR = %08x\n", desc->ddadr);
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seq_printf(s, "\tDSADR = %08x\n", desc->dsadr);
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seq_printf(s, "\tDTADR = %08x\n", desc->dtadr);
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seq_printf(s, "\tDCMD = %08x (%s%s%s%s%s%s%sburst=%d width=%d len=%d)\n",
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dcmd,
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DCMD_STR(INCSRCADDR), DCMD_STR(INCTRGADDR),
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DCMD_STR(FLOWSRC), DCMD_STR(FLOWTRG),
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DCMD_STR(STARTIRQEN), DCMD_STR(ENDIRQEN),
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DCMD_STR(ENDIAN), burst, width,
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dcmd & DCMD_LENGTH);
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phys_desc = desc->ddadr;
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}
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if (i == max_show)
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seq_printf(s, "[%03d] Desc at %08lx ... max display reached\n",
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i, phys_desc);
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else
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seq_printf(s, "[%03d] Desc at %08lx is %s\n",
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i, phys_desc, phys_desc == DDADR_STOP ?
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"DDADR_STOP" : "invalid");
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spin_unlock_irqrestore(&dma_channels[chan].lock, flags);
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return 0;
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}
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static int dbg_show_chan_state(struct seq_file *s, void *p)
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{
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int chan = (int)s->private;
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u32 dcsr, dcmd;
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int burst, width;
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static char *str_prio[] = { "high", "normal", "low" };
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dcsr = DCSR(chan);
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dcmd = DCMD(chan);
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burst = dbg_burst_from_dcmd(dcmd);
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width = (1 << ((dcmd >> 14) & 0x3)) >> 1;
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seq_printf(s, "DMA channel %d\n", chan);
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seq_printf(s, "\tPriority : %s\n", str_prio[dma_channels[chan].prio]);
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seq_printf(s, "\tUnaligned transfer bit: %s\n",
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DALGN & (1 << chan) ? "yes" : "no");
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seq_printf(s, "\tDCSR = %08x (%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s)\n",
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dcsr, DCSR_STR(RUN), DCSR_STR(NODESC),
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DCSR_STR(STOPIRQEN), DCSR_STR(EORIRQEN),
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DCSR_STR(EORJMPEN), DCSR_STR(EORSTOPEN),
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DCSR_STR(SETCMPST), DCSR_STR(CLRCMPST),
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DCSR_STR(CMPST), DCSR_STR(EORINTR), DCSR_STR(REQPEND),
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DCSR_STR(STOPSTATE), DCSR_STR(ENDINTR),
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DCSR_STR(STARTINTR), DCSR_STR(BUSERR));
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seq_printf(s, "\tDCMD = %08x (%s%s%s%s%s%s%sburst=%d width=%d len=%d)\n",
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dcmd,
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DCMD_STR(INCSRCADDR), DCMD_STR(INCTRGADDR),
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DCMD_STR(FLOWSRC), DCMD_STR(FLOWTRG),
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DCMD_STR(STARTIRQEN), DCMD_STR(ENDIRQEN),
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DCMD_STR(ENDIAN), burst, width, dcmd & DCMD_LENGTH);
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seq_printf(s, "\tDSADR = %08x\n", DSADR(chan));
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seq_printf(s, "\tDTADR = %08x\n", DTADR(chan));
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seq_printf(s, "\tDDADR = %08x\n", DDADR(chan));
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return 0;
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}
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static int dbg_show_state(struct seq_file *s, void *p)
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{
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/* basic device status */
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seq_puts(s, "DMA engine status\n");
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seq_printf(s, "\tChannel number: %d\n", num_dma_channels);
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return 0;
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}
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#define DBGFS_FUNC_DECL(name) \
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static int dbg_open_##name(struct inode *inode, struct file *file) \
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{ \
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return single_open(file, dbg_show_##name, inode->i_private); \
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} \
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static const struct file_operations dbg_fops_##name = { \
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.owner = THIS_MODULE, \
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.open = dbg_open_##name, \
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.llseek = seq_lseek, \
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.read = seq_read, \
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.release = single_release, \
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}
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DBGFS_FUNC_DECL(state);
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DBGFS_FUNC_DECL(chan_state);
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DBGFS_FUNC_DECL(descriptors);
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DBGFS_FUNC_DECL(requester_chan);
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static struct dentry *pxa_dma_dbg_alloc_chan(int ch, struct dentry *chandir)
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{
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char chan_name[11];
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struct dentry *chan, *chan_state = NULL, *chan_descr = NULL;
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struct dentry *chan_reqs = NULL;
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void *dt;
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scnprintf(chan_name, sizeof(chan_name), "%d", ch);
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chan = debugfs_create_dir(chan_name, chandir);
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dt = (void *)ch;
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if (chan)
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chan_state = debugfs_create_file("state", 0400, chan, dt,
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&dbg_fops_chan_state);
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if (chan_state)
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chan_descr = debugfs_create_file("descriptors", 0400, chan, dt,
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&dbg_fops_descriptors);
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if (chan_descr)
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chan_reqs = debugfs_create_file("requesters", 0400, chan, dt,
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&dbg_fops_requester_chan);
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if (!chan_reqs)
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goto err_state;
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return chan;
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err_state:
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debugfs_remove_recursive(chan);
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return NULL;
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}
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static void pxa_dma_init_debugfs(void)
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{
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int i;
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struct dentry *chandir;
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dbgfs_root = debugfs_create_dir(DMA_DEBUG_NAME, NULL);
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if (IS_ERR(dbgfs_root) || !dbgfs_root)
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goto err_root;
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dbgfs_state = debugfs_create_file("state", 0400, dbgfs_root, NULL,
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&dbg_fops_state);
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if (!dbgfs_state)
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goto err_state;
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dbgfs_chan = kmalloc(sizeof(*dbgfs_state) * num_dma_channels,
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GFP_KERNEL);
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if (!dbgfs_chan)
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goto err_alloc;
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chandir = debugfs_create_dir("channels", dbgfs_root);
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if (!chandir)
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goto err_chandir;
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for (i = 0; i < num_dma_channels; i++) {
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dbgfs_chan[i] = pxa_dma_dbg_alloc_chan(i, chandir);
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if (!dbgfs_chan[i])
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goto err_chans;
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}
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return;
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err_chans:
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err_chandir:
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kfree(dbgfs_chan);
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err_alloc:
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err_state:
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debugfs_remove_recursive(dbgfs_root);
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err_root:
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pr_err("pxa_dma: debugfs is not available\n");
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}
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static void __exit pxa_dma_cleanup_debugfs(void)
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{
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debugfs_remove_recursive(dbgfs_root);
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}
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#else
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static inline void pxa_dma_init_debugfs(void) {}
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static inline void pxa_dma_cleanup_debugfs(void) {}
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#endif
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int pxa_request_dma (char *name, pxa_dma_prio prio,
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void (*irq_handler)(int, void *),
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void *data)
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{
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unsigned long flags;
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int i, found = 0;
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/* basic sanity checks */
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if (!name || !irq_handler)
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return -EINVAL;
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local_irq_save(flags);
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do {
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/* try grabbing a DMA channel with the requested priority */
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for (i = 0; i < num_dma_channels; i++) {
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if ((dma_channels[i].prio == prio) &&
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!dma_channels[i].name &&
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!pxad_toggle_reserved_channel(i)) {
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found = 1;
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break;
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}
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}
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/* if requested prio group is full, try a hier priority */
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} while (!found && prio--);
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if (found) {
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DCSR(i) = DCSR_STARTINTR|DCSR_ENDINTR|DCSR_BUSERR;
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dma_channels[i].name = name;
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dma_channels[i].irq_handler = irq_handler;
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dma_channels[i].data = data;
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} else {
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printk (KERN_WARNING "No more available DMA channels for %s\n", name);
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i = -ENODEV;
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}
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local_irq_restore(flags);
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return i;
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}
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EXPORT_SYMBOL(pxa_request_dma);
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void pxa_free_dma (int dma_ch)
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{
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unsigned long flags;
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if (!dma_channels[dma_ch].name) {
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printk (KERN_CRIT
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"%s: trying to free channel %d which is already freed\n",
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__func__, dma_ch);
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return;
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}
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local_irq_save(flags);
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DCSR(dma_ch) = DCSR_STARTINTR|DCSR_ENDINTR|DCSR_BUSERR;
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dma_channels[dma_ch].name = NULL;
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pxad_toggle_reserved_channel(dma_ch);
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local_irq_restore(flags);
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}
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EXPORT_SYMBOL(pxa_free_dma);
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static irqreturn_t dma_irq_handler(int irq, void *dev_id)
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{
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int i, dint = DINT, done = 0;
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struct dma_channel *channel;
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while (dint) {
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i = __ffs(dint);
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dint &= (dint - 1);
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channel = &dma_channels[i];
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if (channel->name && channel->irq_handler) {
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channel->irq_handler(i, channel->data);
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done++;
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}
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}
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if (done)
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return IRQ_HANDLED;
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else
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return IRQ_NONE;
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}
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int __init pxa_init_dma(int irq, int num_ch)
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{
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int i, ret;
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dma_channels = kzalloc(sizeof(struct dma_channel) * num_ch, GFP_KERNEL);
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if (dma_channels == NULL)
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return -ENOMEM;
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/* dma channel priorities on pxa2xx processors:
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* ch 0 - 3, 16 - 19 <--> (0) DMA_PRIO_HIGH
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* ch 4 - 7, 20 - 23 <--> (1) DMA_PRIO_MEDIUM
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* ch 8 - 15, 24 - 31 <--> (2) DMA_PRIO_LOW
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*/
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for (i = 0; i < num_ch; i++) {
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DCSR(i) = 0;
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dma_channels[i].prio = min((i & 0xf) >> 2, DMA_PRIO_LOW);
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spin_lock_init(&dma_channels[i].lock);
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}
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ret = request_irq(irq, dma_irq_handler, IRQF_SHARED, "DMA",
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dma_channels);
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if (ret) {
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printk (KERN_CRIT "Wow! Can't register IRQ for DMA\n");
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kfree(dma_channels);
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return ret;
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}
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num_dma_channels = num_ch;
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pxa_dma_init_debugfs();
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return 0;
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}
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@ -1,100 +0,0 @@
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#ifndef __PLAT_DMA_H
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#define __PLAT_DMA_H
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#define DMAC_REG(x) (*((volatile u32 *)(DMAC_REGS_VIRT + (x))))
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#define DCSR(n) DMAC_REG((n) << 2)
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#define DALGN DMAC_REG(0x00a0) /* DMA Alignment Register */
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#define DINT DMAC_REG(0x00f0) /* DMA Interrupt Register */
|
||||
#define DDADR(n) DMAC_REG(0x0200 + ((n) << 4))
|
||||
#define DSADR(n) DMAC_REG(0x0204 + ((n) << 4))
|
||||
#define DTADR(n) DMAC_REG(0x0208 + ((n) << 4))
|
||||
#define DCMD(n) DMAC_REG(0x020c + ((n) << 4))
|
||||
#define DRCMR(n) DMAC_REG((((n) < 64) ? 0x0100 : 0x1100) + \
|
||||
(((n) & 0x3f) << 2))
|
||||
|
||||
#define DCSR_RUN (1 << 31) /* Run Bit (read / write) */
|
||||
#define DCSR_NODESC (1 << 30) /* No-Descriptor Fetch (read / write) */
|
||||
#define DCSR_STOPIRQEN (1 << 29) /* Stop Interrupt Enable (read / write) */
|
||||
#define DCSR_REQPEND (1 << 8) /* Request Pending (read-only) */
|
||||
#define DCSR_STOPSTATE (1 << 3) /* Stop State (read-only) */
|
||||
#define DCSR_ENDINTR (1 << 2) /* End Interrupt (read / write) */
|
||||
#define DCSR_STARTINTR (1 << 1) /* Start Interrupt (read / write) */
|
||||
#define DCSR_BUSERR (1 << 0) /* Bus Error Interrupt (read / write) */
|
||||
|
||||
#define DCSR_EORIRQEN (1 << 28) /* End of Receive Interrupt Enable (R/W) */
|
||||
#define DCSR_EORJMPEN (1 << 27) /* Jump to next descriptor on EOR */
|
||||
#define DCSR_EORSTOPEN (1 << 26) /* STOP on an EOR */
|
||||
#define DCSR_SETCMPST (1 << 25) /* Set Descriptor Compare Status */
|
||||
#define DCSR_CLRCMPST (1 << 24) /* Clear Descriptor Compare Status */
|
||||
#define DCSR_CMPST (1 << 10) /* The Descriptor Compare Status */
|
||||
#define DCSR_EORINTR (1 << 9) /* The end of Receive */
|
||||
|
||||
#define DRCMR_MAPVLD (1 << 7) /* Map Valid (read / write) */
|
||||
#define DRCMR_CHLNUM 0x1f /* mask for Channel Number (read / write) */
|
||||
|
||||
#define DDADR_DESCADDR 0xfffffff0 /* Address of next descriptor (mask) */
|
||||
#define DDADR_STOP (1 << 0) /* Stop (read / write) */
|
||||
|
||||
#define DCMD_INCSRCADDR (1 << 31) /* Source Address Increment Setting. */
|
||||
#define DCMD_INCTRGADDR (1 << 30) /* Target Address Increment Setting. */
|
||||
#define DCMD_FLOWSRC (1 << 29) /* Flow Control by the source. */
|
||||
#define DCMD_FLOWTRG (1 << 28) /* Flow Control by the target. */
|
||||
#define DCMD_STARTIRQEN (1 << 22) /* Start Interrupt Enable */
|
||||
#define DCMD_ENDIRQEN (1 << 21) /* End Interrupt Enable */
|
||||
#define DCMD_ENDIAN (1 << 18) /* Device Endian-ness. */
|
||||
#define DCMD_BURST8 (1 << 16) /* 8 byte burst */
|
||||
#define DCMD_BURST16 (2 << 16) /* 16 byte burst */
|
||||
#define DCMD_BURST32 (3 << 16) /* 32 byte burst */
|
||||
#define DCMD_WIDTH1 (1 << 14) /* 1 byte width */
|
||||
#define DCMD_WIDTH2 (2 << 14) /* 2 byte width (HalfWord) */
|
||||
#define DCMD_WIDTH4 (3 << 14) /* 4 byte width (Word) */
|
||||
#define DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */
|
||||
|
||||
/*
|
||||
* Descriptor structure for PXA's DMA engine
|
||||
* Note: this structure must always be aligned to a 16-byte boundary.
|
||||
*/
|
||||
|
||||
typedef struct pxa_dma_desc {
|
||||
volatile u32 ddadr; /* Points to the next descriptor + flags */
|
||||
volatile u32 dsadr; /* DSADR value for the current transfer */
|
||||
volatile u32 dtadr; /* DTADR value for the current transfer */
|
||||
volatile u32 dcmd; /* DCMD value for the current transfer */
|
||||
} pxa_dma_desc;
|
||||
|
||||
typedef enum {
|
||||
DMA_PRIO_HIGH = 0,
|
||||
DMA_PRIO_MEDIUM = 1,
|
||||
DMA_PRIO_LOW = 2
|
||||
} pxa_dma_prio;
|
||||
|
||||
/*
|
||||
* DMA registration
|
||||
*/
|
||||
|
||||
int __init pxa_init_dma(int irq, int num_ch);
|
||||
|
||||
int pxa_request_dma (char *name,
|
||||
pxa_dma_prio prio,
|
||||
void (*irq_handler)(int, void *),
|
||||
void *data);
|
||||
|
||||
void pxa_free_dma (int dma_ch);
|
||||
|
||||
/*
|
||||
* Cooperation with pxa_dma + dmaengine while there remains at least one pxa
|
||||
* driver not converted to dmaengine.
|
||||
*/
|
||||
#if defined(CONFIG_PXA_DMA)
|
||||
extern int pxad_toggle_reserved_channel(int legacy_channel);
|
||||
#else
|
||||
static inline int pxad_toggle_reserved_channel(int legacy_channel)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
extern void __init pxa2xx_set_dmac_info(int nb_channels, int nb_requestors);
|
||||
|
||||
#endif /* __PLAT_DMA_H */
|
||||
Loading…
Reference in New Issue