hollalinux
/
linux-sg2042
mirror of https://github.com/sophgo/linux-riscv.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Allwinner arm64 DT changes for 5.1, take 2 

Our usual round of DT changes for the arm64 Allwinner SoCs:
   - Enabling of the various power supplies on most a64 boards
   - H6 SRAM controller support
   - A64 CSI support
 -----BEGIN PGP SIGNATURE-----
 
 iHUEABYIAB0WIQRcEzekXsqa64kGDp7j7w1vZxhRxQUCXF1ZiQAKCRDj7w1vZxhR
 xeeaAQCuII0MyMyRYhk4XPkjRncEks7A1Fp7u1kjR4VjbNq8JQD+OhCbKMAz4DVv
 T7DeI92HwEO2Dx/ggNMVYDCUDyH55gI=
 =Pd5b
 -----END PGP SIGNATURE-----

Merge tag 'sunxi-dt64-for-5.1-2' of git://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into arm/dt

Allwinner arm64 DT changes for 5.1, take 2

Our usual round of DT changes for the arm64 Allwinner SoCs:
  - Enabling of the various power supplies on most a64 boards
  - H6 SRAM controller support
  - A64 CSI support

* tag 'sunxi-dt64-for-5.1-2' of git://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
  arm64: dts: allwinner: a64: Enable PMIC power supplies on various boards
  arm64: dts: allwinner: a64: teres-i: enable power supplies
  arm64: dts: allwinner: h6: Add support for the SRAM C1 section
  dt-bindings: sram: sunxi: Add compatible for the H6 SRAM C1
  arm64: dts: allwinner: a64: Add A64 CSI controller
  arm64: dts: allwinner: h6: Move GIC device node fix base address ordering

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2019-02-15 15:41:09 +01:00
parent 51098f76dd a24270afa7
commit 175a366f70
9 changed files with 90 additions and 11 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
Documentation/devicetree/bindings/sram/sunxi-sram.txt
View File

@ -63,6 +63,7 @@ The valid sections compatible for H5 are:
The valid sections compatible for H6 are:
- allwinner,sun50i-h6-sram-c, allwinner,sun50i-a64-sram-c
- allwinner,sun50i-h6-sram-c1, allwinner,sun4i-a10-sram-c1
The valid sections compatible for F1C100s are:
- allwinner,suniv-f1c100s-sram-d, allwinner,sun4i-a10-sram-d

8
arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
View File

@ -222,6 +222,14 @@
#include "axp803.dtsi"
&ac_power_supply {
status = "okay";
};
&battery_power_supply {
status = "okay";
};
&reg_aldo1 {
/*
* This regulator also drives the PE pingroup GPIOs,

4
arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts
View File

@ -186,6 +186,10 @@
#include "axp803.dtsi"
&ac_power_supply {
status = "okay";
};
&reg_aldo2 {
regulator-always-on;
regulator-min-microvolt = <1800000>;

8
arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts
View File

@ -177,6 +177,14 @@
#include "axp803.dtsi"
&ac_power_supply {
status = "okay";
};
&battery_power_supply {
status = "okay";
};
&reg_aldo1 {
regulator-always-on;
regulator-min-microvolt = <2800000>;

8
arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts
View File

@ -193,6 +193,14 @@
#include "axp803.dtsi"
&ac_power_supply {
status = "okay";
};
&battery_power_supply {
status = "okay";
};
&reg_aldo1 {
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;

8
arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
View File

@ -169,6 +169,14 @@
#include "axp803.dtsi"
&ac_power_supply {
status = "okay";
};
&battery_power_supply {
status = "okay";
};
&reg_aldo2 {
regulator-always-on;
regulator-min-microvolt = <1800000>;

8
arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts
View File

@ -145,6 +145,14 @@
#include "axp803.dtsi"
&ac_power_supply {
status = "okay";
};
&battery_power_supply {
status = "okay";
};
&reg_aldo1 {
regulator-always-on;
regulator-min-microvolt = <2800000>;

20
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
View File

@ -559,6 +559,12 @@
interrupt-controller;
#interrupt-cells = <3>;
csi_pins: csi-pins {
pins = "PE0", "PE2", "PE3", "PE4", "PE5", "PE6",
"PE7", "PE8", "PE9", "PE10", "PE11";
function = "csi";
};
i2c0_pins: i2c0_pins {
pins = "PH0", "PH1";
function = "i2c0";
@ -926,6 +932,20 @@
status = "disabled";
};
csi: csi@1cb0000 {
compatible = "allwinner,sun50i-a64-csi";
reg = <0x01cb0000 0x1000>;
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_CSI>,
<&ccu CLK_CSI_SCLK>,
<&ccu CLK_DRAM_CSI>;
clock-names = "bus", "mod", "ram";
resets = <&ccu RST_BUS_CSI>;
pinctrl-names = "default";
pinctrl-0 = <&csi_pins>;
status = "disabled";
};
hdmi: hdmi@1ee0000 {
compatible = "allwinner,sun50i-a64-dw-hdmi",
"allwinner,sun8i-a83t-dw-hdmi";

36
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
View File

@ -167,6 +167,20 @@
reg = <0x0000 0x1e000>;
};
};
sram_c1: sram@1a00000 {
compatible = "mmio-sram";
reg = <0x01a00000 0x200000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x01a00000 0x200000>;
ve_sram: sram-section@0 {
compatible = "allwinner,sun50i-h6-sram-c1",
"allwinner,sun4i-a10-sram-c1";
reg = <0x000000 0x200000>;
};
};
};
ccu: clock@3001000 {
@ -178,17 +192,6 @@
#reset-cells = <1>;
};
gic: interrupt-controller@3021000 {
compatible = "arm,gic-400";
reg = <0x03021000 0x1000>,
<0x03022000 0x2000>,
<0x03024000 0x2000>,
<0x03026000 0x2000>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
interrupt-controller;
#interrupt-cells = <3>;
};
pio: pinctrl@300b000 {
compatible = "allwinner,sun50i-h6-pinctrl";
reg = <0x0300b000 0x400>;
@ -239,6 +242,17 @@
};
};
gic: interrupt-controller@3021000 {
compatible = "arm,gic-400";
reg = <0x03021000 0x1000>,
<0x03022000 0x2000>,
<0x03024000 0x2000>,
<0x03026000 0x2000>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
interrupt-controller;
#interrupt-cells = <3>;
};
mmc0: mmc@4020000 {
compatible = "allwinner,sun50i-h6-mmc",
"allwinner,sun50i-a64-mmc";