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microblaze: Clear all MSR flags on the first kernel instruction 

The main reason is bug because of dynamic TLB allocation.
U-BOOT didn't disable dcache and then writing to physical address
from ASM wan't visible for reading through MMU.
Disabling caches and clearing all flags from previous code
is good to do so.

Signed-off-by: Michal Simek <monstr@monstr.eu>
This commit is contained in:
Michal Simek 2011-11-09 15:39:58 +01:00
parent cc5647a64e
commit 173701d774
1 changed files with 2 additions and 3 deletions
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5
arch/microblaze/kernel/head.S
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@ -63,9 +63,7 @@ ENTRY(_start)
real_start: real_start:
#endif #endif
mfs r1, rmsr mts rmsr, r0
andi r1, r1, ~2
mts rmsr, r1
/* /*
* According to Xilinx, msrclr instruction behaves like 'mfs rX,rpc' * According to Xilinx, msrclr instruction behaves like 'mfs rX,rpc'
* if the msrclr instruction is not enabled. We use this to detect * if the msrclr instruction is not enabled. We use this to detect
@ -73,6 +71,7 @@ real_start:
* r8 == 0 - msr instructions are implemented * r8 == 0 - msr instructions are implemented
* r8 != 0 - msr instructions are not implemented * r8 != 0 - msr instructions are not implemented
*/ */
mfs r1, rmsr
msrclr r8, 0 /* clear nothing - just read msr for test */ msrclr r8, 0 /* clear nothing - just read msr for test */
cmpu r8, r8, r1 /* r1 must contain msr reg content */ cmpu r8, r8, r1 /* r1 must contain msr reg content */