ARM: owl: Implement CPU enable-method for S500
Allow to bring up CPU1. Based on LeMaker linux-actions tree. Signed-off-by: Andreas Färber <afaerber@suse.de>
This commit is contained in:
Andreas Färber
parent
872d1ba47b
commit
172067e0bc
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@ -1 +1,4 @@
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obj-y += owl.o
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obj-${CONFIG_SMP} += platsmp.o headsmp.o
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AFLAGS_headsmp.o := -Wa,-march=armv7-a
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@ -0,0 +1,68 @@
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/*
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* Copyright 2012 Actions Semi Inc.
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* Author: Actions Semi, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/linkage.h>
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#include <linux/init.h>
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ENTRY(owl_v7_invalidate_l1)
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mov r0, #0
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mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
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mcr p15, 2, r0, c0, c0, 0
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mrc p15, 1, r0, c0, c0, 0
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ldr r1, =0x7fff
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and r2, r1, r0, lsr #13
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ldr r1, =0x3ff
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and r3, r1, r0, lsr #3 @ NumWays - 1
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add r2, r2, #1 @ NumSets
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and r0, r0, #0x7
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add r0, r0, #4 @ SetShift
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clz r1, r3 @ WayShift
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add r4, r3, #1 @ NumWays
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1: sub r2, r2, #1 @ NumSets--
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mov r3, r4 @ Temp = NumWays
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2: subs r3, r3, #1 @ Temp--
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mov r5, r3, lsl r1
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mov r6, r2, lsl r0
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orr r5, r5, r6 @ Reg = (Temp<<WayShift)|(NumSets<<SetShift)
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mcr p15, 0, r5, c7, c6, 2
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bgt 2b
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cmp r2, #0
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bgt 1b
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dsb
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isb
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mov pc, lr
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ENDPROC(owl_v7_invalidate_l1)
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ENTRY(owl_secondary_startup)
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mrc p15, 0, r0, c0, c0, 5
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and r0, r0, #0xf
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adr r4, 1f
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ldmia r4, {r5, r6}
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sub r4, r4, r5
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add r6, r6, r4
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pen:
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ldr r7, [r6]
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cmp r7, r0
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bne pen
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/*
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* we've been released from the holding pen: secondary_stack
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* should now contain the SVC stack for this core
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*/
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bl owl_v7_invalidate_l1
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b secondary_startup
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1: .long .
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.long pen_release
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@ -0,0 +1,166 @@
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/*
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* Actions Semi Leopard
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*
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* This file is based on arm realview smp platform.
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*
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* Copyright 2012 Actions Semi Inc.
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* Author: Actions Semi, Inc.
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*
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* Copyright (c) 2017 Andreas Färber
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/smp.h>
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#include <asm/cacheflush.h>
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#include <asm/smp_plat.h>
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#include <asm/smp_scu.h>
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#define OWL_CPU1_ADDR 0x50
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#define OWL_CPU1_FLAG 0x5c
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#define OWL_CPUx_FLAG_BOOT 0x55aa
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static void __iomem *scu_base_addr;
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static void __iomem *timer_base_addr;
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static int ncores;
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static DEFINE_SPINLOCK(boot_lock);
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static void write_pen_release(int val)
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{
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pen_release = val;
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smp_wmb();
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__cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release));
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outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1));
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}
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static void s500_smp_secondary_init(unsigned int cpu)
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{
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/*
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* let the primary processor know we're out of the
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* pen, then head off into the C entry point
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*/
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write_pen_release(-1);
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spin_lock(&boot_lock);
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spin_unlock(&boot_lock);
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}
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void owl_secondary_startup(void);
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static int s500_wakeup_secondary(unsigned int cpu)
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{
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if (cpu > 3)
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return -EINVAL;
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switch (cpu) {
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case 2:
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case 3:
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/* CPU2/3 are power-gated */
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return -EINVAL;
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}
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/* wait for CPUx to run to WFE instruction */
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udelay(200);
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writel(virt_to_phys(owl_secondary_startup),
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timer_base_addr + OWL_CPU1_ADDR + (cpu - 1) * 4);
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writel(OWL_CPUx_FLAG_BOOT,
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timer_base_addr + OWL_CPU1_FLAG + (cpu - 1) * 4);
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dsb_sev();
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mb();
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return 0;
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}
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static int s500_smp_boot_secondary(unsigned int cpu, struct task_struct *idle)
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{
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unsigned long timeout;
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int ret;
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ret = s500_wakeup_secondary(cpu);
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if (ret)
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return ret;
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udelay(10);
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spin_lock(&boot_lock);
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/*
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* The secondary processor is waiting to be released from
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* the holding pen - release it, then wait for it to flag
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* that it has been released by resetting pen_release.
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*/
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write_pen_release(cpu_logical_map(cpu));
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smp_send_reschedule(cpu);
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timeout = jiffies + (1 * HZ);
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while (time_before(jiffies, timeout)) {
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if (pen_release == -1)
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break;
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}
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writel(0, timer_base_addr + OWL_CPU1_ADDR + (cpu - 1) * 4);
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writel(0, timer_base_addr + OWL_CPU1_FLAG + (cpu - 1) * 4);
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spin_unlock(&boot_lock);
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return pen_release != -1 ? -ENOSYS : 0;
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}
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static void __init s500_smp_prepare_cpus(unsigned int max_cpus)
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{
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struct device_node *node;
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node = of_find_compatible_node(NULL, NULL, "actions,s500-timer");
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if (!node) {
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pr_err("%s: missing timer\n", __func__);
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return;
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}
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timer_base_addr = of_iomap(node, 0);
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if (!timer_base_addr) {
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pr_err("%s: could not map timer registers\n", __func__);
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return;
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}
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if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) {
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node = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu");
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if (!node) {
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pr_err("%s: missing scu\n", __func__);
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return;
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}
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scu_base_addr = of_iomap(node, 0);
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if (!scu_base_addr) {
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pr_err("%s: could not map scu registers\n", __func__);
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return;
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}
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/*
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* While the number of cpus is gathered from dt, also get the
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* number of cores from the scu to verify this value when
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* booting the cores.
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*/
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ncores = scu_get_core_count(scu_base_addr);
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pr_debug("%s: ncores %d\n", __func__, ncores);
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scu_enable(scu_base_addr);
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}
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}
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static const struct smp_operations s500_smp_ops __initconst = {
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.smp_prepare_cpus = s500_smp_prepare_cpus,
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.smp_secondary_init = s500_smp_secondary_init,
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.smp_boot_secondary = s500_smp_boot_secondary,
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};
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CPU_METHOD_OF_DECLARE(s500_smp, "actions,s500-smp", &s500_smp_ops);
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