MIPS: Lantiq: Add initial support for Lantiq SoCs
Add initial support for Mips based SoCs made by Lantiq. This series will add support for the XWAY family. The series allows booting a minimal system using a initramfs or NOR. Missing drivers and support for Amazon and GPON family will be provided in a later series. [Ralf: Remove some cargo cult programming and fixed formatting.] Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Ralph Hempel <ralph.hempel@lantiq.com> Signed-off-by: David Daney <ddaney@caviumnetworks.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2252/ Patchwork: https://patchwork.linux-mips.org/patch/2371/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
John Crispin
Ralf Baechle
parent
c0a5afb9bc
commit
171bb2f19e
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@ -11,6 +11,7 @@ platforms += dec
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platforms += emma
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platforms += jazz
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platforms += jz4740
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platforms += lantiq
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platforms += lasat
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platforms += loongson
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platforms += mipssim
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@ -212,6 +212,23 @@ config MACH_JZ4740
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select HAVE_PWM
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select HAVE_CLK
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config LANTIQ
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bool "Lantiq based platforms"
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select DMA_NONCOHERENT
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select IRQ_CPU
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select CEVT_R4K
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select CSRC_R4K
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select SYS_HAS_CPU_MIPS32_R1
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select SYS_HAS_CPU_MIPS32_R2
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select SYS_SUPPORTS_BIG_ENDIAN
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select SYS_SUPPORTS_32BIT_KERNEL
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select SYS_SUPPORTS_MULTITHREADING
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select SYS_HAS_EARLY_PRINTK
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select ARCH_REQUIRE_GPIOLIB
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select SWAP_IO_SPACE
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select BOOT_RAW
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select HAVE_CLK
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config LASAT
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bool "LASAT Networks platforms"
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select CEVT_R4K
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@ -0,0 +1,63 @@
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/*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*
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* Copyright (C) 2010 John Crispin <blogic@openwrt.org>
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*/
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#ifndef _LANTIQ_H__
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#define _LANTIQ_H__
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#include <linux/irq.h>
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/* generic reg access functions */
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#define ltq_r32(reg) __raw_readl(reg)
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#define ltq_w32(val, reg) __raw_writel(val, reg)
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#define ltq_w32_mask(clear, set, reg) \
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ltq_w32((ltq_r32(reg) & ~(clear)) | (set), reg)
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#define ltq_r8(reg) __raw_readb(reg)
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#define ltq_w8(val, reg) __raw_writeb(val, reg)
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/* register access macros for EBU and CGU */
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#define ltq_ebu_w32(x, y) ltq_w32((x), ltq_ebu_membase + (y))
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#define ltq_ebu_r32(x) ltq_r32(ltq_ebu_membase + (x))
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#define ltq_cgu_w32(x, y) ltq_w32((x), ltq_cgu_membase + (y))
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#define ltq_cgu_r32(x) ltq_r32(ltq_cgu_membase + (x))
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extern __iomem void *ltq_ebu_membase;
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extern __iomem void *ltq_cgu_membase;
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extern unsigned int ltq_get_cpu_ver(void);
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extern unsigned int ltq_get_soc_type(void);
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/* clock speeds */
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#define CLOCK_60M 60000000
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#define CLOCK_83M 83333333
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#define CLOCK_111M 111111111
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#define CLOCK_133M 133333333
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#define CLOCK_167M 166666667
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#define CLOCK_200M 200000000
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#define CLOCK_266M 266666666
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#define CLOCK_333M 333333333
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#define CLOCK_400M 400000000
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/* spinlock all ebu i/o */
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extern spinlock_t ebu_lock;
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/* some irq helpers */
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extern void ltq_disable_irq(struct irq_data *data);
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extern void ltq_mask_and_ack_irq(struct irq_data *data);
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extern void ltq_enable_irq(struct irq_data *data);
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/* find out what caused the last cpu reset */
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extern int ltq_reset_cause(void);
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#define LTQ_RST_CAUSE_WDTRST 0x20
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#define IOPORT_RESOURCE_START 0x10000000
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#define IOPORT_RESOURCE_END 0xffffffff
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#define IOMEM_RESOURCE_START 0x10000000
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#define IOMEM_RESOURCE_END 0xffffffff
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#define LTQ_FLASH_START 0x10000000
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#define LTQ_FLASH_MAX 0x04000000
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#endif
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@ -0,0 +1,24 @@
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/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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*/
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#ifndef __ASM_MIPS_MACH_LANTIQ_WAR_H
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#define __ASM_MIPS_MACH_LANTIQ_WAR_H
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#define R4600_V1_INDEX_ICACHEOP_WAR 0
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#define R4600_V1_HIT_CACHEOP_WAR 0
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#define R4600_V2_HIT_CACHEOP_WAR 0
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#define R5432_CP0_INTERRUPT_WAR 0
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#define BCM1250_M3_WAR 0
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#define SIBYTE_1956_WAR 0
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#define MIPS4K_ICACHE_REFILL_WAR 0
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#define MIPS_CACHE_SYNC_WAR 0
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#define TX49XX_ICACHE_INDEX_INV_WAR 0
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#define RM9000_CDEX_SMP_WAR 0
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#define ICACHE_REFILLS_WORKAROUND_WAR 0
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#define R10000_LLSC_WAR 0
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#define MIPS34K_MISSED_ITLB_WAR 0
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#endif
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@ -0,0 +1,9 @@
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# Copyright (C) 2010 John Crispin <blogic@openwrt.org>
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#
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# This program is free software; you can redistribute it and/or modify it
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# under the terms of the GNU General Public License version 2 as published
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# by the Free Software Foundation.
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obj-y := irq.o setup.o clk.o prom.o
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obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
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@ -0,0 +1,7 @@
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#
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# Lantiq
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#
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platform-$(CONFIG_LANTIQ) += lantiq/
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cflags-$(CONFIG_LANTIQ) += -I$(srctree)/arch/mips/include/asm/mach-lantiq
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load-$(CONFIG_LANTIQ) = 0xffffffff80002000
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@ -0,0 +1,140 @@
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/*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*
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* Copyright (C) 2010 Thomas Langer <thomas.langer@lantiq.com>
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* Copyright (C) 2010 John Crispin <blogic@openwrt.org>
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*/
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/list.h>
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#include <asm/time.h>
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#include <asm/irq.h>
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#include <asm/div64.h>
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#include <lantiq_soc.h>
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#include "clk.h"
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struct clk {
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const char *name;
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unsigned long rate;
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unsigned long (*get_rate) (void);
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};
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static struct clk *cpu_clk;
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static int cpu_clk_cnt;
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/* lantiq socs have 3 static clocks */
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static struct clk cpu_clk_generic[] = {
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{
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.name = "cpu",
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.get_rate = ltq_get_cpu_hz,
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}, {
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.name = "fpi",
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.get_rate = ltq_get_fpi_hz,
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}, {
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.name = "io",
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.get_rate = ltq_get_io_region_clock,
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},
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};
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static struct resource ltq_cgu_resource = {
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.name = "cgu",
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.start = LTQ_CGU_BASE_ADDR,
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.end = LTQ_CGU_BASE_ADDR + LTQ_CGU_SIZE - 1,
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.flags = IORESOURCE_MEM,
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};
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/* remapped clock register range */
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void __iomem *ltq_cgu_membase;
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void clk_init(void)
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{
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cpu_clk = cpu_clk_generic;
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cpu_clk_cnt = ARRAY_SIZE(cpu_clk_generic);
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}
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static inline int clk_good(struct clk *clk)
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{
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return clk && !IS_ERR(clk);
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}
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unsigned long clk_get_rate(struct clk *clk)
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{
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if (unlikely(!clk_good(clk)))
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return 0;
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if (clk->rate != 0)
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return clk->rate;
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if (clk->get_rate != NULL)
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return clk->get_rate();
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return 0;
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}
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EXPORT_SYMBOL(clk_get_rate);
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struct clk *clk_get(struct device *dev, const char *id)
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{
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int i;
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for (i = 0; i < cpu_clk_cnt; i++)
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if (!strcmp(id, cpu_clk[i].name))
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return &cpu_clk[i];
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BUG();
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return ERR_PTR(-ENOENT);
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}
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EXPORT_SYMBOL(clk_get);
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void clk_put(struct clk *clk)
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{
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/* not used */
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}
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EXPORT_SYMBOL(clk_put);
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static inline u32 ltq_get_counter_resolution(void)
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{
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u32 res;
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__asm__ __volatile__(
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".set push\n"
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".set mips32r2\n"
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"rdhwr %0, $3\n"
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".set pop\n"
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: "=&r" (res)
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: /* no input */
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: "memory");
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return res;
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}
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void __init plat_time_init(void)
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{
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struct clk *clk;
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if (insert_resource(&iomem_resource, <q_cgu_resource) < 0)
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panic("Failed to insert cgu memory\n");
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if (request_mem_region(ltq_cgu_resource.start,
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resource_size(<q_cgu_resource), "cgu") < 0)
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panic("Failed to request cgu memory\n");
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ltq_cgu_membase = ioremap_nocache(ltq_cgu_resource.start,
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resource_size(<q_cgu_resource));
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if (!ltq_cgu_membase) {
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pr_err("Failed to remap cgu memory\n");
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unreachable();
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}
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clk = clk_get(0, "cpu");
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mips_hpt_frequency = clk_get_rate(clk) / ltq_get_counter_resolution();
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write_c0_compare(read_c0_count());
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clk_put(clk);
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}
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@ -0,0 +1,18 @@
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/*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*
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* Copyright (C) 2010 John Crispin <blogic@openwrt.org>
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*/
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#ifndef _LTQ_CLK_H__
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#define _LTQ_CLK_H__
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extern void clk_init(void);
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extern unsigned long ltq_get_cpu_hz(void);
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extern unsigned long ltq_get_fpi_hz(void);
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extern unsigned long ltq_get_io_region_clock(void);
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#endif
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@ -0,0 +1,33 @@
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/*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*
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* Copyright (C) 2010 John Crispin <blogic@openwrt.org>
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*/
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#include <linux/init.h>
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#include <linux/cpu.h>
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#include <lantiq.h>
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#include <lantiq_soc.h>
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/* no ioremap possible at this early stage, lets use KSEG1 instead */
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#define LTQ_ASC_BASE KSEG1ADDR(LTQ_ASC1_BASE_ADDR)
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#define ASC_BUF 1024
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#define LTQ_ASC_FSTAT ((u32 *)(LTQ_ASC_BASE + 0x0048))
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#define LTQ_ASC_TBUF ((u32 *)(LTQ_ASC_BASE + 0x0020))
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#define TXMASK 0x3F00
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#define TXOFFSET 8
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void prom_putchar(char c)
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{
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unsigned long flags;
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local_irq_save(flags);
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do { } while ((ltq_r32(LTQ_ASC_FSTAT) & TXMASK) >> TXOFFSET);
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if (c == '\n')
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ltq_w32('\r', LTQ_ASC_TBUF);
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ltq_w32(c, LTQ_ASC_TBUF);
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local_irq_restore(flags);
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}
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@ -0,0 +1,326 @@
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/*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*
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* Copyright (C) 2010 John Crispin <blogic@openwrt.org>
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* Copyright (C) 2010 Thomas Langer <thomas.langer@lantiq.com>
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*/
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#include <linux/interrupt.h>
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#include <linux/ioport.h>
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#include <asm/bootinfo.h>
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#include <asm/irq_cpu.h>
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#include <lantiq_soc.h>
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#include <irq.h>
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/* register definitions */
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#define LTQ_ICU_IM0_ISR 0x0000
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#define LTQ_ICU_IM0_IER 0x0008
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#define LTQ_ICU_IM0_IOSR 0x0010
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#define LTQ_ICU_IM0_IRSR 0x0018
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#define LTQ_ICU_IM0_IMR 0x0020
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#define LTQ_ICU_IM1_ISR 0x0028
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#define LTQ_ICU_OFFSET (LTQ_ICU_IM1_ISR - LTQ_ICU_IM0_ISR)
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#define LTQ_EIU_EXIN_C 0x0000
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#define LTQ_EIU_EXIN_INIC 0x0004
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#define LTQ_EIU_EXIN_INEN 0x000C
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/* irq numbers used by the external interrupt unit (EIU) */
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#define LTQ_EIU_IR0 (INT_NUM_IM4_IRL0 + 30)
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#define LTQ_EIU_IR1 (INT_NUM_IM3_IRL0 + 31)
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#define LTQ_EIU_IR2 (INT_NUM_IM1_IRL0 + 26)
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#define LTQ_EIU_IR3 INT_NUM_IM1_IRL0
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#define LTQ_EIU_IR4 (INT_NUM_IM1_IRL0 + 1)
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#define LTQ_EIU_IR5 (INT_NUM_IM1_IRL0 + 2)
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#define LTQ_EIU_IR6 (INT_NUM_IM2_IRL0 + 30)
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#define MAX_EIU 6
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/* irqs generated by device attached to the EBU need to be acked in
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* a special manner
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*/
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#define LTQ_ICU_EBU_IRQ 22
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#define ltq_icu_w32(x, y) ltq_w32((x), ltq_icu_membase + (y))
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#define ltq_icu_r32(x) ltq_r32(ltq_icu_membase + (x))
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#define ltq_eiu_w32(x, y) ltq_w32((x), ltq_eiu_membase + (y))
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#define ltq_eiu_r32(x) ltq_r32(ltq_eiu_membase + (x))
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static unsigned short ltq_eiu_irq[MAX_EIU] = {
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LTQ_EIU_IR0,
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LTQ_EIU_IR1,
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LTQ_EIU_IR2,
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LTQ_EIU_IR3,
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LTQ_EIU_IR4,
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LTQ_EIU_IR5,
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};
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static struct resource ltq_icu_resource = {
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.name = "icu",
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.start = LTQ_ICU_BASE_ADDR,
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.end = LTQ_ICU_BASE_ADDR + LTQ_ICU_SIZE - 1,
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.flags = IORESOURCE_MEM,
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};
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static struct resource ltq_eiu_resource = {
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.name = "eiu",
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.start = LTQ_EIU_BASE_ADDR,
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.end = LTQ_EIU_BASE_ADDR + LTQ_ICU_SIZE - 1,
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.flags = IORESOURCE_MEM,
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};
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static void __iomem *ltq_icu_membase;
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static void __iomem *ltq_eiu_membase;
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void ltq_disable_irq(struct irq_data *d)
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{
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u32 ier = LTQ_ICU_IM0_IER;
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int irq_nr = d->irq - INT_NUM_IRQ0;
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ier += LTQ_ICU_OFFSET * (irq_nr / INT_NUM_IM_OFFSET);
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irq_nr %= INT_NUM_IM_OFFSET;
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ltq_icu_w32(ltq_icu_r32(ier) & ~(1 << irq_nr), ier);
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}
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void ltq_mask_and_ack_irq(struct irq_data *d)
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{
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u32 ier = LTQ_ICU_IM0_IER;
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u32 isr = LTQ_ICU_IM0_ISR;
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int irq_nr = d->irq - INT_NUM_IRQ0;
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ier += LTQ_ICU_OFFSET * (irq_nr / INT_NUM_IM_OFFSET);
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isr += LTQ_ICU_OFFSET * (irq_nr / INT_NUM_IM_OFFSET);
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irq_nr %= INT_NUM_IM_OFFSET;
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ltq_icu_w32(ltq_icu_r32(ier) & ~(1 << irq_nr), ier);
|
||||
ltq_icu_w32((1 << irq_nr), isr);
|
||||
}
|
||||
|
||||
static void ltq_ack_irq(struct irq_data *d)
|
||||
{
|
||||
u32 isr = LTQ_ICU_IM0_ISR;
|
||||
int irq_nr = d->irq - INT_NUM_IRQ0;
|
||||
|
||||
isr += LTQ_ICU_OFFSET * (irq_nr / INT_NUM_IM_OFFSET);
|
||||
irq_nr %= INT_NUM_IM_OFFSET;
|
||||
ltq_icu_w32((1 << irq_nr), isr);
|
||||
}
|
||||
|
||||
void ltq_enable_irq(struct irq_data *d)
|
||||
{
|
||||
u32 ier = LTQ_ICU_IM0_IER;
|
||||
int irq_nr = d->irq - INT_NUM_IRQ0;
|
||||
|
||||
ier += LTQ_ICU_OFFSET * (irq_nr / INT_NUM_IM_OFFSET);
|
||||
irq_nr %= INT_NUM_IM_OFFSET;
|
||||
ltq_icu_w32(ltq_icu_r32(ier) | (1 << irq_nr), ier);
|
||||
}
|
||||
|
||||
static unsigned int ltq_startup_eiu_irq(struct irq_data *d)
|
||||
{
|
||||
int i;
|
||||
int irq_nr = d->irq - INT_NUM_IRQ0;
|
||||
|
||||
ltq_enable_irq(d);
|
||||
for (i = 0; i < MAX_EIU; i++) {
|
||||
if (irq_nr == ltq_eiu_irq[i]) {
|
||||
/* low level - we should really handle set_type */
|
||||
ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_C) |
|
||||
(0x6 << (i * 4)), LTQ_EIU_EXIN_C);
|
||||
/* clear all pending */
|
||||
ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INIC) & ~(1 << i),
|
||||
LTQ_EIU_EXIN_INIC);
|
||||
/* enable */
|
||||
ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INEN) | (1 << i),
|
||||
LTQ_EIU_EXIN_INEN);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void ltq_shutdown_eiu_irq(struct irq_data *d)
|
||||
{
|
||||
int i;
|
||||
int irq_nr = d->irq - INT_NUM_IRQ0;
|
||||
|
||||
ltq_disable_irq(d);
|
||||
for (i = 0; i < MAX_EIU; i++) {
|
||||
if (irq_nr == ltq_eiu_irq[i]) {
|
||||
/* disable */
|
||||
ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INEN) & ~(1 << i),
|
||||
LTQ_EIU_EXIN_INEN);
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static struct irq_chip ltq_irq_type = {
|
||||
"icu",
|
||||
.irq_enable = ltq_enable_irq,
|
||||
.irq_disable = ltq_disable_irq,
|
||||
.irq_unmask = ltq_enable_irq,
|
||||
.irq_ack = ltq_ack_irq,
|
||||
.irq_mask = ltq_disable_irq,
|
||||
.irq_mask_ack = ltq_mask_and_ack_irq,
|
||||
};
|
||||
|
||||
static struct irq_chip ltq_eiu_type = {
|
||||
"eiu",
|
||||
.irq_startup = ltq_startup_eiu_irq,
|
||||
.irq_shutdown = ltq_shutdown_eiu_irq,
|
||||
.irq_enable = ltq_enable_irq,
|
||||
.irq_disable = ltq_disable_irq,
|
||||
.irq_unmask = ltq_enable_irq,
|
||||
.irq_ack = ltq_ack_irq,
|
||||
.irq_mask = ltq_disable_irq,
|
||||
.irq_mask_ack = ltq_mask_and_ack_irq,
|
||||
};
|
||||
|
||||
static void ltq_hw_irqdispatch(int module)
|
||||
{
|
||||
u32 irq;
|
||||
|
||||
irq = ltq_icu_r32(LTQ_ICU_IM0_IOSR + (module * LTQ_ICU_OFFSET));
|
||||
if (irq == 0)
|
||||
return;
|
||||
|
||||
/* silicon bug causes only the msb set to 1 to be valid. all
|
||||
* other bits might be bogus
|
||||
*/
|
||||
irq = __fls(irq);
|
||||
do_IRQ((int)irq + INT_NUM_IM0_IRL0 + (INT_NUM_IM_OFFSET * module));
|
||||
|
||||
/* if this is a EBU irq, we need to ack it or get a deadlock */
|
||||
if ((irq == LTQ_ICU_EBU_IRQ) && (module == 0))
|
||||
ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_PCC_ISTAT) | 0x10,
|
||||
LTQ_EBU_PCC_ISTAT);
|
||||
}
|
||||
|
||||
#define DEFINE_HWx_IRQDISPATCH(x) \
|
||||
static void ltq_hw ## x ## _irqdispatch(void) \
|
||||
{ \
|
||||
ltq_hw_irqdispatch(x); \
|
||||
}
|
||||
DEFINE_HWx_IRQDISPATCH(0)
|
||||
DEFINE_HWx_IRQDISPATCH(1)
|
||||
DEFINE_HWx_IRQDISPATCH(2)
|
||||
DEFINE_HWx_IRQDISPATCH(3)
|
||||
DEFINE_HWx_IRQDISPATCH(4)
|
||||
|
||||
static void ltq_hw5_irqdispatch(void)
|
||||
{
|
||||
do_IRQ(MIPS_CPU_TIMER_IRQ);
|
||||
}
|
||||
|
||||
asmlinkage void plat_irq_dispatch(void)
|
||||
{
|
||||
unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
|
||||
unsigned int i;
|
||||
|
||||
if (pending & CAUSEF_IP7) {
|
||||
do_IRQ(MIPS_CPU_TIMER_IRQ);
|
||||
goto out;
|
||||
} else {
|
||||
for (i = 0; i < 5; i++) {
|
||||
if (pending & (CAUSEF_IP2 << i)) {
|
||||
ltq_hw_irqdispatch(i);
|
||||
goto out;
|
||||
}
|
||||
}
|
||||
}
|
||||
pr_alert("Spurious IRQ: CAUSE=0x%08x\n", read_c0_status());
|
||||
|
||||
out:
|
||||
return;
|
||||
}
|
||||
|
||||
static struct irqaction cascade = {
|
||||
.handler = no_action,
|
||||
.flags = IRQF_DISABLED,
|
||||
.name = "cascade",
|
||||
};
|
||||
|
||||
void __init arch_init_irq(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
if (insert_resource(&iomem_resource, <q_icu_resource) < 0)
|
||||
panic("Failed to insert icu memory\n");
|
||||
|
||||
if (request_mem_region(ltq_icu_resource.start,
|
||||
resource_size(<q_icu_resource), "icu") < 0)
|
||||
panic("Failed to request icu memory\n");
|
||||
|
||||
ltq_icu_membase = ioremap_nocache(ltq_icu_resource.start,
|
||||
resource_size(<q_icu_resource));
|
||||
if (!ltq_icu_membase)
|
||||
panic("Failed to remap icu memory\n");
|
||||
|
||||
if (insert_resource(&iomem_resource, <q_eiu_resource) < 0)
|
||||
panic("Failed to insert eiu memory\n");
|
||||
|
||||
if (request_mem_region(ltq_eiu_resource.start,
|
||||
resource_size(<q_eiu_resource), "eiu") < 0)
|
||||
panic("Failed to request eiu memory\n");
|
||||
|
||||
ltq_eiu_membase = ioremap_nocache(ltq_eiu_resource.start,
|
||||
resource_size(<q_eiu_resource));
|
||||
if (!ltq_eiu_membase)
|
||||
panic("Failed to remap eiu memory\n");
|
||||
|
||||
/* make sure all irqs are turned off by default */
|
||||
for (i = 0; i < 5; i++)
|
||||
ltq_icu_w32(0, LTQ_ICU_IM0_IER + (i * LTQ_ICU_OFFSET));
|
||||
|
||||
/* clear all possibly pending interrupts */
|
||||
ltq_icu_w32(~0, LTQ_ICU_IM0_ISR + (i * LTQ_ICU_OFFSET));
|
||||
|
||||
mips_cpu_irq_init();
|
||||
|
||||
for (i = 2; i <= 6; i++)
|
||||
setup_irq(i, &cascade);
|
||||
|
||||
if (cpu_has_vint) {
|
||||
pr_info("Setting up vectored interrupts\n");
|
||||
set_vi_handler(2, ltq_hw0_irqdispatch);
|
||||
set_vi_handler(3, ltq_hw1_irqdispatch);
|
||||
set_vi_handler(4, ltq_hw2_irqdispatch);
|
||||
set_vi_handler(5, ltq_hw3_irqdispatch);
|
||||
set_vi_handler(6, ltq_hw4_irqdispatch);
|
||||
set_vi_handler(7, ltq_hw5_irqdispatch);
|
||||
}
|
||||
|
||||
for (i = INT_NUM_IRQ0;
|
||||
i <= (INT_NUM_IRQ0 + (5 * INT_NUM_IM_OFFSET)); i++)
|
||||
if ((i == LTQ_EIU_IR0) || (i == LTQ_EIU_IR1) ||
|
||||
(i == LTQ_EIU_IR2))
|
||||
irq_set_chip_and_handler(i, <q_eiu_type,
|
||||
handle_level_irq);
|
||||
/* EIU3-5 only exist on ar9 and vr9 */
|
||||
else if (((i == LTQ_EIU_IR3) || (i == LTQ_EIU_IR4) ||
|
||||
(i == LTQ_EIU_IR5)) && (ltq_is_ar9() || ltq_is_vr9()))
|
||||
irq_set_chip_and_handler(i, <q_eiu_type,
|
||||
handle_level_irq);
|
||||
else
|
||||
irq_set_chip_and_handler(i, <q_irq_type,
|
||||
handle_level_irq);
|
||||
|
||||
#if !defined(CONFIG_MIPS_MT_SMP) && !defined(CONFIG_MIPS_MT_SMTC)
|
||||
set_c0_status(IE_IRQ0 | IE_IRQ1 | IE_IRQ2 |
|
||||
IE_IRQ3 | IE_IRQ4 | IE_IRQ5);
|
||||
#else
|
||||
set_c0_status(IE_SW0 | IE_SW1 | IE_IRQ0 | IE_IRQ1 |
|
||||
IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5);
|
||||
#endif
|
||||
}
|
||||
|
||||
unsigned int __cpuinit get_c0_compare_int(void)
|
||||
{
|
||||
return CP0_LEGACY_COMPARE_IRQ;
|
||||
}
|
||||
|
|
@ -0,0 +1,71 @@
|
|||
/*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License version 2 as published
|
||||
* by the Free Software Foundation.
|
||||
*
|
||||
* Copyright (C) 2010 John Crispin <blogic@openwrt.org>
|
||||
*/
|
||||
|
||||
#include <linux/module.h>
|
||||
#include <linux/clk.h>
|
||||
#include <asm/bootinfo.h>
|
||||
#include <asm/time.h>
|
||||
|
||||
#include <lantiq.h>
|
||||
|
||||
#include "prom.h"
|
||||
#include "clk.h"
|
||||
|
||||
static struct ltq_soc_info soc_info;
|
||||
|
||||
unsigned int ltq_get_cpu_ver(void)
|
||||
{
|
||||
return soc_info.rev;
|
||||
}
|
||||
EXPORT_SYMBOL(ltq_get_cpu_ver);
|
||||
|
||||
unsigned int ltq_get_soc_type(void)
|
||||
{
|
||||
return soc_info.type;
|
||||
}
|
||||
EXPORT_SYMBOL(ltq_get_soc_type);
|
||||
|
||||
const char *get_system_type(void)
|
||||
{
|
||||
return soc_info.sys_type;
|
||||
}
|
||||
|
||||
void prom_free_prom_memory(void)
|
||||
{
|
||||
}
|
||||
|
||||
static void __init prom_init_cmdline(void)
|
||||
{
|
||||
int argc = fw_arg0;
|
||||
char **argv = (char **) KSEG1ADDR(fw_arg1);
|
||||
int i;
|
||||
|
||||
for (i = 0; i < argc; i++) {
|
||||
char *p = (char *) KSEG1ADDR(argv[i]);
|
||||
|
||||
if (p && *p) {
|
||||
strlcat(arcs_cmdline, p, sizeof(arcs_cmdline));
|
||||
strlcat(arcs_cmdline, " ", sizeof(arcs_cmdline));
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void __init prom_init(void)
|
||||
{
|
||||
struct clk *clk;
|
||||
|
||||
ltq_soc_detect(&soc_info);
|
||||
clk_init();
|
||||
clk = clk_get(0, "cpu");
|
||||
snprintf(soc_info.sys_type, LTQ_SYS_TYPE_LEN - 1, "%s rev1.%d",
|
||||
soc_info.name, soc_info.rev);
|
||||
clk_put(clk);
|
||||
soc_info.sys_type[LTQ_SYS_TYPE_LEN - 1] = '\0';
|
||||
pr_info("SoC: %s\n", soc_info.sys_type);
|
||||
prom_init_cmdline();
|
||||
}
|
||||
|
|
@ -0,0 +1,24 @@
|
|||
/*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License version 2 as published
|
||||
* by the Free Software Foundation.
|
||||
*
|
||||
* Copyright (C) 2010 John Crispin <blogic@openwrt.org>
|
||||
*/
|
||||
|
||||
#ifndef _LTQ_PROM_H__
|
||||
#define _LTQ_PROM_H__
|
||||
|
||||
#define LTQ_SYS_TYPE_LEN 0x100
|
||||
|
||||
struct ltq_soc_info {
|
||||
unsigned char *name;
|
||||
unsigned int rev;
|
||||
unsigned int partnum;
|
||||
unsigned int type;
|
||||
unsigned char sys_type[LTQ_SYS_TYPE_LEN];
|
||||
};
|
||||
|
||||
extern void ltq_soc_detect(struct ltq_soc_info *i);
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,41 @@
|
|||
/*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License version 2 as published
|
||||
* by the Free Software Foundation.
|
||||
*
|
||||
* Copyright (C) 2010 John Crispin <blogic@openwrt.org>
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/ioport.h>
|
||||
#include <asm/bootinfo.h>
|
||||
|
||||
#include <lantiq_soc.h>
|
||||
|
||||
void __init plat_mem_setup(void)
|
||||
{
|
||||
/* assume 16M as default incase uboot fails to pass proper ramsize */
|
||||
unsigned long memsize = 16;
|
||||
char **envp = (char **) KSEG1ADDR(fw_arg2);
|
||||
|
||||
ioport_resource.start = IOPORT_RESOURCE_START;
|
||||
ioport_resource.end = IOPORT_RESOURCE_END;
|
||||
iomem_resource.start = IOMEM_RESOURCE_START;
|
||||
iomem_resource.end = IOMEM_RESOURCE_END;
|
||||
|
||||
set_io_port_base((unsigned long) KSEG1);
|
||||
|
||||
while (*envp) {
|
||||
char *e = (char *)KSEG1ADDR(*envp);
|
||||
if (!strncmp(e, "memsize=", 8)) {
|
||||
e += 8;
|
||||
if (strict_strtoul(e, 0, &memsize))
|
||||
pr_warn("bad memsize specified\n");
|
||||
}
|
||||
envp++;
|
||||
}
|
||||
memsize *= 1024 * 1024;
|
||||
add_memory_region(0x00000000, memsize, BOOT_MEM_RAM);
|
||||
}
|
||||
Loading…
Reference in New Issue