drm/radeon: use status regs to determine what to reset (cayman)
When we attempt the reset the GPU, look at the status registers to determine what blocks need to be reset. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Alex Deucher
parent
a65a4369f7
commit
168757ea85
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@ -2349,9 +2349,13 @@ void evergreen_print_gpu_status_regs(struct radeon_device *rdev)
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RREG32(CP_STAT));
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dev_info(rdev->dev, " R_00D034_DMA_STATUS_REG = 0x%08X\n",
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RREG32(DMA_STATUS_REG));
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if (rdev->family >= CHIP_CAYMAN) {
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dev_info(rdev->dev, " R_00D834_DMA_STATUS_REG = 0x%08X\n",
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RREG32(DMA_STATUS_REG + 0x800));
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}
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}
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static bool evergreen_is_display_hung(struct radeon_device *rdev)
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bool evergreen_is_display_hung(struct radeon_device *rdev)
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{
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u32 crtc_hung = 0;
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u32 crtc_status[6];
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@ -34,6 +34,7 @@
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#include "ni_reg.h"
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#include "cayman_blit_shaders.h"
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extern bool evergreen_is_display_hung(struct radeon_device *rdev);
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extern void evergreen_print_gpu_status_regs(struct radeon_device *rdev);
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extern void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save);
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extern void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save);
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@ -1311,21 +1312,86 @@ void cayman_dma_fini(struct radeon_device *rdev)
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radeon_ring_fini(rdev, &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX]);
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}
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static int cayman_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
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static u32 cayman_gpu_check_soft_reset(struct radeon_device *rdev)
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{
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u32 reset_mask = 0;
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u32 tmp;
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/* GRBM_STATUS */
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tmp = RREG32(GRBM_STATUS);
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if (tmp & (PA_BUSY | SC_BUSY |
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SH_BUSY | SX_BUSY |
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TA_BUSY | VGT_BUSY |
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DB_BUSY | CB_BUSY |
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GDS_BUSY | SPI_BUSY |
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IA_BUSY | IA_BUSY_NO_DMA))
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reset_mask |= RADEON_RESET_GFX;
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if (tmp & (CF_RQ_PENDING | PF_RQ_PENDING |
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CP_BUSY | CP_COHERENCY_BUSY))
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reset_mask |= RADEON_RESET_CP;
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if (tmp & GRBM_EE_BUSY)
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reset_mask |= RADEON_RESET_GRBM | RADEON_RESET_GFX | RADEON_RESET_CP;
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/* DMA_STATUS_REG 0 */
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tmp = RREG32(DMA_STATUS_REG + DMA0_REGISTER_OFFSET);
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if (!(tmp & DMA_IDLE))
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reset_mask |= RADEON_RESET_DMA;
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/* DMA_STATUS_REG 1 */
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tmp = RREG32(DMA_STATUS_REG + DMA1_REGISTER_OFFSET);
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if (!(tmp & DMA_IDLE))
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reset_mask |= RADEON_RESET_DMA1;
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/* SRBM_STATUS2 */
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tmp = RREG32(SRBM_STATUS2);
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if (tmp & DMA_BUSY)
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reset_mask |= RADEON_RESET_DMA;
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if (tmp & DMA1_BUSY)
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reset_mask |= RADEON_RESET_DMA1;
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/* SRBM_STATUS */
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tmp = RREG32(SRBM_STATUS);
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if (tmp & (RLC_RQ_PENDING | RLC_BUSY))
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reset_mask |= RADEON_RESET_RLC;
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if (tmp & IH_BUSY)
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reset_mask |= RADEON_RESET_IH;
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if (tmp & SEM_BUSY)
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reset_mask |= RADEON_RESET_SEM;
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if (tmp & GRBM_RQ_PENDING)
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reset_mask |= RADEON_RESET_GRBM;
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if (tmp & VMC_BUSY)
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reset_mask |= RADEON_RESET_VMC;
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if (tmp & (MCB_BUSY | MCB_NON_DISPLAY_BUSY |
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MCC_BUSY | MCD_BUSY))
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reset_mask |= RADEON_RESET_MC;
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if (evergreen_is_display_hung(rdev))
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reset_mask |= RADEON_RESET_DISPLAY;
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/* VM_L2_STATUS */
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tmp = RREG32(VM_L2_STATUS);
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if (tmp & L2_BUSY)
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reset_mask |= RADEON_RESET_VMC;
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return reset_mask;
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}
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static void cayman_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
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{
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struct evergreen_mc_save save;
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u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
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u32 tmp;
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int ret = 0;
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if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
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reset_mask &= ~(RADEON_RESET_GFX | RADEON_RESET_COMPUTE | RADEON_RESET_CP);
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if (RREG32(DMA_STATUS_REG) & DMA_IDLE)
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reset_mask &= ~RADEON_RESET_DMA;
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if (reset_mask == 0)
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return 0;
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return;
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dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask);
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@ -1354,7 +1420,9 @@ static int cayman_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
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tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET);
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tmp &= ~DMA_RB_ENABLE;
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WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp);
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}
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if (reset_mask & RADEON_RESET_DMA1) {
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/* dma1 */
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tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET);
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tmp &= ~DMA_RB_ENABLE;
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@ -1383,7 +1451,31 @@ static int cayman_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
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}
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if (reset_mask & RADEON_RESET_DMA)
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srbm_soft_reset |= SOFT_RESET_DMA | SOFT_RESET_DMA1;
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srbm_soft_reset |= SOFT_RESET_DMA;
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if (reset_mask & RADEON_RESET_DMA1)
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srbm_soft_reset |= SOFT_RESET_DMA1;
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if (reset_mask & RADEON_RESET_DISPLAY)
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srbm_soft_reset |= SOFT_RESET_DC;
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if (reset_mask & RADEON_RESET_RLC)
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srbm_soft_reset |= SOFT_RESET_RLC;
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if (reset_mask & RADEON_RESET_SEM)
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srbm_soft_reset |= SOFT_RESET_SEM;
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if (reset_mask & RADEON_RESET_IH)
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srbm_soft_reset |= SOFT_RESET_IH;
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if (reset_mask & RADEON_RESET_GRBM)
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srbm_soft_reset |= SOFT_RESET_GRBM;
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if (reset_mask & RADEON_RESET_VMC)
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srbm_soft_reset |= SOFT_RESET_VMC;
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if (reset_mask & RADEON_RESET_MC)
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srbm_soft_reset |= SOFT_RESET_MC;
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if (grbm_soft_reset) {
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tmp = RREG32(GRBM_SOFT_RESET);
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@ -1419,32 +1511,26 @@ static int cayman_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
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evergreen_mc_resume(rdev, &save);
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udelay(50);
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#if 0
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if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE | RADEON_RESET_CP)) {
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if (RREG32(GRBM_STATUS) & GUI_ACTIVE)
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ret = -EAGAIN;
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}
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if (reset_mask & RADEON_RESET_DMA) {
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if (!(RREG32(DMA_STATUS_REG) & DMA_IDLE))
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ret = -EAGAIN;
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}
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#endif
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if (!ret)
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r600_set_bios_scratch_engine_hung(rdev, false);
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evergreen_print_gpu_status_regs(rdev);
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return 0;
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}
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int cayman_asic_reset(struct radeon_device *rdev)
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{
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return cayman_gpu_soft_reset(rdev, (RADEON_RESET_GFX |
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RADEON_RESET_COMPUTE |
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RADEON_RESET_DMA |
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RADEON_RESET_CP));
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u32 reset_mask;
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reset_mask = cayman_gpu_check_soft_reset(rdev);
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if (reset_mask)
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r600_set_bios_scratch_engine_hung(rdev, true);
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cayman_gpu_soft_reset(rdev, reset_mask);
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reset_mask = cayman_gpu_check_soft_reset(rdev);
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if (!reset_mask)
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r600_set_bios_scratch_engine_hung(rdev, false);
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return 0;
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}
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/**
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@ -49,6 +49,16 @@
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#define RINGID(x) (((x) & 0x3) << 0)
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#define VMID(x) (((x) & 0x7) << 0)
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#define SRBM_STATUS 0x0E50
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#define RLC_RQ_PENDING (1 << 3)
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#define GRBM_RQ_PENDING (1 << 5)
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#define VMC_BUSY (1 << 8)
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#define MCB_BUSY (1 << 9)
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#define MCB_NON_DISPLAY_BUSY (1 << 10)
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#define MCC_BUSY (1 << 11)
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#define MCD_BUSY (1 << 12)
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#define SEM_BUSY (1 << 14)
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#define RLC_BUSY (1 << 15)
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#define IH_BUSY (1 << 17)
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#define SRBM_SOFT_RESET 0x0E60
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#define SOFT_RESET_BIF (1 << 1)
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@ -68,6 +78,10 @@
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#define SOFT_RESET_REGBB (1 << 22)
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#define SOFT_RESET_ORB (1 << 23)
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#define SRBM_STATUS2 0x0EC4
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#define DMA_BUSY (1 << 5)
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#define DMA1_BUSY (1 << 6)
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#define VM_CONTEXT0_REQUEST_RESPONSE 0x1470
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#define REQUEST_TYPE(x) (((x) & 0xf) << 0)
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#define RESPONSE_TYPE_MASK 0x000000F0
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