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iio: adc: ltc2496: Fix alignment for DMA safety 

____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_DMA_MINALIGN definition.

Update the comment to include 'may'.

Fixes: e4c5c4dfaa ("iio: adc: new driver to support Linear technology's ltc2496")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Acked-by: Nuno Sá <nuno.sa@analog.com>
Link: https://lore.kernel.org/r/20220508175712.647246-22-jic23@kernel.org
This commit is contained in:
Jonathan Cameron 2022-05-08 18:56:01 +01:00
parent 48e4ae96b0
commit 1673b7ca2d
1 changed files with 2 additions and 2 deletions
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4
drivers/iio/adc/ltc2496.c
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@ -24,10 +24,10 @@ struct ltc2496_driverdata {
struct spi_device *spi;
/*
* DMA (thus cache coherency maintenance) requires the
* DMA (thus cache coherency maintenance) may require the
* transfer buffers to live in their own cache lines.
*/
unsigned char rxbuf[3] ____cacheline_aligned;
unsigned char rxbuf[3] __aligned(IIO_DMA_MINALIGN);
unsigned char txbuf[3];
};