hollalinux
/
linux-sg2042
mirror of https://github.com/sophgo/linux-riscv.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

[MIPS] tlbex: Cleanup handling of R2 hazards in TLB handlers. 

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Ralf Baechle 2008-01-29 10:14:54 +00:00
parent 6920df4025
commit 161548bf35
1 changed files with 6 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
arch/mips/mm/tlbex.c
View File

@ -860,6 +860,12 @@ static __init void build_tlb_write_entry(u32 **p, struct label **l,
case tlb_indexed: tlbw = i_tlbwi; break;
}
if (cpu_has_mips_r2) {
i_ehb(p);
tlbw(p);
return;
}
switch (current_cpu_type()) {
case CPU_R4000PC:
case CPU_R4000SC:
@ -935,14 +941,6 @@ static __init void build_tlb_write_entry(u32 **p, struct label **l,
tlbw(p);
break;
case CPU_4KEC:
case CPU_24K:
case CPU_34K:
case CPU_74K:
i_ehb(p);
tlbw(p);
break;
case CPU_RM9000:
/*
* When the JTLB is updated by tlbwi or tlbwr, a subsequent