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arm64: Expose ESR_EL1 information to user when SIGSEGV/SIGBUS 

This information is useful for instruction emulators to detect
read/write and access size without having to decode the faulting
instruction. The current patch exports it via sigcontext (struct
esr_context) and is only valid for SIGSEGV and SIGBUS.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
This commit is contained in:
Catalin Marinas 2013-09-16 15:19:27 +01:00
parent 0e0276d1e1
commit 15af1942dd
2 changed files with 17 additions and 0 deletions
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7
arch/arm64/include/uapi/asm/sigcontext.h
View File

@ -53,5 +53,12 @@ struct fpsimd_context {
__uint128_t vregs[32];
};
/* ESR_EL1 context */
#define ESR_MAGIC 0x45535201
struct esr_context {
struct _aarch64_ctx head;
u64 esr;
};
#endif /* _UAPI__ASM_SIGCONTEXT_H */

10
arch/arm64/kernel/signal.c
View File

@ -194,6 +194,16 @@ static int setup_sigframe(struct rt_sigframe __user *sf,
aux += sizeof(*fpsimd_ctx);
}
/* fault information, if valid */
if (current->thread.fault_code) {
struct esr_context *esr_ctx =
container_of(aux, struct esr_context, head);
__put_user_error(ESR_MAGIC, &esr_ctx->head.magic, err);
__put_user_error(sizeof(*esr_ctx), &esr_ctx->head.size, err);
__put_user_error(current->thread.fault_code, &esr_ctx->esr, err);
aux += sizeof(*esr_ctx);
}
/* set the "end" magic */
end = aux;
__put_user_error(0, &end->magic, err);